CN101546700A - Electrode structure and substrate processing apparatus - Google Patents
Electrode structure and substrate processing apparatus Download PDFInfo
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- CN101546700A CN101546700A CN200910129460A CN200910129460A CN101546700A CN 101546700 A CN101546700 A CN 101546700A CN 200910129460 A CN200910129460 A CN 200910129460A CN 200910129460 A CN200910129460 A CN 200910129460A CN 101546700 A CN101546700 A CN 101546700A
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- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000012545 processing Methods 0.000 title abstract description 27
- 238000000034 method Methods 0.000 claims description 37
- 238000011282 treatment Methods 0.000 claims description 30
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 description 19
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 16
- 238000001020 plasma etching Methods 0.000 description 15
- 239000007921 spray Substances 0.000 description 15
- 150000001768 cations Chemical class 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 7
- 239000002826 coolant Substances 0.000 description 4
- 230000008676 import Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000011148 porous material Substances 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004087 circulation Effects 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
- H01J37/32155—Frequency modulation
- H01J37/32165—Plural frequencies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32541—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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Abstract
An electrode structure capable of adequately increasing an electron density in a processing space at a part facing a circumferential edge portion of a substrate. In a processing chamber of a substrate processing apparatus that performs RIE processing on a wafer, an upper electrode of the electrode structure is disposed to face the wafer placed on a susceptor inside the processing chamber. The upper electrode includes an inner electrode facing a central portion of the wafer and an outer electrode facing the circumferential edge portion of the wafer. The inner and outer electrodes are connected with first and second DC power sources, respectively. The outer electrode has its first secondary electron emission surface extending parallel to the wafer and its second secondary electron emission surface obliquely extending relative to the first secondary electron emission surface.
Description
Technical field
The present invention relates to electrode structure and substrate board treatment, particularly relate to the electrode structure that in the process chamber of substrate board treatment, disposes and connect DC power supply.
Background technology
The substrate board treatment of implementing plasma treatment as the wafer of substrate is comprised: accommodate wafer process chamber, be configured in and be used for the mounting table of mounting wafer in this process chamber and the spray head of handling gas is supplied with in the processing space in process chamber.In this substrate board treatment, on mounting table, be connected with high frequency electric source, mounting table applies High frequency power to handling the space, makes to supply to the processing gas of handling the space and encouraged by High frequency power and become plasma (cation, electronics).
Because the plasma distribution in the processing space has very big influence to the result of the plasma treatment of wafer, therefore, preferred initiatively article on plasma body distributes and controls, with it accordingly, in order to control plasma distribution, particularly electron density distribution applies direct voltage to spray head.
Spray head is being applied under the situation of direct voltage, as the structure member of spray head, be connected with DC power supply to handling the discoideus top electrode plate of exposing in the space.At this, when applying negative direct voltage to spray head, this spray head only attracts the cation in the plasma.Because direct voltage is different with high frequency voltage, its current potential does not change in time, so cation attracted to spray head constantly.And the cation that attracted to spray head is launched secondary electron from the constituting atom of this spray head.Its result is in the portions of electronics density rising (for example, with reference to patent documentation 1) relative with the spray head of handling the space.
Patent documentation 1: the Japan Patent spy opens communique the 2006-No. 270019
Yet, there is the influence of the shape be subjected to process chamber etc. in electron density distribution and the uneven situation that becomes in handling the space, but under the situation that top electrode plate is made of a conductive plate, even owing to the electron density that top electrode plate is applied the whole parts in also just relative with the spray head processing space of direct voltage rises, so can not eliminate the inhomogeneous of electron density distribution.Its result, with the opposed part of the circumference of wafer, electron density reduces in handling the space, under the situation of etch processes, exists the etch-rate of the circumference of wafer to compare the problem that descends to some extent with the central part of wafer.
Summary of the invention
The objective of the invention is to, a kind of electrode structure and substrate board treatment that with the opposed part of the circumference of substrate electron density is risen in handling the space is provided.
To achieve these goals, the electrode structure of a first aspect of the present invention, it is configured in implements in the process chamber that substrate board treatment possessed of plasma treatment substrate, in this process chamber be positioned in mounting table on aforesaid substrate mutually opposed, it is characterized in that: this electrode structure comprise with the opposed medial electrode of the central part of aforesaid substrate and with the opposed lateral electrode of the circumference of aforesaid substrate, above-mentioned medial electrode is connected with first DC power supply, and above-mentioned lateral electrode is connected with second DC power supply, and above-mentioned lateral electrode has parallel with aforesaid substrate first and with respect to second of this first face tilt.
The electrode structure of a second aspect of the present invention is characterised in that: in the electrode structure of first aspect, and above-mentioned first and above-mentioned second circumference that points to aforesaid substrate.
To achieve these goals, the substrate board treatment of a third aspect of the present invention, it implements plasma treatment to substrate, it is characterized in that, comprising: the process chamber of accommodating aforesaid substrate; Be configured in mounting table in this process chamber, that be used for the mounting aforesaid substrate; Be configured in the above-mentioned process chamber, and with the opposed electrode structure of aforesaid substrate that is positioned on the above-mentioned mounting table, above-mentioned electrode structure comprise with the opposed medial electrode of the central part of aforesaid substrate and with the opposed lateral electrode of the circumference of aforesaid substrate, above-mentioned medial electrode is connected with first DC power supply, and above-mentioned lateral electrode is connected with second DC power supply, and above-mentioned lateral electrode has parallel with aforesaid substrate first and with respect to second of this first face tilt.
According to the electrode structure of first aspect present invention and the substrate board treatment of the third aspect, be applied in direct voltage thereby be connected second DC power supply with the opposed lateral electrode of the circumference of substrate.When lateral electrode was applied in direct voltage, this lateral electrode attracted the cation in the plasma to launch secondary electron.Its result can make the electron density of handling in the space with the opposed part of circumference of substrate rise.In addition, the lateral electrode that connects second DC power supply has parallel with substrate first and with respect to second of this first face tilt, goes out secondary electron from first and second surface launching.Because second with respect to first face tilt, thus in handling the space with the opposed part of the circumference of substrate, overlapping from the secondary electron that second surface launching goes out with the secondary electron that goes out from first surface launching.Its result can fully rise electron density with the opposed part of the circumference of substrate in handling the space.
According to the electrode structure of second aspect present invention, because the circumference of first and second sensing substrate, so secondary electron that goes out from first surface launching and the secondary electron that goes out from second surface launching are overlapping directly over the circumference of substrate.Its result can make electron density reliably and fully rise directly over the circumference of substrate.
Description of drawings
Fig. 1 is the sectional view of structure of representing the substrate board treatment of embodiments of the present invention briefly.
Fig. 2 is near the amplification sectional view of the structure the lateral electrode of the upper electrode in the presentation graphs 1 briefly.
Fig. 3 is the chart of relation of etch-rate of the circumference of expression lateral electrode surface area of lateral electrode and wafer.
Fig. 4 is the chart of the etch-rate climbing of the value of the direct voltage of representing that electrode laterally applies when increasing.
Fig. 5 is the chart of relation of etch-rate of the circumference of lateral electrode surface area in expression embodiments of the invention 1 and the comparative example 1,2 and wafer.
Label declaration
The W wafer
10 substrate board treatments
11 process chambers
12 pedestals
31 upper electrodes
34 medial electrodes
35 lateral electrodes
35a the 1st secondary emission surface
35b the 2nd secondary emission surface
37 first DC power supply
38 second DC power supply
Embodiment
Below, with reference to accompanying drawing embodiments of the present invention are described.
Fig. 1 is the sectional view of structure of representing the substrate board treatment of present embodiment briefly, and Fig. 2 is near the amplification sectional view of the structure the lateral electrode of the upper electrode in the presentation graphs 1 briefly.This substrate board treatment constitutes and uses plasma that the semiconductor wafer as substrate is implemented RIE (Reactive Ion Etching: active-ion-etch).
In Fig. 1 and Fig. 2, substrate board treatment 10 comprises: the process chamber 11 of drum; Be configured in this process chamber 11, be used for mounting for example diameter be the columned pedestal 12 of semiconductor wafer (following simply be called " the wafer ") W of 300mm as mounting table.
In substrate board treatment 10,, form and play the exhaust flow path 13 that is discharged to the effect of the outer stream of process chamber 11 as gas processing space S described later by the side of the madial wall and the pedestal 12 of process chamber 11.Dispose exhaustion plate (air exhaust loop) 14 midway at this exhaust flow path 13.
(Turbo Mo1ecular Pump: turbomolecular pump) (not shown), (Dry Pump: dry pump) (not shown), these pumps are to vacuumizing in the process chamber 11 to implement decompression to be connected with DP on the blast pipe 18 to be connected with TMP on the blast pipe 17.Particularly, DP will process chamber be decompressed to medium vacuum state (for example, 1.3 * 10Pa (0.1Torr) is following) from atmospheric pressure in 11, and TMP cooperates with DP and will be decompressed in the process chamber 11 than the medium vacuum state high vacuum state of low-pressure (for example, 1.3 * 10 more
-3Pa (1.0 * 10
-5Torr) following).Wherein, the pressure in the process chamber 11 is controlled by APC valve (not shown).
On the pedestal 12 in process chamber 11, be connected first high frequency electric source 19 and second high frequency electric source 20 with second adaptation 22 by first adaptation 21 respectively.First high frequency electric source 19 applies than higher frequency, for example applies the High frequency power of 60MHz to pedestal 12, and second high frequency electric source 20 applies lower frequency, for example applies the High frequency power of 2MHz to pedestal 12.Thus, pedestal 12 plays the effect that applies the lower electrode of High frequency power as the processing space S between this pedestal 12 and spray head described later 30.
In addition, on pedestal 12, dispose the discoideus electrostatic chuck 24 that constitutes by the insulating properties material that has electrostatic attraction electrode plate 23 in inside.During the mounting wafer W, this wafer W is configured on the electrostatic chuck 24 on pedestal 12.In this electrostatic chuck 24, on electrostatic attraction electrode plate 23, be electrically connected with DC power supply 25.When on electrostatic attraction electrode plate 23, applying positive direct voltage, go up at the face (hereinafter referred to as " back side ") of electrostatic chuck 24 1 sides of wafer W and to produce negative voltage, between the back side of electrostatic attraction electrode plate 23 and wafer W, produce potential difference, Coulomb force or Johnson of being caused by this potential difference draw Buick power, wafer W is adsorbed remains on the electrostatic chuck 24.
In addition, on pedestal 12, be adsorbed the mode of the wafer W of maintenance with encirclement, mounting has circular focusing ring 26.Focusing ring 26 by electroconductive component for example silicon constitute, make the surperficial pinching of plasma to wafer W, improve the RIE treatment effeciency.
In addition, in the inside of pedestal 12, for example be provided with the cooling medium chamber 27 of the ring-type of extending at circumferencial direction.Supply with for example cooling water, GALDEN (registered trade mark) liquid with pipe arrangement 28 to these cooling medium chamber 27 circulations by coolant from cooling unit (not shown).By the pedestal 12 of the coolant of this low temperature cooling across electrostatic chuck 24 cooling wafer W and focusing rings 26.
The top absorption of electrostatic chuck 24 keeps part (hereinafter referred to as " the adsorption plane ") opening of wafer W that a plurality of heat-conducting gas supply holes 29 are arranged.These a plurality of heat-conducting gas supply holes 29 will be supplied with the gap at the back side of adsorption plane and wafer W as the helium (He) of heat-conducting gas by heat-conducting gas supply hole 29.The helium in gap that is fed into the back side of adsorption plane and wafer W is delivered to electrostatic chuck 24 effectively with the heat of wafer W.
Dispose spray head 30 at the top of process chamber 11.This spray head 30 comprises: to handling that space S is exposed and with the insulation board 32 that is positioned in wafer W (hereinafter referred to as " mounting wafer W ") opposed upper electrode 31 (electrode structure) on the pedestal 12, be made of the insulating properties parts, by the electrode hanging body (electrode fixing body) 33 of these insulation board 32 hangings (install, hang and install) upper electrode 31, upper electrode 31, insulation board 32 and electrode hanging body 33 are overlapping successively.
Electrode hanging body 33 has surge chamber 39 in inside.Surge chamber 39 is columned spaces, by circular seal for example O shape ring 40 be divided into inboard surge chamber 39a and outside surge chamber 39b.
Inboard surge chamber 39a is connected with processing gas introduction tube 41, and outside surge chamber 39b is connected with and handles gas introduction tube 42, and surge chamber 39a and outside surge chamber 39b import processing gas to the inside respectively to handle gas introduction tube 41,42.
Handle gas introduction tube 41,42 because have flow controller (MFC) (not shown) respectively, thus to the inside the flow of the processing gas that imports of surge chamber 39a and outside surge chamber 39b by control independently respectively.In addition, surge chamber 39 is communicated with the processing space S by the pore 43 of electrode hanging body 33, the pore 44 of insulation board 32 and the pore 36 of upper electrode 31, and the processing gas that imports inboard surge chamber 39a and outside surge chamber 39b is fed into the processing space S.At this moment, the distribution that comes the processing gas of control and treatment space S by the flow of adjusting the processing gas that imports inboard surge chamber 39a and outside surge chamber 39b.
In this substrate board treatment 10, when the mounting wafer W is implemented the RIE processing, spray head 30 will be handled gas and supply with the processing space S, to handling the High frequency power that space S applies 60MHz, and second high frequency electric source 20 applies the High frequency power of 2MHz to first high frequency electric source 19 to pedestal 12 by pedestal 12.At this moment, processing gas becomes plasma by the High frequency power excitation of 60MHz.In addition, because the High frequency power of 2MHz produces bias voltage at pedestal 12, the cation in the plasma, electronics attracted to the surface of mounting wafer W, this mounting wafer W is implemented RIE handle.
But, in order in handling the space, to control electron density distribution partly, research and development have with upper electrode be divided into the opposed medial electrode of the central part of wafer and with the opposed lateral electrode of the circumference of wafer, and independently medial electrode and lateral electrode are applied the method for the direct voltage of negative polarity respectively.In the method, lateral electrode is applied the direct voltage different with the value of medial electrode, independently in the control and treatment space with the electron density of the opposed part of lateral electrode and with the electron density of the opposed part of medial electrode.
About this method, the present inventor etc. draw to draw a conclusion: by the experiment of RIE processing, when increasing the surface area (hereinafter referred to as " lateral electrode surface area ") of lateral electrode and the opposed faces mutually in processing space, handle in the space and rise with the electron density of the opposed part of the opposite face of lateral electrode (hereinafter referred to as " the mutually opposed part of lateral electrode "), its result, the etch-rate rising (with reference to Fig. 3) of the circumference of wafer.
In addition, the present inventor etc. also draw following conclusion: when increase is applied to the value of the direct voltage of lateral electrode, as expected, the electron density of the mutually opposed part of lateral electrode rises really, its result, and the etch-rate of the circumference of wafer rises.Particularly, value at the direct voltage that will be applied to medial electrode maintains under the state of 300V, the absolute value that makes the direct voltage that is applied to lateral electrode when 300V rises to 900V, the etch-rate that confirms the circumference of wafer about 7% (with reference to Fig. 4) that rise.
But, in common substrate board treatment, owing to have other process chamber configurations parts at the periphery of lateral electrode, so be difficult to mostly the lateral electrode surface area is increased to certain more than the value.In addition, because the restriction of the performance of DC power supply etc. also is difficult to make the value of the DC power supply that is applied to lateral electrode to rise to certain more than the value mostly.That is, be in handling the space make fully rise difficulty normally of electron density with the opposed part of the circumference of wafer.
In substrate board treatment 10, corresponding to this, upper electrode 31 have with the opposed medial electrode of the central part of mounting wafer W 34 and surround this medial electrode 34 and with the opposed lateral electrode 35 of the circumference of mounting wafer W, the 2nd secondary emission surface 35b (second face) that lateral electrode 35 has the 1st secondary emission surface 35a (first face) parallel with the mounting wafer W and tilts towards the mounting wafer W with respect to the 1st secondary emission surface 35a.The 1st secondary emission surface 35a and lateral electrode 35b point to the circumference of mounting wafer W respectively.
At this, medial electrode 34 for example is made of the disk-like member of diameter 300mm, has a plurality of pores 36 that connect on thickness direction.Lateral electrode 35 is made of the circle shape part of external diameter 380mm and internal diameter 300mm.Medial electrode 34 and lateral electrode 35 by conductivity or semiconduction material for example monocrystalline silicon constitute.
In addition, in upper electrode 31, medial electrode 34 is connected with first DC power supply 37, and lateral electrode 35 is connected with second DC power supply 38, and medial electrode 34 and lateral electrode 35 are applied direct voltage respectively independently.
In the substrate board treatment 10, during the RIE processing, the medial electrode 34 and the lateral electrode 35 of first DC power supply 37 and 38 pairs of upper electrodes 31 of second DC power supply apply negative direct voltage.At this moment, the cation in the plasma in the processing space S attracted to medial electrode 34, lateral electrode 35.The cation that attracted to is given energy to the electronics in the constituting atom of medial electrode 34 and lateral electrode 35, when the energy that is endowed surpassed certain value, the electronics in the constituting atom emitted from the surface of medial electrode 34, the 1st secondary emission surface 35a and the 2nd secondary emission surface 35b of lateral electrode 35 as secondary electron.
As mentioned above, medial electrode 34 is a disk-like member, because only parallel with mounting wafer W surface exposes to handling space S, so the central part from the secondary electron of this surface emitting from the mounting wafer W roughly evenly distributes to circumference.Its result, spread all over the mounting wafer W whole promote RIE to handle.
The 1st secondary emission surface 35a of lateral electrode 35 and the 2nd secondary emission surface 35b are as mentioned above, owing to all point to the circumference of mounting wafer W, so the secondary electron that emits from the 1st secondary emission surface 35a and the 2nd secondary emission surface 35b is overlapping directly over the circumference of mounting wafer W.Its result can make electron density fully rise directly over the circumference of mounting wafer W, and the RIE that promotes at the circumference of mounting wafer W handles.
Wherein, the CPU control of the control part (not shown) that possessed by substrate board treatment 10 of the action of each structure member of above-mentioned substrate board treatment 10.
According to the upper electrode 31 as electrode structure of present embodiment, with the opposed lateral electrode 35 of the circumference of mounting wafer W on be connected with second DC power supply 38 and be applied in direct voltage.When lateral electrode 35 was applied direct voltage, this lateral electrode 35 attracted the cation in the plasma and launches secondary electron.Its result, can make the mounting wafer W of handling space S circumference directly over electron density fully rise.In addition, the lateral electrode 35 that connects second DC power supply 38 has the 1st secondary emission surface 35a parallel with the mounting wafer W and with respect to the 2nd secondary emission surface 35b of the 1st secondary emission surface 35a towards the inclination of mounting wafer W, launches secondary electron from the 1st secondary emission surface 35a and the 2nd secondary emission surface 35b.The 1st secondary emission surface 35a and the 2nd secondary emission surface 35b are owing to all point to the circumference of mounting wafer W, so can make the mounting wafer W circumference directly over electron density fully rise, the RIE that can promote at the circumference of mounting wafer W handles.
For above-mentioned upper electrode 31, owing to can not increase the area with opposite face wafer W lateral electrode 35 make the mounting wafer W circumference directly over electron density fully rise, therefore do not need to strengthen lateral electrode 35.Its result can cut down the use amount of the monocrystalline silicon of high price, thereby can reduce the manufacturing cost of upper electrode 31.
In addition, in above-mentioned upper electrode 31, the 1st secondary emission surface 35a not only, the 2nd secondary emission surface 35b also points to the circumference of mounting wafer W, but the 2nd secondary emission surface 35b also can not point to the circumference of mounting wafer W, for example, the 2nd secondary emission surface 35b also can be vertical with respect to the 1st secondary emission surface 35a.Under these circumstances, also overlapping because handle the secondary electron that emits with the opposed part of the circumference of mounting wafer W in the space S, so electron density is fully risen with the opposed part of the circumference of mounting wafer W.
And the 2nd secondary emission surface 35b is unnecessary to be the plane, also can be the parabola that points to the circumference of mounting wafer W.Under these circumstances, can launch secondary electron in the circumference concentrated area from the 2nd secondary emission surface 35b towards the mounting wafer W, thus can further make the mounting wafer W circumference directly over electron density fully rise.
Wherein, in above-mentioned present embodiment, the substrate of implementing etch processes is a semiconductor wafer W, but the substrate of implementing etch processes is not limited thereto, liquid crystal display), FPD (Flat Panel Display: flat panel display) etc. glass substrate for example, also can be LCD (LiquidCrystal Display:.
[embodiment]
Then embodiments of the invention are described.
At first, the present inventor implements RIE to the mounting wafer W and handles in substrate board treatment 10, measures the etch-rate of the circumference of the mounting wafer W that this RIE handles, and its result is depicted in the chart of Fig. 5 with " ● ".
Comparative example 1,2
Then, the present inventor replaces lateral electrode 35, prepares only to have and the parallel surface of mounting wafer W and area that should the surface 2 different lateral electrodes mutually.Then, with the lateral electrode 35 in each lateral electrode replacement substrate board treatment 10 of being prepared, and the mounting wafer W is implemented RIE handle, measure the etch-rate of the circumference of the mounting wafer W that this RIE handles, its result is depicted in the chart of Fig. 5 with " ◆ ".
The transverse axis of the chart of Fig. 5 is represented the surface area of lateral electrode.Herein, the surface area of lateral electrode is equivalent to the 1st secondary emission surface 35a among the embodiment 1 and the aggregate value of the area of the 2nd secondary emission surface 35b, the area on the surface parallel with the mounting wafer W in the comparative example 1,2.In addition, in the chart of Fig. 5, transverse axis represents the surface area of the lateral electrode of comparative example 1 surface area as the lateral electrode of 1 o'clock embodiment 1 and each comparative example, and the longitudinal axis represents that etch-rate with comparative example 1 is as 1 o'clock the embodiment 1 and the etch-rate of each comparative example.By the chart of Fig. 5 as can be known, than the surface area that increases lateral electrode, fully rise by the electron density that is provided with directly over the circumference that the 2nd secondary emission surface 35b that tilts with respect to the 1st secondary emission surface 35a can more effectively make the mounting wafer W, the RIE that can promote at the circumference of mounting wafer W handles.
Claims (4)
1. electrode structure, this electrode structure are configured in to be implemented in the process chamber that substrate board treatment possessed of plasma treatment substrate, in this process chamber be positioned in mounting table on described substrate mutually opposed, it is characterized in that:
This electrode structure comprise with the opposed medial electrode of the central part of described substrate and with the opposed lateral electrode of the circumference of described substrate, wherein,
Described medial electrode is connected with first DC power supply, and described lateral electrode is connected with second DC power supply,
Described lateral electrode has parallel with described substrate first and with respect to second of this first face tilt.
2. electrode structure according to claim 1 is characterized in that:
Described first and described second circumference that points to described substrate.
3. substrate board treatment, this substrate board treatment is implemented plasma treatment to substrate, it is characterized in that, comprising:
Accommodate the process chamber of described substrate;
Be configured in the mounting table that this process chamber is interior, be used for the described substrate of mounting; With
Be configured in the described process chamber and with the opposed electrode structure of described substrate that is positioned on the described mounting table,
Described electrode structure comprise with the opposed medial electrode of the central part of described substrate and with the opposed lateral electrode of the circumference of described substrate,
Described medial electrode is connected with first DC power supply, and described lateral electrode is connected with second DC power supply,
Described lateral electrode has parallel with described substrate first and with respect to second of this first face tilt.
4. substrate board treatment according to claim 3 is characterized in that:
Described first and described second circumference that points to described substrate.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008083046A JP5348919B2 (en) | 2008-03-27 | 2008-03-27 | Electrode structure and substrate processing apparatus |
| JP2008083046 | 2008-03-27 | ||
| JP2008-083046 | 2008-03-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101546700A true CN101546700A (en) | 2009-09-30 |
| CN101546700B CN101546700B (en) | 2011-04-13 |
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ID=41115344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101294603A Active CN101546700B (en) | 2008-03-27 | 2009-03-20 | Electrode structure and substrate processing apparatus |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20090242133A1 (en) |
| JP (1) | JP5348919B2 (en) |
| KR (1) | KR20110131157A (en) |
| CN (1) | CN101546700B (en) |
| TW (1) | TWI475610B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024567A (en) * | 2015-03-31 | 2016-10-12 | 朗姆研究公司 | Plasma processing systems and structures having sloped confinement rings |
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| US5472565A (en) * | 1993-11-17 | 1995-12-05 | Lam Research Corporation | Topology induced plasma enhancement for etched uniformity improvement |
| TW299559B (en) * | 1994-04-20 | 1997-03-01 | Tokyo Electron Co Ltd | |
| JP3814176B2 (en) * | 2001-10-02 | 2006-08-23 | キヤノンアネルバ株式会社 | Plasma processing equipment |
| US7740737B2 (en) * | 2004-06-21 | 2010-06-22 | Tokyo Electron Limited | Plasma processing apparatus and method |
| JP4672456B2 (en) * | 2004-06-21 | 2011-04-20 | 東京エレクトロン株式会社 | Plasma processing equipment |
| US7988816B2 (en) * | 2004-06-21 | 2011-08-02 | Tokyo Electron Limited | Plasma processing apparatus and method |
| JP4704088B2 (en) * | 2005-03-31 | 2011-06-15 | 東京エレクトロン株式会社 | Plasma processing equipment |
| US7993489B2 (en) * | 2005-03-31 | 2011-08-09 | Tokyo Electron Limited | Capacitive coupling plasma processing apparatus and method for using the same |
| US8789493B2 (en) * | 2006-02-13 | 2014-07-29 | Lam Research Corporation | Sealed elastomer bonded Si electrodes and the like for reduced particle contamination in dielectric etch |
| US7829469B2 (en) * | 2006-12-11 | 2010-11-09 | Tokyo Electron Limited | Method and system for uniformity control in ballistic electron beam enhanced plasma processing system |
| JP5231038B2 (en) * | 2008-02-18 | 2013-07-10 | 東京エレクトロン株式会社 | Plasma processing apparatus, plasma processing method, and storage medium |
| JP2009239012A (en) * | 2008-03-27 | 2009-10-15 | Tokyo Electron Ltd | Plasma processing device and method of plasma etching |
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- 2009-03-19 US US12/407,109 patent/US20090242133A1/en not_active Abandoned
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024567A (en) * | 2015-03-31 | 2016-10-12 | 朗姆研究公司 | Plasma processing systems and structures having sloped confinement rings |
| CN106024567B (en) * | 2015-03-31 | 2018-05-04 | 朗姆研究公司 | With the plasma process system and structure for tilting confinement ring |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201001530A (en) | 2010-01-01 |
| CN101546700B (en) | 2011-04-13 |
| JP5348919B2 (en) | 2013-11-20 |
| KR20110131157A (en) | 2011-12-06 |
| TWI475610B (en) | 2015-03-01 |
| US20090242133A1 (en) | 2009-10-01 |
| JP2009239014A (en) | 2009-10-15 |
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