JP2009239014A - Electrode structure and substrate processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrode structure capable of sufficiently raising an electron density at locations facing a peripheral edge of a substrate in a processing space. <P>SOLUTION: An upper electrode 31 arranged in a processing chamber 11 of a substrate processing device 10 for performing RIE process to a wafer W and facing the wafer W placed on a susceptor 12 in the processing chamber 11 comprises an inside electrode 34 facing a center part of the wafer W placed on the susceptor 12 and an outside electrode 35 facing a peripheral edge of the wafer W. The inside electrode 34 is connected to a first DC power source 37 and the outside electrode 35 is connected to a second DC power source 38. The outside electrode 35 comprises a first secondary electron emission face 35a parallel to the wafer W placed on the susceptor 12, and a second secondary electron emission face 35b inclined toward the wafer W with respect to the first secondary electron emission face 35a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electrode structure and a substrate processing apparatus, and more particularly to an electrode structure that is disposed in a processing chamber of a substrate processing apparatus and connected to a DC power source.

  A substrate processing apparatus that performs plasma processing on a wafer as a substrate includes: a processing chamber that accommodates the wafer; a mounting table that is placed in the processing chamber to place the wafer; and a shower that supplies processing gas to the processing space in the processing chamber And a head. In this substrate processing apparatus, a high frequency power source is connected to the mounting table, the mounting table applies high frequency power to the processing space, and the processing gas supplied to the processing space is excited by the high frequency power to generate plasma (positive ions or electrons). Become.

  Since the plasma distribution in the processing space has a great influence on the result of the plasma processing of the wafer, it is preferable to positively control the plasma distribution. Correspondingly, a shower is used to control the plasma distribution, particularly the electron density distribution. A DC voltage is applied to the head.

When a DC voltage is applied to the shower head, a DC power source is connected to a disk-shaped ceiling electrode plate that is a component of the shower head and is exposed to the processing space. Here, when a negative DC voltage is applied to the shower head, the shower head draws only positive ions in the plasma. Unlike the high-frequency voltage, the direct-current voltage does not change with time, so that positive ions are continuously drawn into the showerhead. The cations drawn into the shower head cause secondary electrons to be emitted from the constituent atoms of the shower head. As a result, the electron density increases in the portion of the processing space facing the shower head (see, for example, Patent Document 1).
JP 2006-270019 A

  By the way, the electron density distribution may be non-uniform in the processing space due to the influence of the shape of the processing chamber. However, when the ceiling electrode plate is composed of one conductive plate, a DC voltage is applied to the ceiling electrode plate. Even if it is applied, the electron density of all the portions in the processing space facing the shower head only rises, so the nonuniformity of the electron density distribution cannot be eliminated. As a result, the electron density is reduced at the portion of the processing space that faces the peripheral edge of the wafer, and in the case of the etching process, the etch rate at the peripheral edge of the wafer is lower than that at the center of the wafer.

  An object of the present invention is to provide an electrode structure and a substrate processing apparatus capable of sufficiently increasing the electron density at a portion facing the peripheral edge of a substrate in a processing space.

  To achieve the above object, the electrode structure according to claim 1 is disposed in a processing chamber provided in a substrate processing apparatus for performing plasma processing on a substrate, and faces the substrate mounted on a mounting table in the processing chamber. An electrode structure, comprising: an inner electrode facing the central portion of the substrate; and an outer electrode facing the peripheral edge of the substrate; a first DC power supply is connected to the inner electrode; and the outer electrode Is connected to a second DC power source, and the outer electrode has a first surface parallel to the substrate and a second surface inclined with respect to the first surface.

  The electrode structure according to a second aspect is the electrode structure according to the first aspect, wherein the first surface and the second surface are directed to a peripheral edge of the substrate.

  In order to achieve the above object, a substrate processing apparatus according to claim 3 is a substrate processing apparatus for performing plasma processing on a substrate, a processing chamber for accommodating the substrate, and a substrate disposed in the processing chamber. And an electrode structure disposed in the processing chamber and facing the substrate placed on the mounting table, the electrode structure comprising an inner electrode facing a central portion of the substrate, An outer electrode facing the peripheral edge of the substrate, a first DC power supply is connected to the inner electrode, a second DC power supply is connected to the outer electrode, and the outer electrode is connected to the substrate It has a parallel 1st surface and a 2nd surface inclined with respect to this 1st surface, It is characterized by the above-mentioned.

  According to the electrode structure of the first aspect and the substrate processing apparatus of the third aspect, the second direct current power source is connected to the outer electrode facing the peripheral edge portion of the substrate, and the direct current voltage is applied. When a DC voltage is applied to the outer electrode, the outer electrode draws cations in the plasma and emits secondary electrons. As a result, it is possible to increase the electron density at a portion facing the peripheral edge of the substrate in the processing space. The outer electrode to which the second DC power supply is connected has a first surface parallel to the substrate and a second surface inclined with respect to the first surface, and the secondary electrons are the first. And the second surface. Since the second surface is inclined with respect to the first surface, secondary electrons emitted from the second surface are emitted from the first surface at a portion facing the peripheral edge of the substrate in the processing space. Overlapping with secondary electrons. As a result, it is possible to sufficiently increase the electron density at a portion facing the peripheral edge of the substrate in the processing space.

  According to the electrode structure of claim 2, since the first surface and the second surface are directed to the peripheral portion of the substrate, the secondary electrons emitted from the first surface and the second surface are emitted from the second surface. Secondary electrons overlap just above the peripheral edge of the substrate. As a result, the electron density can be reliably and sufficiently increased immediately above the peripheral edge of the substrate.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view schematically showing the configuration of the substrate processing apparatus according to the present embodiment, and FIG. 2 is an enlarged cross-sectional view schematically showing the configuration in the vicinity of the outer electrode of the upper electrode in FIG. . This substrate processing apparatus is configured to perform RIE (Reactive Ion Etching) processing on a semiconductor wafer as a substrate using plasma.

  1 and 2, the substrate processing apparatus 10 includes a cylindrical processing chamber 11 and a semiconductor wafer (hereinafter simply referred to as “wafer”) W having a diameter of 300 mm, which is disposed in the processing chamber 11. And a columnar susceptor 12 as a mounting table.

  In the substrate processing apparatus 10, an exhaust flow path 13 that functions as a flow path for discharging a gas in the processing space S described later to the outside of the processing chamber 11 is formed by the inner wall of the processing chamber 11 and the side surface of the susceptor 12. An exhaust plate (exhaust ring) 14 is disposed in the middle of the exhaust flow path 13.

  The exhaust plate 14 is a plate-like member having a large number of through holes, and functions as a partition plate that partitions the processing chamber 11 into an upper part and a lower part. Plasma is generated in an upper portion (hereinafter referred to as “reaction chamber”) 15 of the processing chamber 11 partitioned by the exhaust plate 14 as will be described later. Further, exhaust pipes 17 and 18 for discharging gas in the processing chamber 11 are connected to a lower portion 16 (hereinafter referred to as “exhaust chamber (manifold)”) of the processing chamber 11. The exhaust plate 14 captures or reflects the plasma generated in the reaction chamber 15 to prevent leakage to the manifold 16.

A TMP (Turbo Molecular Pump) (not shown) is connected to the exhaust pipe 17, and a DP (Dry Pump) (not shown) is connected to the exhaust pipe 18, and these pumps evacuate the inside of the processing chamber 11. Reduce pressure. Specifically, DP depressurizes the inside of the processing chamber 11 from atmospheric pressure to a medium vacuum state (for example, 1.3 × 10 Pa (0.1 Torr or less)), and TMP cooperates with the DP in the processing chamber 11. The pressure is reduced to a high vacuum state (for example, 1.3 × 10 ⁻³ Pa (1.0 × 10 ⁻⁵ Torr or less)) that is lower than the medium vacuum state. Note that the pressure in the processing chamber 11 is controlled by an APC valve (not shown).

  A first high-frequency power source 19 and a second high-frequency power source 20 are connected to the susceptor 12 in the processing chamber 11 via a first matching unit 21 and a second matching unit 22, respectively. Applies a relatively high frequency, for example, 60 MHz high frequency power to the susceptor 12, and the second high frequency power supply 20 applies a relatively low frequency, for example, 2 MHz high frequency power to the susceptor 12. Thereby, the susceptor 12 functions as a lower electrode that applies high-frequency power to a processing space S between the susceptor 12 and a shower head 30 described later.

  Further, on the susceptor 12, an electrostatic chuck 24 made of a disk-shaped insulating member having an electrostatic electrode plate 23 inside is disposed. When the wafer W is placed on the susceptor 12, the wafer W is placed on the electrostatic chuck 24. In the electrostatic chuck 24, a DC power source 25 is electrically connected to the electrostatic electrode plate 23. When a positive DC voltage is applied to the electrostatic electrode plate 23, a negative potential is generated on the surface of the wafer W on the electrostatic chuck 24 side (hereinafter referred to as “back surface”), and the electrostatic electrode plate 23 and the wafer. A potential difference is generated between the back surfaces of W, and the wafer W is attracted and held on the electrostatic chuck 24 by Coulomb force or Johnson-Rahbek force resulting from the potential difference.

  An annular focus ring 26 is mounted on the susceptor 12 so as to surround the wafer W held by suction. The focus ring 26 is made of a conductive member, for example, silicon, and converges plasma toward the surface of the wafer W to improve the efficiency of the RIE process.

  Further, for example, an annular refrigerant chamber 27 extending in the circumferential direction is provided inside the susceptor 12. A low-temperature refrigerant such as cooling water or a Galden (registered trademark) liquid is circulated and supplied to the refrigerant chamber 27 through a refrigerant pipe 28 from a chiller unit (not shown). The susceptor 12 cooled by the low-temperature refrigerant cools the wafer W and the focus ring 26 via the electrostatic chuck 24.

  A plurality of heat transfer gas supply holes 29 are opened in a portion of the upper surface of the electrostatic chuck 24 where the wafer W is sucked and held (hereinafter referred to as “sucking surface”). The plurality of heat transfer gas supply holes 29 supply helium (He) gas as a heat transfer gas to the gap between the adsorption surface and the back surface of the wafer W through the heat transfer gas supply holes 29. The helium gas supplied to the gap between the suction surface and the back surface of the wafer W efficiently transfers the heat of the wafer W to the electrostatic chuck 24.

  A shower head 30 is disposed on the ceiling of the processing chamber 11. The shower head 30 includes an upper electrode 31 (electrode structure) that is exposed to the processing space S and faces the wafer W (hereinafter referred to as “mounting wafer W”) placed on the susceptor 12 and an insulating member. And an electrode fishing support 33 that supports the upper electrode 31 via the insulating plate 32. The upper electrode 31, the insulating plate 32, and the electrode fishing support 33 are superposed in this order. Yes.

  The electrode fishing support 33 has a buffer chamber 39 inside. The buffer chamber 39 is a cylindrical space, and is divided into an inner buffer chamber 39a and an outer buffer chamber 39b by an annular seal material, for example, an O-ring 40.

  A processing gas introduction pipe 41 is connected to the inner buffer chamber 39a, and a processing gas introduction pipe 42 is connected to the outer buffer chamber 39b. The processing gas introduction pipes 41 and 42 are respectively connected to the inner buffer chamber 39a and the outer buffer chamber 39b. Process gas is introduced into

  Since the processing gas introduction pipes 41 and 42 each have a flow rate controller (MFC) (not shown), the flow rates of the processing gases introduced into the inner buffer chamber 39a and the outer buffer chamber 39b are independently controlled. The buffer chamber 39 communicates with the processing space S through the gas hole 43 of the electrode fishing support 33, the gas hole 44 of the insulating plate 32, and the gas hole 36 of the upper electrode 31, and the inner buffer chamber 39a and the outer buffer The processing gas introduced into the chamber 39b is supplied to the processing space S. At this time, the distribution of the processing gas in the processing space S is controlled by adjusting the flow rate of the processing gas introduced into the inner buffer chamber 39a and the outer buffer chamber 39b.

  In the substrate processing apparatus 10, when the RIE process is performed on the mounting wafer W, the shower head 30 supplies a processing gas to the processing space S, and the first high-frequency power source 19 passes through the susceptor 12 to the processing space S at 60 MHz. While applying the high frequency power, the second high frequency power supply 20 applies the high frequency power of 2 MHz to the susceptor 12. At this time, the processing gas is excited by high frequency power of 60 MHz to become plasma. In addition, since the high frequency power of 2 MHz generates a bias voltage in the susceptor 12, positive ions and electrons in the plasma are drawn into the surface of the mounting wafer W, and the mounting wafer W is subjected to RIE processing.

  By the way, in order to partially control the electron density distribution in the processing space, the upper electrode is divided into an inner electrode facing the center of the wafer and an outer electrode facing the peripheral edge of the wafer. A method of applying a DC voltage to each independently has been developed. In this method, a DC voltage having a value different from that of the inner electrode is applied to the outer electrode to independently control the electron density of the portion facing the outer electrode and the electron density of the portion facing the inner electrode in the processing space. .

  With regard to this method, the present inventors increase the surface area of the outer electrode facing the processing space (hereinafter referred to as “outer electrode surface area”) through the RIE processing experiment, and thereby the outer electrode facing surface in the processing space. The electron density of the part (hereinafter referred to as “outer electrode facing part”) opposite to the substrate increases, and as a result, the knowledge that the etch rate at the peripheral edge of the wafer increases (see FIG. 3) has been obtained.

  Further, the inventors have found that when the value of the DC voltage applied to the outer electrode is increased, the electron density in the portion facing the outer electrode also increases, and as a result, the etch rate at the peripheral edge of the wafer increases. Got. Specifically, when the value of the DC voltage applied to the outer electrode is increased from 300 V to 900 V while the value of the DC voltage applied to the inner electrode is maintained at 300 V, the etch rate at the peripheral edge of the wafer is about 7%. A rise was confirmed (see FIG. 4).

  However, in a normal substrate processing apparatus, since other processing chamber components exist around the outer electrode, it is often difficult to increase the surface area of the outer electrode beyond a certain value. Further, it is often difficult to raise the value of the DC power source applied to the outer electrode to a certain value or more due to restrictions on the performance of the DC power source. That is, it is usually difficult to sufficiently increase the electron density in the portion of the processing space facing the peripheral edge of the wafer.

  In the substrate processing apparatus 10, the upper electrode 31 correspondingly corresponds to the inner electrode 34 facing the center portion of the mounting wafer W, and the outer side surrounding the inner electrode 34 and facing the peripheral edge portion of the mounting wafer W. The outer electrode 35 is mounted on the first secondary electron emission surface 35a (first surface) parallel to the mounting wafer W and the first secondary electron emission surface 35a. A second secondary electron emission surface 35b (second surface) inclined toward the wafer W is provided. The first secondary electron emission surface 35a and the outer electrode 35b are directed to the peripheral edge of the mounting wafer W, respectively.

  Here, the inner electrode 34 is made of, for example, a disk-shaped member having a diameter of 300 mm, and has a large number of gas holes 36 penetrating in the thickness direction. The outer electrode 35 is made of an annular member having an outer diameter of 380 mm and an inner diameter of 300 mm. The inner electrode 34 and the outer electrode 35 are made of a conductive or semiconductive material, for example, single crystal silicon.

  In the upper electrode 31, a first DC power source 37 is connected to the inner electrode 34, and a second DC power source 38 is connected to the outer electrode 35. A DC voltage is applied to the inner electrode 34 and the outer electrode 35, respectively. Applied independently.

  In the substrate processing apparatus 10, the first DC power supply 37 and the second DC power supply 38 apply a negative DC voltage to the inner electrode 34 and the outer electrode 35 of the upper electrode 31 during the RIE process. At this time, cations in the plasma in the processing space S are drawn into the inner electrode 34 and the outer electrode 35. The drawn cations impart energy to the electrons in the constituent atoms in the inner electrode 34 and the outer electrode 35, and when the applied energy exceeds a certain value, the electrons in the constituent atoms become secondary electrons as the inner electrode. 34 and the first secondary electron emission surface 35 a and the second secondary electron emission surface 35 b of the outer electrode 35.

  As described above, the inner electrode 34 is a disk-shaped member, and since only the surface parallel to the mounting wafer W is exposed to the processing space S, the secondary electrons emitted from the surface are exposed to the mounting wafer W. Almost uniformly distributed from the center to the periphery. As a result, the RIE process is promoted over the entire surface of the mounting wafer W.

  Since the first secondary electron emission surface 35a and the second secondary electron emission surface 35b of the outer electrode 35 are both directed toward the peripheral edge of the mounting wafer W as described above, the first secondary electrons are emitted. The secondary electrons emitted from the emission surface 35a and the second secondary electron emission surface 35b overlap immediately above the peripheral edge of the mounting wafer W. As a result, the electron density can be sufficiently increased immediately above the peripheral portion of the mounting wafer W, and the RIE process is promoted at the peripheral portion of the mounting wafer W.

  The operation of each component of the substrate processing apparatus 10 described above is controlled by a CPU of a control unit (not shown) provided in the substrate processing apparatus 10.

  According to the upper electrode 31 as the electrode structure according to the present embodiment, a second DC power supply 38 is connected to the outer electrode 35 facing the peripheral edge of the mounting wafer W, and a DC voltage is applied. When a DC voltage is applied to the outer electrode 35, the outer electrode 35 draws positive ions in the plasma and emits secondary electrons. As a result, the electron density can be increased immediately above the peripheral edge of the mounting wafer W in the processing space S. The outer electrode 35 to which the second DC power source 38 is connected is placed on the first secondary electron emission surface 35a parallel to the placement wafer W and the first secondary electron emission surface 35a. A second secondary electron emission surface 35b inclined toward the wafer W, and the secondary electrons are emitted from the first secondary electron emission surface 35a and the second secondary electron emission surface 35b. Since both the first secondary electron emission surface 35a and the second secondary electron emission surface 35b are directed to the peripheral portion of the mounting wafer W, the electron density is sufficiently increased immediately above the peripheral portion of the mounting wafer W. In addition, the RIE process can be promoted at the peripheral edge of the mounting wafer W.

  In the upper electrode 31 described above, the outer electrode 35 can sufficiently increase the electron density immediately above the peripheral edge of the mounting wafer W without increasing the area of the outer electrode 35 facing the wafer W. There is no need to increase the size. As a result, the amount of expensive single crystal silicon used can be reduced, and the manufacturing cost of the upper electrode 31 can be reduced.

  In the upper electrode 31 described above, not only the first secondary electron emission surface 35a but also the second secondary electron emission surface 35b are directed to the peripheral portion of the mounting wafer W. The emission surface 35b may not be directed to the peripheral edge of the mounting wafer W. For example, the second secondary electron emission surface 35b may be perpendicular to the first secondary electron emission surface 35a. . Even in this case, since the secondary electrons emitted from the portion of the processing space S facing the peripheral edge of the mounting wafer W overlap, the electron density is sufficiently increased in the portion of the processing wafer S facing the peripheral edge. Can be raised.

  Further, the second secondary electron emission surface 35b does not need to be a flat surface, and may be a parabolic surface directed to the peripheral edge of the mounting wafer W. In this case, secondary electrons can be intensively emitted from the second secondary electron emission surface 35b toward the peripheral portion of the mounting wafer W, and thus the electron density immediately above the peripheral portion of the mounting wafer W. Can be raised sufficiently.

  In the present embodiment described above, the substrate on which the etching process is performed is the semiconductor wafer W. However, the substrate on which the etching process is performed is not limited to this, for example, an LCD (Liquid Crystal Display) or an FPD (FPD). It may be a glass substrate such as Flat Panel Display).

  Next, examples of the present invention will be described.

Example 1
First, the inventor performs RIE processing on the mounting wafer W in the substrate processing apparatus 10, measures the etch rate of the peripheral edge of the mounting wafer W in the RIE processing, and the result is shown in the graph of FIG. And plotted.

Comparative Examples 1 and 2
Next, the present inventor prepared two outer electrodes having only surfaces parallel to the mounting wafer W and having different surface areas instead of the outer electrodes 35. Then, the outer electrode 35 is replaced with the prepared outer electrode in the substrate processing apparatus 10, the mounting wafer W is subjected to RIE processing, and the etch rate of the peripheral edge of the mounting wafer W in the RIE processing is measured. Is plotted on the graph of FIG.

  The horizontal axis of the graph in FIG. 5 indicates the surface area of the outer electrode. Here, the surface area of the outer electrode is parallel to the total value of the areas of the first secondary electron emission surface 35a and the second secondary electron emission surface 35b in the first embodiment and the mounting wafer W in the first and second comparative examples. Corresponds to the surface area. In the graph of FIG. 5, the horizontal axis indicates the surface area of the outer electrode of Example 1 and each comparative example when the surface area of the outer electrode of Comparative Example 1 is 1, and the vertical axis indicates the etch of Comparative Example 1. The etch rate of Example 1 and each comparative example when the rate is 1 is shown. From the graph of FIG. 5, rather than increasing the surface area of the outer electrode, the placement wafer W is efficiently provided by providing the second secondary electron emission surface 35b inclined with respect to the first secondary electron emission surface 35a. It has been found that the electron density immediately above the peripheral edge of the wafer can be sufficiently increased, and the RIE process can be promoted at the peripheral edge of the mounting wafer W.

It is sectional drawing which shows schematically the structure of the substrate processing apparatus which concerns on embodiment of this invention. It is an expanded sectional view which shows roughly the structure of the outer electrode vicinity of the upper electrode in FIG. It is a graph which shows the relationship between the outer electrode surface area in an outer electrode, and the etch rate in the peripheral part of a wafer. It is a graph which shows the etching rate increase rate when the value of the DC voltage applied to an outer electrode is increased. It is a graph which shows the relationship between the outer electrode surface area in Example 1 of this invention, and Comparative Examples 1 and 2, and the etch rate in the peripheral part of a wafer.

Explanation of symbols

W wafer 10 substrate processing apparatus 11 processing chamber 12 susceptor 31 upper electrode 34 inner electrode 35 outer electrode 35a first secondary electron emission surface 35b second secondary electron emission surface 37 first DC power supply 38 second DC power supply

Claims (3)

An electrode structure disposed in a processing chamber provided in a substrate processing apparatus for performing plasma processing on a substrate, and facing the substrate mounted on a mounting table in the processing chamber,
An inner electrode facing the center of the substrate, and an outer electrode facing the peripheral edge of the substrate,
A first DC power source is connected to the inner electrode, and a second DC power source is connected to the outer electrode,
The outer electrode has a first surface parallel to the substrate and a second surface inclined with respect to the first surface.   The electrode structure according to claim 1, wherein the first surface and the second surface are directed toward a peripheral edge of the substrate. In a substrate processing apparatus for performing plasma processing on a substrate,
A processing chamber containing the substrate;
A mounting table disposed in the processing chamber for mounting the substrate;
An electrode structure disposed in the processing chamber and facing the substrate mounted on the mounting table,
The electrode structure comprises an inner electrode facing the center of the substrate and an outer electrode facing the peripheral edge of the substrate,
A first DC power source is connected to the inner electrode, and a second DC power source is connected to the outer electrode,
The substrate processing apparatus, wherein the outer electrode has a first surface parallel to the substrate and a second surface inclined with respect to the first surface.

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