US20090242133A1

US20090242133A1 - Electrode structure and substrate processing apparatus

Info

Publication number: US20090242133A1
Application number: US12/407,109
Authority: US
Inventors: Hiroyuki Nakayama; Masanobu Honda; Kenji MASUZAWA; Manabu Iwata
Original assignee: Tokyo Electron Ltd
Current assignee: Tokyo Electron Ltd
Priority date: 2008-03-27
Filing date: 2009-03-19
Publication date: 2009-10-01
Also published as: JP5348919B2; CN101546700A; TWI475610B; KR20110131157A; JP2009239014A; TW201001530A; CN101546700B

Abstract

An electrode structure capable of adequately increasing an electron density in a processing space at a part facing a circumferential edge portion of a substrate. In a processing chamber of a substrate processing apparatus that performs RIE processing on a wafer, an upper electrode of the electrode structure is disposed to face the wafer placed on a susceptor inside the processing chamber. The upper electrode includes an inner electrode facing a central portion of the wafer and an outer electrode facing the circumferential edge portion of the wafer. The inner and outer electrodes are connected with first and second DC power sources, respectively. The outer electrode has its first secondary electron emission surface extending parallel to the wafer and its second secondary electron emission surface obliquely extending relative to the first secondary electron emission surface.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to an electrode structure and a substrate processing apparatus, and more particularly, to an electrode structure disposed inside a processing chamber of a substrate processing apparatus and connected to a DC power source.
2. Description of the Related Art
A substrate processing apparatus for performing plasma processing on substrates, e.g., wafers, includes a processing chamber in which a wafer is housed, a mounting table which is disposed inside the processing chamber and on which the wafer is mounted, a shower head that supplies a processing gas to a processing space inside the processing chamber. The mounting table is connected with a high-frequency power supply and applies high-frequency electric power to the processing space. The processing gas supplied to the processing space is excited by the high-frequency electric power, whereby a plasma (cations and electrons) is produced.
Since a plasma distribution in the processing space greatly affects on results of plasma processing on wafers, it is preferable to positively control the plasma distribution. To control the plasma distribution, especially, electron density distribution, a DC voltage is applied to the shower head.
For application of the DC voltage to the shower head, a DC power source is connected to a circular disk-shaped ceiling electrode plate, which is a component part of the shower head and exposed to the processing space. When applied with a negative DC voltage, the shower head only draws cations in the plasma. Since a DC voltage has an electric potential remaining constant with elapse of time unlike a high frequency voltage, cations are continuously drawn into the shower head. The cations drawn into the shower head cause secondary electrons to be emitted from constituent atoms of the shower head. As a result, the electron density in the processing space increases at a part facing the shower head (see, for example, US Patent Application Publication No. 20060066247A1 (corresponding to Japanese Laid-open Patent Publication No. 2006-270019)).
The electron density distribution sometimes becomes ununiform due to affections of the shape of the processing chamber, etc. In the case of the ceiling electrode plate comprised of a single electrically conductive plate, even when a DC voltage is applied to the ceiling electrode plate, the electron density in the processing space increases at all the parts corresponding to the shower head, making it impossible to eliminate the problem of uneven electron density distribution. As a result, the electron density in the processing space decreases at a part facing a circumferential edge portion of a wafer, posing a problem that the etching rate in etching processing decreases at the circumferential edge portion of the wafer as compared to that at a central portion thereof.

SUMMARY OF THE INVENTION

The present invention provides an electrode structure and a substrate processing apparatus, which are capable of adequately increasing an electron density in a processing space at a part facing a circumferential edge portion of a substrate.
According to a first aspect of this invention, there is provided an electrode structure disposed inside a processing chamber of a substrate processing apparatus for performing plasma processing on a substrate, so as to face the substrate placed on a mounting table in the processing chamber, which comprises an inner electrode disposed to face a central portion of the substrate, and an outer electrode disposed to face a circumferential edge portion of the substrate, wherein the inner electrode is connected to a first DC power source, the outer electrode is connected to a second DC power source, and the outer electrode has a first surface thereof extending parallel to the substrate and a second surface thereof obliquely extending relative to the first surface of the outer electrode.
With the electrode structure of this invention, the outer electrode facing a circumferential edge portion of a substrate is connected with the second DC power source and applied with a DC voltage. When applied with the DC voltage, the outer electrode draws cations in a plasma and emits secondary electrons. As a result, it is possible to increase an electron density in the processing space at a part facing the circumferential edge portion of the substrate. The outer electrode has its first surface extending parallel to the substrate and its second surface obliquely extending relative to the first surface, and secondary electrons are emitted from the first and second surfaces. Since the second surface obliquely extends relative to the first surface, secondary electrons emitted from the second surface are superimposed on secondary electrons emitted from the first surface at the part in the processing space facing the circumferential edge portion of the substrate. As a result, it is possible to adequately increase the electron density in the processing space at the part facing the circumferential edge portion of the substrate.
The first and second surfaces of the outer electrode can be directed toward the circumferential edge portion of the substrate.
With this electrode structure, the first and second surfaces are directed to the circumferential edge portion of the substrate, and therefore, secondary electrons emitted from the first surface and those emitted from the second surface are superimposed on one another at a part right above the circumferential edge portion of the substrate. As a result, it is possible to reliably and adequately increase the electron density right above the circumferential edge portion of the substrate.
According to a second aspect of this invention, there is provided a substrate processing apparatus including a processing chamber for housing a substrate, a mounting table disposed inside the processing chamber and adapted to place the substrate thereon, and an electrode structure disposed inside the processing chamber so as to face the substrate placed on the mounting table, the substrate processing being adapted to perform plasma processing on the substrate, wherein the electrode structure includes an inner electrode thereof disposed to face a central portion of the substrate and an outer electrode thereof disposed to face a circumferential edge portion of the substrate, the inner electrode is connected to a first DC power source and the outer electrode is connected to a second DC power source, and the outer electrode has a first surface thereof extending parallel to the substrate and a second surface thereof obliquely extending relative to the first surface of the outer electrode.
With the substrate processing apparatus of this invention, secondary electrons emitted from the second surface of the outer electrode are superimposed on the secondary electrons emitted from the first surface of the outer electrode at a part in the processing space facing a circumferential edge portion of a substrate, making it possible to adequately increase the electron density in the processing space at the part facing the circumferential edge portion of the substrate.
Further features of the present invention will become apparent from the following description of an exemplary embodiment with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a section view schematically showing the construction of a substrate processing apparatus according to one embodiment of this invention;

FIG. 2 is a fragmentary enlarged section view schematically showing the construction of and around an outer electrode of an upper electrode shown in FIG. 1;

FIG. 3 is a graph showing a relation between outer electrode surface area and etching rate at a circumferential edge portion of a wafer;

FIG. 4 is a graph showing the rate of increase in etching rate observed when a value of DC voltage applied to the outer electrode is increased; and

FIG. 5 is a graph showing relation between outer electrode surface area and etching rate at a circumferential edge portion of a wafer in example 1 of this invention and comparative examples 1 and 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will now be described in detail below with reference to the drawings showing a preferred embodiment thereof.
FIG. 1 schematically shows in cross section the construction of a substrate processing apparatus according to one embodiment of this invention, and FIG. 2 schematically shows in fragmentary enlarged view the construction of and around an outer electrode of an upper electrode in FIG. 1. The substrate processing apparatus is adapted to perform RIE (reactive ion etching) processing on semiconductor wafers as substrates by using a plasma.
As shown in FIGS. 1 and 2, the substrate processing apparatus 10 includes a cylindrical processing chamber 11 and a columnar susceptor 12 disposed therein and serving as a mounting table on which is placed a semiconductor wafer (hereinafter simply referred to as wafer) W having a diameter, e.g., of 300 mm.
An exhaust passage 13 is defined by an inner side wall of the processing chamber 11 and a side surface of the susceptor 12 and functions as a flow passage through which a gas in a processing space S, described later, is exhausted to the outside of the processing chamber 11. An exhaust plate (exhaust ring) 14 is disposed in the middle of the exhaust passage 13.
The exhaust plate 14 is a plate-like member formed with a number of through holes and functions as a partition plate by which the processing chamber 11 is divided into an upper part and a lower part. In the upper part (hereinafter referred to as reaction chamber) 15 of the processing chamber 11, a plasma is generated as described later. To the lower part (hereinafter referred to as exhaust chamber (manifold)) 16 of the processing chamber 11 are connected exhaust pipes 17, 18 through which a gas in the processing chamber 11 is exhausted. The exhaust plate 14 catches or reflects the plasma generated in the reaction chamber 15 to prevent leakage of the plasma to the manifold 16.
The exhaust pipe 17 is connected to a TMP (turbo molecular pump), not shown, and the exhaust pipe 18 is connected to a DP (dry pump), not shown. These pumps vacuum and depressurize the inside of the processing chamber 11. Specifically, the DP depressurizes the inside of the chamber 11 from atmospheric pressure to a medium vacuum (for example, not higher than 1.3×10 Pa (0.1 Torr)), and the TMP cooperates with the DP to depressurize the inside of the chamber 11 to a high vacuum (for example, not higher than 1.3×10⁻³Pa (1.0×10⁻⁵Torr)) which is lower in pressure than the medium vacuum. The pressure within the processing chamber 11 is controlled by an APC valve (not shown).
The susceptor 12 inside the processing chamber 11 is connected via a first matcher 21 to a first high-frequency power supply 19 and also connected via a second matcher 22 to a second high-frequency power supply 20. The first high-frequency power supply 19 applies high-frequency electric power of a relatively high frequency, e.g., 60 MHz, to the susceptor 12, and the second high-frequency power supply 20 applies high-frequency electric power of a relatively low frequency, e.g., 2 MHz, to the susceptor 12. The susceptor 12 functions as a lower electrode that applies high-frequency power to the processing space S defined between the susceptor 12 and a shower head 30 described later.
An electrostatic chuck 24 made of a disk-shaped insulating member and having an electrostatic electrode plate 23 incorporated therein is disposed on the susceptor 12. A wafer W is mounted on the electrostatic chuck 24 when it is placed on the susceptor 12. A DC power supply 25 is electrically connected to the electrostatic electrode plate 23 in the electrostatic chuck 24. When a positive DC voltage is applied to the electrode plate 23, a negative electrical potential is generated on a surface of the wafer W on the side of the electrostatic chuck 24 (hereinafter referred to as the rear surface), and a potential difference is produced between the electrode plate 23 and the rear surface of the wafer W. Due to the potential difference, the wafer W is attracted to and held by the electrostatic chuck 24 through a Coulomb force or a Johnsen-Rahbek force.
An annular focus ring 26 is disposed on the susceptor 12 such as to surround the wafer W held by the susceptor. The focus ring 26 is made of a conductive member, e.g., silicon, and converges plasma toward the surface of the wafer W to improve the efficiency of RIE processing.
An annular coolant unit 27 is provided inside the susceptor 12 and extends circumferentially of the susceptor. A low temperature coolant, for example, cooling water or a Galden fluid (registered trademark), is supplied from a chiller unit (not shown) via a coolant pipe 28 into the coolant chamber 27 for circulation. The susceptor 12 is cooled by the low temperature coolant and cools the wafer W and the focus ring 26 via the electrostatic chuck 24.
A plurality of heat-transfer gas feed holes 29 of a gas feed pipe are opened to that part of the upper surface of the electrostatic chuck 24 (hereinafter referred to as the suction surface) by which the wafer W is attracted and held. Helium (He) gas, as a heat transfer gas, is supplied from the gas feed holes 29 to a gap between the suction surface of the electrostatic chuck 24 and the rear surface of the wafer W. The helium gas supplied to the gap efficiently transfers heat of the wafer W to the electrostatic chuck 24.
The shower head 30 is disposed at a ceiling portion of the processing chamber 11. The shower head 30 includes an upper electrode 31 (electrode structure) disposed to face the wafer W placed on the susceptor 12 (hereinafter referred to as the placed wafer W) so as to be exposed to the processing space S, an insulating plate 32 made of an insulative member, and an electrode support member 33 that supports via the insulating plate 32 the upper electrode 31 hanging therefrom. The upper electrode 31, the insulating plate 32, and the electrode support member 33 are stacked one upon another in this order.
The electrode support member 33 has a buffer chamber 39 formed therein. The buffer chamber 39 defines a columnar space, which is divided into inner and outer buffer chambers 39 a, 39 b by an annular sealing member, e.g., an O-ring 40.
A processing gas introduction pipe 41 is connected to the inner buffer chamber 39 a, and a processing gas introduction pipe 42 is connected to the outer buffer chamber 39 b. A processing gas is introduced into the inner buffer chamber 39 a via the gas introduction pipe 41, and a processing gas is introduced into the outer buffer chamber 39 b via the gas introduction pipe 42.
The processing gas introduction pipes 41, 42 each include a mass flow controller (MFC), not shown. Therefore, amounts of flow of processing gases introduced into the inner and outer buffer chambers 39 a, 39 b are controlled independently of each other. As shown in FIG. 2, the buffer chamber 39 is communicated with the processing space S via gas holes 43 formed in the electrode support member 33, gas holes 33 formed in the insulating plate 32, and gas holes 36 formed in the upper electrode 31. The processing gases introduced into the inner and outer buffer chambers 39 a, 39 b are supplied to the processing space S. At that time, the amounts of flow of processing gases introduced into the inner and outer buffer chambers 39 a, 39 b are adjusted, whereby a distribution of processing gases in the processing space S is controlled.
With the substrate processing apparatus 10, when RIE processing is performed on the placed wafer W, the shower head 30 supplies processing gases into the processing space S, the first high-frequency power supply 19 applies high-frequency power of 60 MHz to the processing space S via the susceptor 12, and the second high-frequency power supply 20 applies high-frequency power of 2 MHz to the susceptor 12. The processing gases are excited by the high-frequency power of 60 MHz and converted into plasma. The high-frequency power of 2 MHz produces a bias voltage on the susceptor 12, and therefore cations or electrons in the plasma are drawn into the surface of the placed wafer W, whereby RIE processing is performed on the wafer W.
To control apart of electron density distribution in a processing space, there has been developed a method in which an upper electrode is divided into inner and outer electrodes respectively facing a central portion and a circumferential edge portion of a wafer, and DC voltages of negative polarity are independently applied to the inner and outer electrodes. In this method, a DC voltage of a value different from that applied to the inner electrode is applied to the outer electrode to thereby independently control the electron density in the processing space at parts facing the outer and inner electrodes.
With regard to this method, the present inventors et al. conducted experiments on RIE processing and had knowledge that the electron density in the processing space at a part facing an opposite surface of the outer electrode (hereinafter referred to as the part facing the outer electrode) increased with the increase in surface area of that surface of the outer electrode facing the processing space (hereinafter referred to as the outer electrode surface area), resulting in increase in etching rate at a circumferential edge portion of the wafer (see FIG. 3).
The present inventors et al. also had knowledge that the electron density at the part facing the outer electrode increased with the increase in a value of DC voltage applied to the outer electrode, resulting in increase in etching rate at the circumferential edge portion of the wafer. Specifically, it was confirmed that the etching rate at the circumferential edge portion of the wafer increased by about 7% when an absolute value of DC voltage applied to the outer electrode was increased from 300 volts to 900 volts, with the DC voltage applied to the inner electrode kept at an absolute value of 300 volts (see FIG. 4).
However, in an ordinary substrate processing apparatus, there are processing chamber component parts around the outer electrode, which makes it difficult to increase the outer electrode surface area up to a certain value or more. Due to limited performance of the DC power source, etc., it is often difficult to increase DC power applied to the outer electrode up to a certain value or more. Thus, it is usually difficult to adequately increase the electron density in the processing space at a part facing the circumferential edge portion of the wafer.
In view of the above, the upper electrode 31 of the substrate processing apparatus 10 has its inner electrode 34 facing a central portion of the placed wafer W and its outer electrode 35 arranged to surround the inner electrode 34 and facing a circumferential edge portion of the placed wafer W, and the outer electrode 35 has a first secondary electron emission surface 35 a (first surface) thereof extending parallel to the place wafer W and a second secondary electron emission surface 35 b (second surface) thereof obliquely extending relative to the first secondary electron emission surface 35 a toward the placed wafer W. The first and second secondary electron emission surfaces 35 a, 35 b are directed to the circumferential edge portion of the placed wafer W.
The inner electrode 34 is made of a circular disk shaped member having a diameter, e.g., of 300 mm, and is formed with a number of gas holes 36 extending in the thickness direction of the inner electrode 34. The outer electrode 35 is an annular member having an outer diameter, e.g., of 380 mm and an inner diameter, e.g., of 300 mm. The inner and outer electrodes 34, 35 are each made of a conductive or semiconductor material, e.g., single crystal silicon.
First and second DC power sources 37, 38 are respectively connected to the inner and outer electrode 34, of the upper electrode 31, and DC voltages are independently applied to the electrodes 34, 35.
During RIE processing in the substrate processing apparatus 10, negative DC voltages are applied from the first and second DC power sources 37, 38 to the inner and outer electrodes 34, 35 of the upper electrode 31. Cations in the plasma produced in the processing space S are therefore drawn into the inner and outer electrodes 34, 35, and supply energy to electrons of constituent atoms of the electrodes 34, 35. When the supplied energy exceeds a certain value, electrons of constituent atoms as secondary electrons are emitted from the surface of the inner electrode 34 and the first and second secondary electron emission surfaces 35 a, 35 b of the outer electrode 35.
Since the inner electrode 34 is made of a disk-shaped member as described above, only that surface of the inner electrode 34 extending parallel to the placed wafer W is exposed to the processing space S. Therefore, the secondary electrons emitted from the surface of the inner electrode 34 are uniformly distributed from a central portion to a circumferential edge portion of the wafer W. Thus, RIE processing is promoted on the entire surface of the placed wafer W.
As described above, both the first and second secondary electron emission surfaces 35 a, 35 b of the outer electrode 35 are directed to the circumferential edge portion of the placed wafer W. Therefore, secondary electrons emitted from the first and second secondary electron emission surface 35 a, 35 b are superimposed on one another at locations right above the circumferential edge portion of the place wafer W. As a result, it is possible to adequately increase the electron density right above the circumferential edge portion of the placed wafer W, and RIE processing on the circumferential edge portion of the placed wafer W is promoted.
Operations of component parts of the substrate processing apparatus 10 are controlled by a CPU of a control unit (not shown) of the substrate processing apparatus 10.
With the upper electrode 31 as an electrode structure according to this embodiment, the second DC power source 38 is connected to the outer electrode 35 facing the circumferential edge portion of the placed wafer W, and a DC voltage is applied to the outer electrode 35. When applied with the DC voltage, the outer electrode 35 draws cations in the plasma and emits secondary electrons, whereby the electron density in the processing space S right above the circumferential edge portion of the placed wafer W can be increased. The outer electrode 35 has its first secondary electron emission surface 35 a extending parallel to the placed wafer W and its second secondary electron emission surface 35 b extending obliquely relative to the electron emission surface 35 a toward the placed wafer W, and secondary electrons are emitted from the electron emission surfaces 35 a, 35 b. Since both the surfaces 35 a, 35 b are directed to the circumferential edge portion of the placed wafer W, the electron density right above the circumferential edge portion of the placed wafer W can adequately be increased, whereby RIE processing on the circumferential edge portion of the wafer W can be promoted.
With the upper electrode 31, the electron density right above the circumferential edge portion of the placed wafer W can be adequately increased, without the need of increasing the area of the surface of the outer electrode 35 facing the wafer W. As a result, it is possible to reduce an amount of use of high-priced single crystal silicon, making it possible to decrease the fabrication cost of the upper electrode 31.
In the upper electrode 31, both the first and second secondary electron emission surfaces 35 a, 35 b are directed to the circumferential edge portion of the placed wafer W. However, the second secondary electron emission surface 35 b may not be directed to the circumferential edge portion of the placed wafer W. For example, the electron emission surface 35 b may extend perpendicular to the first secondary electron emission surface 35 a. Even in that case, the electron density at a part facing the circumferential edge portion of the placed wafer W can be adequately increased since secondary electrons emitted from the electron emission surfaces 35 a, 35 are superimposed on one another in the part in the processing space S facing the circumferential edge portion of the placed wafer W.
Furthermore, the second secondary electron emission surface 35 b may not be a flat surface, but may be a parabolic surface directed to the circumferential edge portion of the placed wafer W. In that case, it is possible to emit secondary electrons from the electron emission surface 35 b concentratedly toward the circumferential edge portion of the placed wafer W, whereby the electron density right above the circumferential edge portion of the wafer W can further be adequately increased.
In the above described embodiment, the substrate subjected to etching processing is a semiconductor wafer W. However, the substrate subjected to etching processing is not limited thereto, and may be, for example, a glass substrate for a display such as LCD (liquid crystal display) or FPD (flat panel display).

EXAMPLE

Next, an example of this invention is described.

Example 1

The present inventors performed RIE processing on a placed wafer W by using the substrate processing apparatus 10, and measured the etching rate by the RIE processing at a circumferential edge portion of the wafer W. The result is shown by a black-circle mark in a graph of FIG. 5.

Comparative Examples 1, 2

The present inventors prepared two outer electrodes each only having a surface extending parallel to a placed wafer W and having different surface areas, and then replaced the outer electrode 35 of the substrate processing apparatus 10 with one of the prepared outer electrodes. Subsequently, RIE processing was performed on the placed wafer W, and the etching rate by the RIE processing at a circumferential edge portion of the placed wafer W was measured (Comparative Example 1). Then, the outer electrode was replaced by another outer electrode, and a similar measurement was made (Comparative Example 2). The results are shown by black diamond-shaped marks in the graph of FIG. 5.
In the graph of FIG. 5, surface area of outer electrode is taken along abscissa and etching rate is taken along ordinate. The surface area of outer electrode in Example 1 corresponds to the total area of the first and second secondary electron emission surfaces 35 a, 35 b of the outer electrode 35. The surface area of outer electrode in each of Comparative Examples 1, 2 corresponds to the area of the surface of the outer electrode extending parallel to the placed wafer W. In the graph of FIG. 5, the surface areas of the outer electrodes of and the etching rates in Example 1 and Comparative Examples 1, 2 are each represented by a numerical value which assumes a value of 1 for those of Comparative Example 1. It is understood from the graph of FIG. 5 that, by providing the second secondary electron emission surface 35 b extending obliquely relative to the first secondary electron emission surface 35 a rather than by increasing the surface area of outer electrode, the electron density right above the circumferential edge portion of the placed wafer W can be efficiently and adequately increased, whereby RIE processing at the circumferential edge portion of the placed wafer W can be promoted.

Claims

1. An electrode structure disposed inside a processing chamber of a substrate processing apparatus for performing plasma processing on a substrate, so as to face the substrate placed on a mounting table in the processing chamber, comprising:

an inner electrode disposed to face a central portion of the substrate; and

an outer electrode disposed to face a circumferential edge portion of the substrate,

wherein said the inner electrode is connected to a first DC power source,

said outer electrode is connected to a second DC power source, and

said outer electrode has a first surface thereof extending parallel to the substrate and a second surface thereof obliquely extending relative to the first surface of said outer electrode.

2. The electrode structure according to claim 1, wherein the first and second surfaces of said outer electrode are directed toward the circumferential edge portion of the substrate.

3. A substrate processing apparatus including a processing chamber for housing a substrate, a mounting table disposed inside the processing chamber and adapted to place the substrate thereon, and an electrode structure disposed inside the processing chamber so as to face the substrate placed on the mounting table, the substrate processing being adapted to perform plasma processing on the substrate, wherein:

the electrode structure includes an inner electrode thereof disposed to face a central portion of the substrate and an outer electrode thereof disposed to face a circumferential edge portion of the substrate,

said inner electrode is connected to a first DC power source and said outer electrode is connected to a second DC power source, and

4. The substrate processing apparatus according to claim 3, wherein the first and second surfaces of said outer electrode are directed toward the circumferential edge portion of the substrate.