CN101515561A - Method capable of improving quality for producing mosaic structures capable of improving quality for improving quality - Google Patents
Method capable of improving quality for producing mosaic structures capable of improving quality for improving quality Download PDFInfo
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- CN101515561A CN101515561A CNA2008100338154A CN200810033815A CN101515561A CN 101515561 A CN101515561 A CN 101515561A CN A2008100338154 A CNA2008100338154 A CN A2008100338154A CN 200810033815 A CN200810033815 A CN 200810033815A CN 101515561 A CN101515561 A CN 101515561A
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Abstract
The invention provides a method capable of improving the quality for producing mosaic structures capable of improving the quality capable of improving the quality. In the prior art, an inter-metal dielectric layer is deposited and then is not subjected to planarization treatment, sowhich causes that the bridging phenomenon is easy to appear on the mosaic structures in the inter-metal dielectric layer during subsequent production. The method comprises the following steps: firstly, providing a silicon substrate with an interlayer dielectric layer is provided; secondly, depositingthen the inter-metalinterlayer dielectric layer is deposited withon the interlayerinter-metal dielectric layer; thirdly, performingthen the chemical-mechanical polishing is performed to flattenon the inter-metal dielectric layer for planarization; fourthly,then forming accommodationreceiving grooves for accommodatingreceiving the mosaic structures are formed on the inter-metal dielectric layer through photoetching technology and etching process; then fifthly, producing diffusion barrier layers are produced on the groove walls of the receiving accommodation grooves; and then finally, filling metal copper is filled in the receiving accommodation grooves to form and forming the mosaic structures through by a chemical-mechanical polishing process of the copper. The adoption of the method can avoid the bridging phenomenon among the mosaic structures further to improve the quality of the mosaic structures and the rate of finished products of devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of mosaic structure production method that improves the quality.
Background technology
Enter the epoch of deep-submicron when semiconductor device after, the current density in the plain conductor constantly increases, and the response time constantly shortens, and the conventional aluminum lead does not more and more satisfy needs.Copper conductor has than low resistivity of aluminum conductor and high anti-electron transfer ability, so copper wiring (or being called mosaic structure production method) becomes the main flow technology of semicon industry gradually.Prior art is when carrying out copper wiring, one silicon substrate of making interlayer dielectric layer (ILD) on it is provided earlier, then at dielectric layer (IMD) between plated metal on this interlayer dielectric layer, in intermetallic dielectric layer, be formed for the containing groove of ccontaining mosaic texture afterwards by photoetching and etching technics, on this containing groove cell wall, make diffusion impervious layer at last and in this containing groove, fill metallic copper and carry out copper CMP technology forming mosaic texture.
But the mosaic texture that forms by above-mentioned copper wiring is prone to the residual and consequent bridge joint of copper (bridge) phenomenon, referring to Fig. 1, first, second and the 3rd mosaic texture 10,11 and 12 are produced in the intermetallic dielectric layer 1, the residual structure 13 of copper has appearred in first and second mosaic textures 10 and 11, and the residual structure 13 of this copper can cause first and second mosaic textures 10 and 11 s' bridge joint phenomenon.This bridge joint phenomenon can not effectively be removed by the parameter of adjusting copper CMP technology, trace it to its cause find to be since intermetallic dielectric layer 1 surface unevenness caused, prior art does not have smooth its surperficial step behind dielectric layer between plated metal 1, along with further reducing of the minimum feature size of semiconductor device, can more and more frequent appearance by the bridge joint phenomenon of the mosaic texture that unevenness caused on intermetallic dielectric layer 1 surface, so therefore finished semiconductor device product rate also can reduce.
Therefore, how to provide a kind of mosaic structure production method that improves the quality to avoid the mosaic texture bridge joint phenomenon that unevenness was caused because of the inter-metal medium surface, and then can improve the quality of mosaic texture and the rate of finished products of device, become the technical problem that industry needs to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of mosaic structure production method that improves the quality, the mosaic texture bridge joint phenomenon that unevenness caused can be avoided by described method, and then the quality of mosaic texture and the rate of finished products of device can be improved because of the inter-metal medium laminar surface.
The object of the present invention is achieved like this: a kind of mosaic structure production method that improves the quality may further comprise the steps: a, provide a silicon substrate, be manufactured with interlayer dielectric layer on it; B, at dielectric layer between plated metal on this interlayer dielectric layer; C, on this intermetallic dielectric layer, be formed for the containing groove of ccontaining mosaic texture by photoetching and etching technics; D, on this containing groove cell wall, make diffusion impervious layer; E, in this containing groove, fill metallic copper; F, form mosaic texture by copper CMP technology; This method is also carried out a chemical-mechanical polishing step with smooth this intermetallic dielectric layer between step b and c.
In the above-mentioned mosaic structure production method that improves the quality, this interlayer dielectric layer is a silicon nitride.
In the above-mentioned mosaic structure production method that improves the quality, this intermetallic dielectric layer is silicon dioxide or the silicon dioxide that is doped with boron, phosphorus or fluorine element.
In the above-mentioned mosaic structure production method that improves the quality, this diffusion impervious layer is the tantalum nitride and the tantalum of stacked on top of one another.
In the above-mentioned mosaic structure production method that improves the quality, in step e, in this containing groove, fill metallic copper by electroplating technology.
With after having deposited intermetallic dielectric layer, it is not carried out planarization in the prior art, causing the follow-up mosaic texture that is produced in this intermetallic dielectric layer to be prone to the bridge joint phenomenon compares, the mosaic structure production method that improves the quality of the present invention after having deposited intermetallic dielectric layer on the silicon substrate also by smooth its surface of chemico-mechanical polishing, so this on the intermetallic dielectric layer of smooth processing by photoetching, etching, the probability that the bridge joint phenomenon appears in the mosaic texture that electroplating deposition and CMP (Chemical Mechanical Polishing) process form reduces greatly, and then can improve the quality of mosaic texture and the rate of finished products of device.
Description of drawings
The mosaic structure production method that improves the quality of the present invention is provided by following embodiment and accompanying drawing.
The schematic diagram of the mosaic texture that Fig. 1 makes for prior art;
Fig. 2 is the flow chart of the mosaic structure production method that improves the quality of the present invention;
Fig. 3 to Fig. 8 is respectively and finishes among Fig. 2 the cutaway view of silicon substrate behind the step S20 to S26.
Embodiment
Below will be described in further detail the mosaic structure production method that improves the quality of the present invention.
Referring to Fig. 2, the mosaic structure production method that improves the quality of the present invention at first carries out step S20, and a silicon substrate is provided, and is manufactured with interlayer dielectric layer on it.In the present embodiment, described interlayer dielectric layer is a silicon nitride.
Referring to Fig. 3, cutaway view of the silicon substrate that provides among the step S20 has been provided for it, as shown in the figure, is manufactured with semiconductor device, ground floor metal 20 and interlayer dielectric layer 21 on the silicon substrate 2.
Then continue step S21, at dielectric layer between plated metal on the described interlayer dielectric layer, described intermetallic dielectric layer is silicon dioxide or the silicon dioxide that is doped with boron, phosphorus or fluorine element.
Then continue step S22, carry out chemico-mechanical polishing with smooth described intermetallic dielectric layer.
Referring to Fig. 4, in conjunction with referring to Fig. 3, Fig. 4 has shown the cutaway view of silicon substrate behind the completing steps S22, and as shown in the figure, intermetallic dielectric layer 1 is deposited on the interlayer dielectric layer 21, and its surface has high evenness because of having carried out CMP (Chemical Mechanical Polishing) process.
Then continue step S23, on described intermetallic dielectric layer, be formed for the containing groove of ccontaining mosaic texture by photoetching and etching technics.
Referring to Fig. 5, in conjunction with referring to Fig. 3 and Fig. 4, Fig. 5 has shown the cutaway view of silicon substrate behind the completing steps S23, and as shown in the figure, first, second and the 3rd containing groove 100,110 and 120 are arranged in the intermetallic dielectric layer 1 from left to right successively.
Then continue step S24, on described containing groove cell wall, make diffusion impervious layer.In the present embodiment, described diffusion impervious layer is the tantalum nitride and the tantalum of stacked on top of one another.
Referring to Fig. 6, in conjunction with referring to Fig. 3 to Fig. 5, Fig. 6 has shown the cutaway view of silicon substrate behind the completing steps S24, and as shown in the figure, diffusion impervious layer 3 is deposited on the cell wall of first, second and the 3rd containing groove 100,110 and 120.
Then continue step S25, in described containing groove, fill metallic copper.In the present embodiment, in described containing groove, fill metallic copper by electroplating technology.
Referring to Fig. 7, in conjunction with referring to Fig. 3 to Fig. 6, Fig. 7 has shown the cutaway view of silicon substrate behind the completing steps S25, and as shown in the figure, metallic copper 4 is deposited in first, second and the 3rd containing groove 100,110 and 120 and covers on the intermetallic dielectric layer 1.
Then continue step S26, form mosaic texture by copper CMP technology.
Referring to Fig. 8, in conjunction with referring to Fig. 3 to Fig. 7, Fig. 8 has shown the cutaway view of silicon substrate behind the completing steps S26, as shown in the figure, first, second and the 3rd mosaic texture 10,11 and 12 are separately positioned in first, second and the 3rd containing groove 100,110 and 120, with compare among Fig. 1, the residual structure 13 of copper has not appearred in first and second mosaic textures 10 among Fig. 8 and 11, so the bridge joint phenomenon that causes because of copper is residual can not appear in first and second mosaic textures 10 and 11 yet among Fig. 8.
In sum, the mosaic structure production method that improves the quality of the present invention after having deposited intermetallic dielectric layer on the silicon substrate also by smooth its surface of chemico-mechanical polishing, so the probability that bridge joint phenomenon occur in the described mosaic texture that forms by photoetching, etching, electroplating deposition and CMP (Chemical Mechanical Polishing) process on the intermetallic dielectric layer of smooth processing reduces greatly, and then can improve the quality of mosaic texture and the rate of finished products of device.
Claims (5)
1, a kind of mosaic structure production method that improves the quality may further comprise the steps: a, provide a silicon substrate, be manufactured with interlayer dielectric layer on it; B, at dielectric layer between plated metal on this interlayer dielectric layer; C, on this intermetallic dielectric layer, be formed for the containing groove of ccontaining mosaic texture by photoetching and etching technics; D, on this containing groove cell wall, make diffusion impervious layer; E, in this containing groove, fill metallic copper; F, form mosaic texture by copper CMP technology; It is characterized in that this method is also carried out a chemical-mechanical polishing step with smooth this intermetallic dielectric layer between step b and c.
2, the mosaic structure production method that improves the quality as claimed in claim 1 is characterized in that, this interlayer dielectric layer is a silicon nitride.
3, the mosaic structure production method that improves the quality as claimed in claim 1 is characterized in that, this intermetallic dielectric layer is silicon dioxide or the silicon dioxide that is doped with boron, phosphorus or fluorine element.
4, the mosaic structure production method that improves the quality as claimed in claim 1 is characterized in that, this diffusion impervious layer is the tantalum nitride and the tantalum of stacked on top of one another.
5, the mosaic structure production method that improves the quality as claimed in claim 1 is characterized in that, in step e, fills metallic copper by electroplating technology in this containing groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNA2008100338154A CN101515561A (en) | 2008-02-22 | 2008-02-22 | Method capable of improving quality for producing mosaic structures capable of improving quality for improving quality |
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| CNA2008100338154A CN101515561A (en) | 2008-02-22 | 2008-02-22 | Method capable of improving quality for producing mosaic structures capable of improving quality for improving quality |
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| CN101515561A true CN101515561A (en) | 2009-08-26 |
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| CNA2008100338154A Pending CN101515561A (en) | 2008-02-22 | 2008-02-22 | Method capable of improving quality for producing mosaic structures capable of improving quality for improving quality |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534017A (en) * | 2018-12-26 | 2019-12-03 | 友达光电股份有限公司 | Display panel |
| CN117724207A (en) * | 2024-02-18 | 2024-03-19 | 上海铭锟半导体有限公司 | Amorphous silicon optical waveguide manufacturing method and amorphous silicon optical waveguide |
-
2008
- 2008-02-22 CN CNA2008100338154A patent/CN101515561A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534017A (en) * | 2018-12-26 | 2019-12-03 | 友达光电股份有限公司 | Display panel |
| CN110534017B (en) * | 2018-12-26 | 2021-03-26 | 友达光电股份有限公司 | Display panel |
| CN117724207A (en) * | 2024-02-18 | 2024-03-19 | 上海铭锟半导体有限公司 | Amorphous silicon optical waveguide manufacturing method and amorphous silicon optical waveguide |
| CN117724207B (en) * | 2024-02-18 | 2024-04-30 | 上海铭锟半导体有限公司 | Amorphous silicon optical waveguide manufacturing method and amorphous silicon optical waveguide |
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