CN117724207A - Amorphous silicon optical waveguide manufacturing method and amorphous silicon optical waveguide - Google Patents
Amorphous silicon optical waveguide manufacturing method and amorphous silicon optical waveguide Download PDFInfo
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Abstract
The invention relates to the technical field of semiconductors and discloses a manufacturing method of an amorphous silicon optical waveguide and the amorphous silicon optical waveguide. The invention solves the problems of large dependence on advanced photoetching machines and the like in the prior art when manufacturing submicron amorphous silicon optical waveguides.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an amorphous silicon optical waveguide and the amorphous silicon optical waveguide.
Background
The silicon photon (Silicon photonics) integrated chip technology has wide market space in the aspects of information transmission and signal processing, is being applied to the information transmission fields of optical communication, data centers and the like by partially replacing discrete photoelectric devices or photon integrated chips of III-V compound semiconductors, and has great development potential in the emerging fields of optical sensing (such as laser radar, optical gyroscope, biomedical detection) and optical computing (such as optical artificial intelligence, optical quanta and the like). Silicon photons benefit from the tremendous refractive index differences of silicon/silicon oxide material systems and Complementary Metal Oxide Semiconductor (CMOS) compatible fabrication processes, with the outstanding advantages of high integration, miniaturization, large-scale fabrication, and low cost, and the potential for optoelectronic integration (EPIC) with well-established CMOS circuits. However, the mainstream silicon photonics single crystal silicon-based material systems also present some technical and economic limitations: firstly, only expensive silicon-on-insulator (Silicon on insulator, SOI) substrates can be used, and neither the design nor the fabrication techniques of electrical chips on SOI substrates are as mature as conventional bulk silicon substrates; secondly, single crystal silicon optical waveguides and devices can only be processed by Front end of the line (FEOL), cannot be manufactured by Back end of the line (BEOL) with low temperature limitation, and can only be manufactured by inserting silicon optical devices and electrical devices in the Front process, so that the structure and the process are complex and are often restricted; third, single crystal silicon optical waveguides and devices can be integrated in the same layer (top layer silicon of SOI) generally, but in recent years, wafer bonding (wafer bonding) technology can theoretically bond multiple layers of single crystal silicon together, and the integrated practicality of the multi-layer single crystal silicon photonic device is not provided due to the problems of structural complexity, interlayer limitation, process cost and the like.
Amorphous silicon material can just overcome the above-mentioned limitations of single crystal silicon photonic integration. Pure amorphous silicon materials cannot be used because of high defect density, and amorphous silicon generally refers to hydrogenated amorphous silicon materials with hydrogen doped passivation to reduce defect density, and is called amorphous silicon for short. Amorphous silicon can be deposited on various semiconductor, glass, metal substrates or dielectric layers thereon; the low-temperature deposition characteristic (about 100-400 ℃) can be used for the semiconductor post-process, and amorphous silicon is deposited after a dielectric layer is covered on the circuit; amorphous silicon can also be deposited in multiple layers for three-dimensional integration of optical signal transmission and processing. As the most basic photonic integrated structure, submicron amorphous silicon optical waveguides achieve light propagation losses below 1dB/cm at 1550 nm in the infrared band, which is already close to the level of single crystal silicon optical waveguides (see Ryohei Takei et al, sub-1 dB/cm submicron-scale amorphous silicon waveguide for backend on-chip optical interconnect, OPTICS EXPRESS, 2014, 22 (4), pp. 4779-4788.). Active devices such as parametric amplifiers, all-optical signal processing devices, and all-optical modulators based on amorphous silicon materials have also been implemented. However, the horizontal structure size of the submicron amorphous silicon optical waveguide and the device can be as low as deep as submicron or even tens of nanometers according to design requirements, and the resolution of the typical photoetching machines (such as commonly used I-line and G-line light source stepping photoetching machines or older contact type and proximity type photoetching machines) at the later stage of a semiconductor commercial manufacturing factory is often lower than that of the advanced photoetching equipment at the former stage, so that the fine photoetching of the amorphous silicon optical waveguide is difficult to support, and the design and manufacturing limitation of the optical waveguide and the optical path are caused; advanced lithography machines equipped with e.g. KrF, arF light sources in the factory for fine etching of amorphous silicon optical waveguides are very uneconomical, and the subsequent amorphous silicon layer is lithographically processed with the advanced lithography machines in the front-end, involving additional costs and risks for metal impurity contamination management, which are not generally allowed in commercial venues. Therefore, it is necessary to propose a new structure and preparation method of amorphous silicon optical waveguide, which utilizes the micron resolution photoetching machine at the back of semiconductor factory to realize the deep submicron horizontal dimension processing of amorphous silicon optical waveguide, and provides greater design and manufacturing freedom for amorphous silicon photon integration.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a manufacturing method of an amorphous silicon optical waveguide and the amorphous silicon optical waveguide, and solves the problems that the prior art has too large dependence on an advanced photoetching machine when manufacturing submicron amorphous silicon optical waveguides.
The invention solves the problems by adopting the following technical scheme:
a method for manufacturing amorphous silicon optical waveguide adopts micron-sized photoetching machine and dry etching to generate dielectric steps with deep submicron height, and adopts amorphous silicon deposition with deep submicron thickness and maskless dry etching back to obtain amorphous silicon optical waveguide with deep submicron width.
As a preferred technical scheme, the method comprises the following steps:
s1, preparing a substrate wafer;
s2, depositing a first dielectric layer as a lower cladding of the amorphous silicon optical waveguide;
s3, photoetching and dry etching are adopted to etch the first dielectric layer to form a step;
s4, depositing an amorphous silicon layer to serve as a core layer of the amorphous silicon optical waveguide;
s5, etching back the amorphous silicon layer to form a core of the amorphous silicon optical waveguide;
s6, depositing a second dielectric layer as an upper cladding of the amorphous silicon optical waveguide;
and S7, polishing the second dielectric layer until the surface is flat.
As a preferred technical scheme, in the step S2, a first dielectric layer is deposited at 100-400 ℃ by adopting a plasma enhanced chemical vapor deposition method.
In step S5, the method of automatic stop of etching by end point detection is selected to remove the excessive amorphous silicon, or a fixed etching time is calculated according to the deposition thickness and the etching rate and the overetching is increased by 5% -15%.
As a preferred embodiment, the substrate wafer is made of a semiconductor, metal, inorganic nonmetal or organic resin material.
In step S2, the material of the first dielectric layer is silicon oxide, silicon oxynitride, silicon nitride or a low-dielectric-constant dielectric.
As a preferred technical solution, in step S3, the amorphous silicon layer is deposited to a thickness ranging from 0.1 to 3 μm.
In step S6, the second dielectric layer is made of silicon oxide, silicon oxynitride, silicon nitride or a low-k dielectric.
As a preferable technical scheme, the height, width and shape of the amorphous silicon optical waveguide are controlled by adjusting the height of the dielectric step, the deposition thickness and the etching back amount of the amorphous silicon.
The utility model provides an amorphous silicon optical waveguide, including the substrate wafer, first dielectric layer, the amorphous silicon layer, the second dielectric layer, the top of substrate wafer is located to first dielectric layer, the upper surface of first dielectric layer is including the first horizontal segment that connects gradually, first vertical section, the second horizontal segment, the first horizontal segment is higher than the height of second horizontal segment distance substrate wafer from the height of substrate wafer, the lower surface of second dielectric layer is including the third horizontal segment that connects gradually, the arc limit, the fourth horizontal segment, the third horizontal segment is located the height of being higher than the height of fourth horizontal segment distance substrate wafer from the height of substrate wafer from the third horizontal segment, first horizontal segment is laminated with the third horizontal segment, the second horizontal segment is laminated with the fourth horizontal segment, first vertical segment, the second horizontal segment, the arc limit constitutes an accommodation space, the amorphous silicon layer is located in the accommodation space, the surface and the first vertical segment of amorphous silicon layer, the second horizontal segment, the arc limit is laminated respectively.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention gets rid of the dependence of the manufacture of submicron amorphous silicon optical waveguide on an advanced photoetching machine: amorphous silicon is deposited on the lower cladding medium step, the covering characteristic of a PECVD deposited amorphous silicon film and the excellent directionality of plasma dry etching are utilized to convert the key width dimension of the optical waveguide determined by the resolution of a conventional photoetching machine into the dimension controlled by the deposited thickness of the amorphous silicon film, so that a semiconductor factory can manufacture amorphous silicon optical waveguides with deep submicron or even tens of nanometers in width under the condition of not having an advanced photoetching machine;
(2) The invention has simple structure and process, and can save the manufacturing cost: compared with the conventional method of defining amorphous silicon optical waveguide by photoetching and dry etching, the invention has simple structure and process, does not additionally increase material layers and photoetching times, replaces the high-resolution amorphous silicon optical waveguide photoetching of the conventional method by low-resolution dielectric step photoetching, and remarkably saves manufacturing cost from the aspects of photoetching equipment, photoetching plates, photoresist materials and the like.
Drawings
FIG. 1 is a schematic view of a cross-section of an amorphous silicon optical waveguide obtained by conventional processing;
FIG. 2 is a schematic diagram of a cross-section of an amorphous silicon optical waveguide according to the present invention;
FIG. 3 is a flow chart of a method for fabricating an amorphous silicon optical waveguide according to the present invention;
FIG. 4 is a schematic diagram of the steps of a method for fabricating an amorphous silicon optical waveguide according to the present invention;
FIG. 5 is one of the optical mode field simulation diagrams of an amorphous silicon optical waveguide of the present invention;
FIG. 6 is a second optical mode field simulation of an amorphous silicon optical waveguide of the present invention;
fig. 7 is a third optical mode field simulation of the amorphous silicon optical waveguide of the present invention.
The reference numerals in the drawings and their corresponding names: 1. the substrate wafer comprises 2 parts of a first dielectric layer, 3 parts of an amorphous silicon layer, 4 parts of a second dielectric layer, 21 parts of a first horizontal section, 22 parts of a first vertical section, 23 parts of a second horizontal section, 41 parts of a third horizontal section, 42 parts of a third horizontal section, a cambered edge, 43 parts of a fourth horizontal section.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but embodiments of the present invention are not limited thereto.
Example 1
As shown in fig. 1 to 7, the present invention aims to propose a new amorphous silicon optical waveguide structure and a manufacturing method thereof, which can be manufactured by using a micron resolution photoetching machine at the back of a semiconductor chip factory, and is not limited by the resolution thereof, so that the deep submicron width processing of the amorphous silicon optical waveguide can be realized. The new method has simple structure, feasible process and good compatibility with the subsequent equipment, materials and process of the semiconductor chip factory.
Fig. 1 shows a cross section of an optical waveguide obtained by a conventional processing manner, a dielectric lower cladding layer (a first dielectric layer 2) and an amorphous silicon core layer are sequentially deposited on a substrate wafer 1, amorphous silicon is subjected to photoetching and etching to form an optical waveguide core (an amorphous silicon layer 3) with a rectangular cross section, and then the dielectric upper cladding layer (a second dielectric layer 4) is deposited and planarized to complete the manufacture of the optical waveguide. Height of optical waveguidehThe target height of tens of nanometers to several micrometers can be easily achieved, depending on the thickness of the amorphous silicon deposit; width of optical waveguidewThe minimum width is limited by the minimum linewidth that the photoresist can process, as determined by the stripe width of the photoresist.
Fig. 2 shows a cross section of an amorphous silicon optical waveguide obtained by means of side wall etching (Sidewall spacer etch) according to the invention. Fig. 4 shows the process steps of a method for fabricating an amorphous silicon optical waveguide according to the present invention. First, a dielectric lower cladding layer (a first dielectric layer 2) is deposited on a substrate wafer 1, and the dielectric is subjected to photoetching and partial etching to form a dielectric layer with the height ofhAn amorphous silicon layer 3 is deposited, excessive amorphous silicon is removed by dry etching back (etching back) and is etched in an automatic stopping mode by end point detection (Endpoint detection), or etching time is calculated according to the etching rate according to the deposition thickness of the amorphous silicon and the over etching is increased by a slight degree of 5% -15%), an amorphous silicon optical waveguide with a quasi-sector section formed by two straight sides and one arc side is formed at the step (the upper surface of a first dielectric layer 2 comprises a first horizontal section 21, a first vertical section 22 and a second horizontal section 23 which are sequentially connected, and the lower surface of a second dielectric layer 4 comprises a third horizontal section 41, an arc side 42 and a fourth horizontal section 43 which are sequentially connected). Is called quasi-fan shape because of the two sidesh、wThe lengths are not necessarily equal, nor is the arc edge a standard arc. In the end point detection automatic stop mode or time full etching (By time full etch) mode of amorphous silicon dry etching, if the step heighthThickness of amorphous silicon film depositiont a-Si Comparable (the dimension ratio is within 5 times), the bottom width of the amorphous silicon after etching is finishedwAboutt a-Si Mainly determined by the thin film deposition characteristics and dry etching characteristics, irrespective of the height of the step. High optical waveguide cross sectionhI.e. the step height. Thus, deep submicron height dielectric step heights can be created using micron scale lithography and dry etchinghAnd (3) carrying out deep submicron-width amorphous silicon optical waveguide by matching with deep submicron-thickness amorphous silicon deposition and maskless dry etching back. That is, the width of the optical waveguide, which is typically defined by photolithography, is translated into the thickness of the thin film deposition and is therefore no longer limited by the resolution of the micro-lithography machine. In the case of increasing over etching (Overetch), the height and width of the amorphous silicon optical waveguide are further reduced, at which time, since the large area amorphous silicon etching is already completed,the plasma can be excessively concentrated to the amorphous silicon region remained at the step, causing uncontrollable amorphous silicon morphology and serious plasma damage. Therefore, the mode of automatic stopping etching by end point detection should be selected, or the etching time should be calculated according to the deposition thickness and the etching rate, and the over etching should be controlled between 5% and 15%, so as to avoid a large amount of over etching. In short, by properly adjusting the height of the medium step and the thickness of the amorphous silicon deposition within a certain range (the proportion is not more than 5 times in general), the width, the height and the shape of the amorphous silicon optical waveguide can be controlled, and the deep submicron optical waveguide scale processing and the optical mode field control can be conveniently realized without being limited by the resolution of a photoetching machine.
Further description is made of the amorphous silicon optical waveguide structure defined by the side wall etching in fig. 2:
the substrate wafer 1 may be a semiconductor material substrate such as bulk silicon, silicon on insulator SOI, gallium arsenide, indium phosphide, silicon carbide, gallium nitride, aluminum nitride, diamond, etc., a metal material substrate such as aluminum, copper stainless steel, etc., a non-metal inorganic material substrate such as quartz, glass, ceramic, etc., or a temperature-resistant organic resin substrate; the substrate can be a single material or a stack of multiple layers of materials without a fabricated structure, or can be a wafer from which discrete devices, integrated circuits, or optoelectronic integrated chips have been fabricated; the substrate thickness may be from tens of microns to hundreds of microns.
The first dielectric layer 2 serves as a lower cladding of the amorphous silicon optical waveguide on the one hand, and on the other hand, the layer forms a step after being subjected to photoetching and etching to form part of thickness, so that the position and the height of the amorphous silicon optical waveguide are defined; the material is silicon oxide, silicon oxynitride, silicon nitride or various low dielectric constant media (often doped silicon oxide) adopted in the subsequent process of a semiconductor, preferably silicon oxide, well matched with the silicon material and most commonly used as a cladding in a silicon optical waveguide structure; depositing by adopting a chemical vapor deposition mode, preferably a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) mode, and depositing at 100-400 ℃; step height in first dielectric layerhAt the same time, the height of the amorphous silicon optical waveguide needs to be considered, the design of the optical waveguide needs to be considered, and the steps cannot be passedThe low dry etching back of amorphous silicon to form optical waveguide is difficult to control, at least should be takenhNot less than 0.05 micron; deposition thickness of first dielectric layert ox1 Firstly, the optical mode field is limited by considering that the amorphous silicon optical waveguide can be effectively coated with the optical mode field with enough thickness (such as at least 1 micron) after the subsequent step etchingt ox1 ≥h+1, second, facilitate forming the through hole to realize the electrical connection of amorphous silicon layer or subsequent 3D integration layer and substrate device layer, the first dielectric layer is not suitable to exceed 3 microns, therefore the thickness range is takenh+1≤t ox1 And less than or equal to 3 micrometers.
The amorphous silicon layer 3 serves as a core layer of the amorphous silicon optical waveguide. The PECVD amorphous silicon is preferably deposited by adopting a chemical vapor or physical vapor mode. PECVD is a common device for the subsequent process of a semiconductor factory, can realize deposition at a lower temperature, and has uniform film forming property and good thickness uniformity. The deposition thickness of amorphous silicon is in the range of 0.1-3 microns, mainly taking into account the dimensional requirements of the optical waveguide design and allowing a degree of over-etching.
The second dielectric layer 4 serves as an upper cladding of the amorphous silicon optical waveguide, and the surface is flattened after the subsequent chemical mechanical polishing step; the material is silicon oxide, silicon oxynitride, silicon nitride or various low dielectric constant media adopted in the subsequent process of a semiconductor, preferably silicon oxide, well matched with silicon material, and most commonly used as a cladding in a silicon optical waveguide structure; adopting a chemical vapor deposition mode, preferably a PECVD mode; the deposited thickness of the dielectric is mainly considered to have enough thickness to cover the amorphous silicon optical waveguide to limit the optical mode field after the subsequent chemical mechanical polishing (Chemical mechanical polishing, CMP) step, and the deposited thickness range is 1-3 microns.
Fig. 3 shows the process steps of the method for manufacturing amorphous silicon optical waveguide with quasi-sector cross section, which comprises the following specific processes: starting from a substrate wafer 1; depositing a first dielectric layer 2 on the surface of a substrate; photoetching and dry etching part of the thickness of the first medium to form a step; depositing an amorphous silicon layer; etching back the amorphous silicon layer according to the deposition thickness by a maskless dry method; depositing a second dielectric layer to form a coating on the amorphous silicon optical waveguide from the periphery and the upper part; and carrying out chemical mechanical polishing on the second dielectric layer until the surface is flat, thus completing the manufacture of the amorphous silicon optical waveguide with the quasi-sector cross section.
The invention has the following characteristics:
an amorphous silicon optical waveguide structure with a quasi-sector cross-section shape formed by constructing a dielectric step and etching back amorphous silicon; forming the amorphous silicon optical waveguide structure; the deposition mode, the temperature range and the thickness range of amorphous silicon; material selection, deposition mode, temperature range and thickness range of the upper and lower medium cladding layers; dielectric step etch heighthAnd amorphous silicon deposition thicknesst a-Si Is not more than 5 times, 1/5 < >h/t a-Si < 5; maskless masking state of amorphous silicon etching, dry plasma etching mode, automatic stop mode of etching end point detection or mode of calculating etching time according to thickness and controlling over etching to 5% -15%.
Example 2
As further optimization of embodiment 1, as shown in fig. 1 to 7, this embodiment further includes the following technical features on the basis of embodiment 1:
fig. 3 shows a process flow of the method for fabricating an amorphous silicon optical waveguide of the present invention.
S1, starting from an 8-inch P (100) silicon substrate wafer with a thickness of 725 microns and a resistivity of about 10 ohms for the completed CMOS ICCm.
S2, depositing a silicon oxide layer at 400 ℃ in a PECVD mode to form a CMOS IC with the substrate wafer covered with 2 microns, and subsequently manufacturing a silicon oxide step and serving as a lower cladding of the amorphous silicon optical waveguide.
S3, etching the first silicon oxide layer with a partial thickness of 0.4 microns by photoetching and dry method to form a silicon oxide step with a height of 0.4 microns.
S4, depositing an amorphous silicon layer at 400 ℃ in a PECVD mode to cover the silicon oxide layer with the step height of 0.4 microns. Due to the deposition and capping characteristics of the PECVD amorphous silicon film, an amorphous silicon thickness of up to about 1 micron is formed at the step, gradually decreasing to the right along the step, until returning to a deposition thickness of 0.6 microns away from the step impact.
S5, under the condition of no mask masking, etching and removing amorphous silicon in an automatic stop mode of end point detection of dry etching equipment. An amorphous silicon strip-shaped structure with a quasi-sector section is formed at the step after etching, and the maximum height at the sharp angle at the left side of the amorphous silicon strip-shaped structurehStep height 0.4 μm, bottom widthwAbout two-thirds of the thickness of the amorphous silicon deposit, i.e. 0.62/3=0.4 microns.
S6, depositing a second silicon dioxide layer at 400 ℃ for 2 micrometers in a PECVD mode, and forming coverage and surrounding of the strip-shaped amorphous silicon from the periphery and the upper side.
S7, polishing the second silicon dioxide layer by adopting a chemical mechanical polishing method to remove the amorphous silicon with the thickness of 0.2 microns, so as to remove the silicon oxide bulge at the optical waveguide and obtain the full surface flatness of the second silicon dioxide layer, thereby completing the manufacture of the amorphous silicon optical waveguide, wherein the cross section of the amorphous silicon optical waveguide is approximately 90 microns with the radius of 0.4 micronsQuasi sector.
The submicron amorphous silicon optical waveguide manufactured by the invention gets rid of the dependence on the resolution of a photoetching machine, but the section shape of the submicron amorphous silicon optical waveguide is quasi-sector, and deviates from the rectangular section shape of the optical waveguide manufactured by the conventional photoetching/etching method. In order to examine the confinement of light waves by sub-micron amorphous silicon optical waveguides with quasi-fan-shaped cross sections, mode field confinement in the optical waveguides was simulated using optical numerical simulation software, and the results are shown in figures 5 to 7 (in figure 5,h=w=0.4 microns; in the view of figure 6 of the drawings,hthe number of the particles is =0.22 micrometers,w=0.4 microns; in the view of figure 7 of the drawings,hthe number of the particles is =0.4 micrometers,w=0.22 micrometers). The cross-sectional shape of the polysilicon optical waveguide is controlled by controlling the thickness of the polysilicon deposit and the height of the step, thereby obtaining the required optical field mode. It can be seen in fig. 5 to 7w=h、w>hAndw<hUnder several conditions, the amorphous silicon optical waveguide can well limit the optical field mode and support the optical waveIs a normal transmission of (c).
As described above, the present invention can be preferably implemented.
All of the features disclosed in all of the embodiments of this specification, or all of the steps in any method or process disclosed implicitly, except for the mutually exclusive features and/or steps, may be combined and/or expanded and substituted in any way.
The foregoing description of the preferred embodiment of the invention is not intended to limit the invention in any way, but rather to cover all modifications, equivalents, improvements and alternatives falling within the spirit and principles of the invention.
Claims (9)
1. The method for manufacturing the amorphous silicon optical waveguide is characterized in that a micron-sized photoetching machine and dry etching are adopted to generate a dielectric step with a deep submicron height, and amorphous silicon deposition with a deep submicron thickness and maskless dry etching back are adopted to obtain the amorphous silicon optical waveguide with a deep submicron width;
the method comprises the following steps:
s1, preparing a substrate wafer;
s2, depositing a first dielectric layer as a lower cladding of the amorphous silicon optical waveguide;
s3, photoetching and dry etching are adopted to etch the first dielectric layer to form a step;
s4, depositing an amorphous silicon layer to serve as a core layer of the amorphous silicon optical waveguide;
s5, etching back the amorphous silicon layer to form a core of the amorphous silicon optical waveguide;
s6, depositing a second dielectric layer as an upper cladding of the amorphous silicon optical waveguide;
and S7, polishing the second dielectric layer until the surface is flat.
2. The method of fabricating an amorphous silicon optical waveguide according to claim 1, wherein in step S2, a first dielectric layer is deposited at 100-400 ℃ by a plasma enhanced chemical vapor deposition method.
3. The method of fabricating an amorphous silicon optical waveguide according to claim 1, wherein in step S5, the method of end point detection to automatically stop etching is selected to remove the excessive amorphous silicon, or a fixed etching time is calculated according to the deposition thickness and the etching rate and the overetching is increased by 5% -15%.
4. The method of fabricating an amorphous silicon optical waveguide according to claim 1, wherein the substrate wafer is made of a semiconductor, metal, inorganic non-metal or organic resin material.
5. The method of claim 1, wherein in step S2, the first dielectric layer is made of silicon oxide, silicon oxynitride, silicon nitride or a low-k dielectric.
6. The method of fabricating an amorphous silicon optical waveguide according to claim 1, wherein in step S3, the amorphous silicon layer is deposited to a thickness ranging from 0.1 to 3 μm.
7. The method of claim 1, wherein in step S6, the second dielectric layer is made of silicon oxide, silicon oxynitride, silicon nitride or a low-k dielectric.
8. The method according to any one of claims 1 to 7, wherein the height, width and shape of the amorphous silicon optical waveguide are controlled by adjusting the height of the dielectric step, the deposition thickness of amorphous silicon and the etching back amount.
9. The utility model provides an amorphous silicon optical waveguide, a serial communication port, including substrate wafer (1), first dielectric layer (2), amorphous silicon layer (3), second dielectric layer (4), the top of substrate wafer (1) is located in first dielectric layer (2), the upper surface of first dielectric layer (2) is including first horizontal segment (21) that connects gradually, first vertical section (22), second horizontal segment (23), first horizontal segment (21) are higher than the height of second horizontal segment (23) from substrate wafer (1), the lower surface of second dielectric layer (4) is including third horizontal segment (41) that connects gradually, arc limit (42), fourth horizontal segment (43), third horizontal segment (41) are located the height of being higher than the height of fourth horizontal segment (43) from substrate wafer (1), first horizontal segment (21) are laminated with third horizontal segment (41), second horizontal segment (23) are laminated with fourth horizontal segment (43), first horizontal segment (23) are located the vertical silicon containing space of second horizontal segment (23), the first arc containing space (3), the upper surface of second dielectric layer (4) is located, the arc edges (42) are respectively attached.
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