CN101512773A - 以密闭式晶胞结构增加信道密度的次微米平面半导体功率器件 - Google Patents

以密闭式晶胞结构增加信道密度的次微米平面半导体功率器件 Download PDF

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CN101512773A
CN101512773A CNA2007800231678A CN200780023167A CN101512773A CN 101512773 A CN101512773 A CN 101512773A CN A2007800231678 A CNA2007800231678 A CN A2007800231678A CN 200780023167 A CN200780023167 A CN 200780023167A CN 101512773 A CN101512773 A CN 101512773A
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雪克·玛力卡勒强斯瓦密
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Abstract

一种位于半导体衬底上的半导体功率器件，其包含有数个晶体管晶胞，而每一个晶胞具有一源极与一漏极区域，位于半导体衬底上的栅极区域的两侧。一栅极电极以电极层方式形成于栅极区域顶部，以控制源极与漏极区域间传输的电流。位于该半导体衬底顶部的栅极电极层被图案化为波状的长条，以本质上增加源极与漏极区域间且越过栅极的电流传导面积。

Description

以密闭式晶胞结构增加信道密度的次微米平面半导体功率器件
发明背景
1.技术领域
本发明涉及一种平面半导体功率器件，特别是关于一种新颖改良的次微米平面高功率半导体器件，其具有增加信道密度飞密闭式晶胞结构，例如半导体区域的每单位信道宽度。
2.先前技术
传统上藉由增加一特定金属氧化物半导体(MOS)晶体管区域的信道宽度来减少侧向MOS晶体管的启动电阻的技术已经到达限度。减少MOS晶体管蜂巢式阵列的启动电阻是一种期望，因为越低功率的损失就能传导高电流。在低电压应用中，例如，金属氧化物半导体场效应晶体管(MOSFET)应用于低于12伏特的低电压，相较于垂直双扩散式金属氧化物半导体场效应晶体管(VDMOS)而言，侧向MOSFET提供较低的器件电阻。然而，在一设计为大面积的侧向MOSFET，这贡献是来自于寄生电阻，如金属汇流的增加。在这个技术领域中的人皆知VDMOS可具有低启动电阻，当以蜂巢式晶胞的单位面积作为量测单位时。这样的低启动电阻被达成，利用整体表面积运作为一漏极电极。这样的结构允许垂直平面式晶体管高密度的以并联连接。这些平面垂直电流通道形成于源极区域，如覆盖顶表面的较大面积，与漏极电极，其连接至底表面。然而，在有些应用中VDMOS晶体管间无法方便的整合。在这些情况下，一般使用侧向MOS晶体管，而忽略垂直MOS晶体管相较于侧向MOS晶体管具有较低的启动电阻。
为了克服这个较高启动电阻的缺点，减少在侧向MOS晶体管中来自于金属与接触点所贡献的启动电阻的第一与最简单的方法就是增加接触点的宽度与金属条。然而，接触点金属条的较大宽度增加了被晶体管阵列占据的面积。在牺牲增加被晶体管阵列所占据的面积的情况下，可获得启动电阻的减少。在小型化电子装置的强烈需求理由下，这个方法无法提供有效地解答来减少侧向MOSFET器件的启动电阻。
晶胞阵列的数种布局探索着达到增加信道宽度每一单位面积(宽度/面积)。如图1A所示，其呈现出具有条状晶胞架构之侧向架构，其藉由并联连接数个MOSFET来获得大通道宽度。在这些条状晶胞阵列中，交替的漏极与源极条是交错放置，因此每一漏极/源极条共有邻近的源极/漏极，藉此减少器件总面积。由条状晶胞所增加的通道宽度能够增加回路中功率管理效率，例如开关调节器、低压差稳压器与离散式MOSFET传动器。
图1B显示出具有多晶硅栅极网状的蜂巢式晶体管。此多晶硅栅极网状如同方形晶胞。如同图1B所示，这些方形晶胞阵列更增加信道宽度每一单位面积(宽度/面积)，藉由描绘多晶硅线的网状，以形成交替的源极与漏极晶胞，其是藉由金属以并联方式连接。特别是，在美国专利号5,355,008的专利中，方形网状阵列是施行于MOSFET器件中。藉由将在多晶硅网状中的开口形成为方块的形状，例如具有一长对角线与一短对角线，源极与漏极金属条设置于短对角线的方向，可以形成较宽与较短，因此在无增加晶体管面积的情况下减少晶体管的启动电阻。
然而，如同对具有低启动电阻且适用于较大电流开关运作的半导体功率器件的有强烈需求，仍存在更进一步增加信道密度(W/area)的需要。因此，提供侧向晶体管晶胞阵列交替布局，以更增加信道宽度每一单位面积(W/area)。此外也更渴望能在无须牺牲晶体管面积的情况下，进一步减少启动电阻。更者，希望侧向晶体管阵列可以利用标准互补型金属氧物半导体(CMOS)技术制造，这样的话，上述讨论的困难点与限制皆可被解决。
发明内容
本发明的主要目的在于提供一种全新且改良的侧向半导体功率器件，其利用新的布局来增加单位面积信道宽度。利用这全新的晶胞布局阵列，启动电阻可以被进一步增加，从而适用于大电流开关运作，因此上述讨论的问题与困难点就可以被解决。
特别的是，本发明的另一目的是提供改良式侧向半导体功率器件，其是在一晶体管晶胞阵列上利用新的晶体管晶胞布局。在这个新的晶体管晶胞阵列，一般利用多晶硅来形成设置于源极与漏极区域间的栅极区域，并架构为具有波状结构。多晶硅栅极区域依照最小间距工艺技术来形成。因为多晶硅栅极区域被图案化为最小间距，伴随着介于形成为波形图案多晶硅栅极间的源极与漏极接触点，因此可达成较高信道密度。较高信道密度转换为较高信道宽度每单位面积(W/area)。
简单来说，在本发明的具体实施例中公开一位于半导体衬底上的侧向半导体功率器件。这个侧向半导体功率器件包含有数个晶体管晶胞，每一晶体管晶胞包含有一源极与一漏极，其位于半导体衬底上的栅极区域的两侧，其中一栅极电极以电极层形式形成于栅极区域顶部，以控制介于源极与漏极区域间的电流传输。位于半导体顶部的栅极电极层被图案化为波状结构，以本质上增加介于源极与漏极区域越过栅极的电流传导面积。
本发明更公开了一种架构位于半导体衬底上的半导体功率器件的方法。这个方法包含有形成数个晶体管晶胞的步骤，其中每一晶体管晶胞具有一源极与一漏极区域，其位于半导体衬底上的栅极区域的两侧。这个方法更包含有步骤：在栅极区域顶部形成一栅极电极层，以控制源极与漏极区域间的电流传输并且图案化栅极电极层以形成波状长条，以本质上增加介于源极与漏极区域越过栅极的电流传导面积。
下文将藉由具体实施例详加说明，将更容易了解本发明的目的、技术内容、特点及其所达到的技术效果。
附图说明
图1A至图1B分别为背景技术中利用具有条状晶胞与网格状晶胞来增加信道宽度单位面积的侧向MOSFET器件的俯视图；
图2A至图2E为本发明的新式布局的MOSFET晶胞阵列的俯视图，其中多晶硅栅极是架构为波状图案并且金属层是形成来用以与漏极、源极与栅极接触的。
图2F为以图2A中沿A-A’截面所获得的晶胞结构剖视图。
图3为本发明的另一具体实施例的俯视图。
具体实施方式
请参阅图2A至图2E，其呈现出图2A中多晶硅布局的一系列俯视图与本发明侧向半导体功率器件在形成接触点与源极、漏极，以及作为提供电性接触点的栅极金属层的步骤示意图。图2F是侧向半导体功率晶体管晶胞沿着图2A中A-A’截面的剖视图。如同在图2F与图2A中所示，侧向半导体功率器件100是设置在一半导体衬底105上的，其形成有一磊晶层110，磊晶层110内形成有P型井115。或者P型井115也可直接形成于衬底105上，而无须磊晶层110。半导体功率晶体管晶胞更包含有一源极区域120-S与一漏极区域120-D，与一位于栅极氧化层130上的多晶硅栅极125，以控制源极与漏极区域间的信道。半导体功率晶体管晶胞被一绝缘层135覆盖，绝缘层135形成有接触开口140-S与140-D，其填满源极与漏极接触金属150-S与150-D。一金属硅化物层142将接触点延伸至源极与漏极区域，且使源极与漏极区域分别离开相应的接触开口，以减少源极/漏极的硅电阻。此半导体功率晶体管晶胞更包含有一位于金属150-S与150-D上的第二金属层160，其利用一绝缘层152，使得第二金属层160和金属150-S以及150-D分隔开。这第二金属层160更包含有一作为源极衬垫的160-S部分，与一作为漏极衬垫的160-D部分(图中未示)。源极衬垫160-S穿过内部金属连接中介窗155-S，并连接至源极金属150-S。漏极衬垫160-D穿过内部金属连接中介窗155-D，并连接至漏极金属150-D(图中未示)。
请参阅图2B，在器件设置好栅极125，源极区域120-S与漏极区域120-D各自的位置后，随后一金属硅化物层142(见图2F)也被形成。根据制成步骤，随后沉积一钝化层。随后，进行接触点开口的蚀刻。数个源极与漏极接触点的开口140-S与140-D被形成，以与源极区域120-S与漏极区域120-D连接。再者，栅极接触点开口140-G形成于栅极衬垫125-pad上，以连接至该栅极衬垫125-pad。请参阅图2C，沉积第一金属层并填满源极接处点开口140-S、漏极接触点开口140-D与栅极接触点开口140-G。第一金属层进一步被图案化为数个源极金属150-S、漏极金属150-D与栅极金属150-G，以将每一电极分隔开。请参阅图2D，形成一覆盖第一图案化金属层150-S与150-D的第二绝缘层。随后，数个内部金属连接中介窗155-S与155-D被形成且穿透该第二绝缘层，以连接至金属条150-S与150-D的下方。在图2D中所呈现的具体实施例，覆盖于每一源极金属条150-S上方的内部金属连接中介窗155-S是位于器件的上方部分，而覆盖于每一漏极金属条150-D上方的内部金属连接中介窗155-D是位于器件的下方部分。在另一具体实施例中(图中未示)，覆盖于每一源极金属条150-S上方的内部金属连接中介窗155-S是位于器件的下方部分，而覆盖于每一漏极金属条150-D上方的内部金属连接中介窗155-D是位于器件的上方部分。在图2E中，沉积一第二金属层以填入内部金属连接中介窗155-S与155-D中。此第二金属层更被图案化为一第二源极金属160-S、一第二漏极金属160-D与一第二栅极金属160-G。所有的金属条150-S通过数个内部金属连接中介窗155-S连接至源极金属160-S，所有的金属条150-D通过数个内部金属连接中介窗155-D连接至漏极金属160-D。因此源极金属160-S与漏极金属160-D提供了源极衬垫与漏极衬垫作为打线接合或其它联机工具。
在图2D与图2F所示的具体实施例中，器件较低部分的源极区域连接至金属条150-S的较低部分，并且通过该金属条150-S到达内部金属连接中介窗155-S。由于位于器件上方部分的源极区域是直接穿过金属条150-S的上方部分即可连接至内部金属连接中介窗155-S的，相比较之下，位于器件下方部分的源极区域将承受较高的电阻。这对位于器件上方部分的漏极区域是相同的。这样就增加了整体的电阻。
请参阅图3，其是本发明的另一具体实施例，其中第一金属层被图案化为数个具有不同宽度以连接至源极或漏极接触点的M1条。金属条150-S的下方部分较上方部分宽，以降低下方部分的源极电阻。金属条150-S的上方部分是较窄的，以形成空间提供金属条150-D在上方部分宽度的延伸，因此减少上方部分的漏极电阻，因此如图3中的具体实例所示，可以减少器件整体的电阻。
依据图2A至图2E与图3，侧向MOSFET晶胞的多晶硅栅极区域分为源极与漏极区域，并且多晶硅栅极被架构为波状图案。多晶硅栅极的波状图案是依循一最小化多晶硅间隔法来架构的，其是目前的制程技术可达到的。因为多晶硅条刻画为最小间隔，无须源极与漏极接触点介于多晶硅波状图案间，因此可获得较高的信道密度，其转换为较高的W/单位面积，其中W是指所有总通道宽度的总和。
现在，在流入位于波状图案末端的接触点前，介于源极与漏极区域间的信道电流是由介于多晶硅栅极区域的硅源极与漏极区域汇集而来。这将意味着器件具有较高电阻，原因是附加了源极/漏极硅电阻。然而，在先进的次微米技术中，相较于无金属硅化物的制程，由于金属硅化物的形成，漏极与源极硅电阻减少大约电阻的十分之一。因此，源极/漏极电阻不会影响开关的电阻。
更者，多晶硅波状图案栅极是间歇地连接形成一网格，以减少多晶硅栅极电阻。另外，这个新布局结构可无须让步金属电阻即可增加信道密度。这既有利于单一金属制程，其宽的M1条可用来减少金属电阻，也有利于双金属制程，其较宽的M2条总线可因为较低M1条电阻而获得。如同图2A所示，多晶硅波状图案化栅极的布局特性是连接为一网格，以减少多晶硅栅极的电阻。
虽然本发明利用上数个各种具体实施例进行说明，但并不能以这样的描述来作为对本发明的局限。对熟悉该项技术者而言，在阅读过上述的描述后，各种改变与修饰将被认为是显而易见的。举例来说，利用其它传导性材料来取代多晶硅。这个技术可应用于双N/P型态的MOSFET与LDD MOSFET。据此，申请专利范围所能涵盖所有修改与修饰皆是本发明的精神与范围。

Claims (23)

1.一种半导体功率器件，其位于一半导体衬底上，特征在于，该半导体功率器件包含：
数个晶体管晶胞，每一个晶体管晶胞具有一源极与一漏极区域，位于该半导体衬底上的栅极区域的两侧，其中栅极电极被形成为一位于栅极区域顶部的栅极电极层，以控制该源极与漏极区域间的电流传输；以及
所述的位于半导体衬底顶部的栅极电极层被图案化为波状的长条，以实质上增加介于该源极与漏极区域间越过栅极的电流传导面积。
2.如权利要求1所述的半导体功率器件，其特征在于，所述的栅极电极层更包含一多晶硅层，位于所述的半导体衬底顶部并且被图案化为数个波状的多晶硅长条。
3.如权利要求1所述的半导体功率器件，其特征在于，所述的栅极电极层更包含栅极流道，其连接至已图案化为波状长条的栅极电极层，以构成栅极电极网格，以减少栅极电阻。
4.如权利要求3所述的半导体功率器件，其特征在于，所述的栅极流道更连接至一栅极衬垫，该栅极衬垫设置于半导体衬底的四周。
5.如权利要求1所述的半导体功率器件，其特征在于，根据制程与设计的最小间距法则，所述的栅极电极层被图案化为在两邻近的波状长条间具有最小的距离。
6.如权利要求1所述的半导体功率器件，其特征在于，更包含有：
一第一绝缘层，其覆盖该半导体器件并且具有数个贯穿第一绝缘层的接触点开口槽，该接触点开口槽填满源极金属接触点与漏极金属接触点，以供各自与该源极与本体区域进行接触。
7.如权利要求6所述的半导体功率器件，其特征在于，更包含有：
一第一金属层，其被图案化为数个金属条，其包含数个与源极金属接触点接触的源极金属条和数个与漏极金属接触点接触的漏极金属条。
8.如权利要求7所述的半导体功率器件，其特征在于，更包含有：
一第二绝缘层，其覆盖所述的金属条，其中该第二绝缘层具有数个穿透其本身的源极中介窗接触点与漏极中介窗接触点，以各自连接至源极金属条以及漏极金属条。
9.如权利要求8所述的半导体功率器件，其特征在于，更包含有：
一第二金属层，其位于第二绝缘层顶部，并且被图案化为一源极金属和一漏极金属，以各自连接至源极中介窗接触点与漏极中介窗接触点。
10.如权利要求9所述的半导体功率器件，其特征在于，更包含有：所述的源极金属与所述的漏极金属设置于半导体功率器件顶部的两相对侧。
11.如权利要求4所述的半导体功率器件，其特征在于，更包含有：一栅极金属，其与栅极衬垫接触，以作为一外部的栅极电极。
12.如权利要求9所述的半导体功率器件，其特征在于，所述的第一金属层被图案化为数个具有不同宽度的源极与漏极金属条，其中该源极金属条的下方部分比该源极金属条的上方部分宽，以减少该下方部分的源极电阻，并且该源极金属条的上方部分具有一较窄的宽度，以供漏极金属条的上方部分具有较大的宽度，以减少在上方部分的漏极电阻。
13.一种架构位于半导体衬底上的半导体功率器件的方法，其特征在于，包含以下步骤：
形成数个晶体管晶胞，每一晶体管晶胞具有一源极与一漏极区域，位于半导体衬底上的栅极区域的两侧；以及
在栅极区域顶部形成一栅极电极层，以控制传输于源极与漏极区域间的电流，并且图案化所述的栅极电极层成波状的长条，以本质上增加介于源极与漏极区域间越过该栅极的电流传导面积。
14.如权利要求13所述的方法，其特征在于，所述的形成栅极电极层的步骤更包含有：在该栅极区域顶部设置一多晶硅层，并图案化该多晶硅层为数个波状长条的步骤。
15.如权利要求13所述的方法，其特征在于，所述的形成栅极电极层的步骤更包含有：将栅极流道连接至已图案化为波状长条的栅极电极层的步骤，以构成栅极电极网格，减少栅极电阻。
16.如权利要求15所述的方法，其特征在于，更包含有：将所述的栅极流道连接至一位于半导体衬底四周的栅极衬垫。
17.如权利要求13所述的方法，其特征在于，所述的形成该栅极电极层的步骤更包含有：根据制程与设计的最小间距法则，图案化该栅极电极层使得其邻近的波状长条间具有最小距离的步骤。
18.如权利要求1所述的方法，其特征在于，更包含有以下步骤：
沉积一覆盖所述半导体器件的第一绝缘层，并设置数个贯穿该第一绝缘层的接触点开口槽，随后将源极金属接触点与漏极金属接触点填入所述的接触开口槽内，以各自与该源极与本体区域接触。
19.如权利要求18所述的方法，其特征在于，更包含有以下步骤：
在所述的第一绝缘层顶部沉积一第一金属层，并且图案化该第一金属层成为数个金属条，其中具有数个源极金属条与所述的源极金属接触点接触，以及数个漏极金属条与所述的漏极金属接触点接触。
20.如权利要求19所述的方法，其特征在于，更包含有以下步骤：
沉积一覆盖所述金属条的第二绝缘层，且在该第二绝缘层上开设数个开孔，填满该些开孔以形成数个穿透第二绝缘层的源极中介窗接触点与漏极中介窗接触点，以各自与该源极金属条以及漏极金属条相接触。
21.如权利要求20所述的方法，其特征在于，更包含有以下步骤：
在所述第二绝缘层顶部沉积一第二金属层，并且图案化该第二金属层为一源极金属和一漏极金属，以各自与所述的源极中介窗接触点以及漏极中介窗接触点相连接接触。
22.如权利要求21所述的方法，其特征在于，更包含有：图案化所述源极金属和漏极金属于该第二绝缘层顶部的两相对侧的步骤。
23.如权利要求16所述的方法，其特征在于，更包含有：形成一栅极金属，以与所述栅极衬垫接触，作为一外部栅极电极的步骤。
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