CN101506895B - 可扩缩的存储器系统 - Google Patents

可扩缩的存储器系统 Download PDF

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Publication number
CN101506895B
CN101506895B CN2007800313409A CN200780031340A CN101506895B CN 101506895 B CN101506895 B CN 101506895B CN 2007800313409 A CN2007800313409 A CN 2007800313409A CN 200780031340 A CN200780031340 A CN 200780031340A CN 101506895 B CN101506895 B CN 101506895B
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CN
China
Prior art keywords
memory
command
memory device
data
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007800313409A
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English (en)
Chinese (zh)
Other versions
CN101506895A (zh
Inventor
金镇祺
吴学俊
潘弘柏
S·普日贝尔斯基
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Examine Vincent Zhi Cai Management Co
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/840,692 external-priority patent/US7904639B2/en
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of CN101506895A publication Critical patent/CN101506895A/zh
Application granted granted Critical
Publication of CN101506895B publication Critical patent/CN101506895B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
CN2007800313409A 2006-08-22 2007-08-22 可扩缩的存储器系统 Expired - Fee Related CN101506895B (zh)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US83932906P 2006-08-22 2006-08-22
US60/839,329 2006-08-22
US86877306P 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US90200307P 2007-02-16 2007-02-16
US60/902,003 2007-02-16
US89270507P 2007-03-02 2007-03-02
US60/892,705 2007-03-02
US11/840,692 US7904639B2 (en) 2006-08-22 2007-08-17 Modular command structure for memory and memory system
US11/840,692 2007-08-17
PCT/CA2007/001469 WO2008022454A1 (en) 2006-08-22 2007-08-22 Scalable memory system

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN2012101119432A Division CN102760476A (zh) 2006-08-22 2007-08-22 可扩缩的存储器系统

Publications (2)

Publication Number Publication Date
CN101506895A CN101506895A (zh) 2009-08-12
CN101506895B true CN101506895B (zh) 2012-06-27

Family

ID=39106444

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2012101119432A Pending CN102760476A (zh) 2006-08-22 2007-08-22 可扩缩的存储器系统
CN2007800313409A Expired - Fee Related CN101506895B (zh) 2006-08-22 2007-08-22 可扩缩的存储器系统

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2012101119432A Pending CN102760476A (zh) 2006-08-22 2007-08-22 可扩缩的存储器系统

Country Status (7)

Country Link
EP (1) EP2062261A4 (enrdf_load_stackoverflow)
JP (2) JP5575474B2 (enrdf_load_stackoverflow)
KR (2) KR101476515B1 (enrdf_load_stackoverflow)
CN (2) CN102760476A (enrdf_load_stackoverflow)
CA (1) CA2659828A1 (enrdf_load_stackoverflow)
TW (1) TWI437577B (enrdf_load_stackoverflow)
WO (1) WO2008022454A1 (enrdf_load_stackoverflow)

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US7865756B2 (en) 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
US8467486B2 (en) 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US8781053B2 (en) 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
KR20110081958A (ko) * 2008-09-30 2011-07-15 모사이드 테크놀로지스 인코퍼레이티드 출력 지연 조정을 가진 직렬 연결 메모리 시스템
US7957173B2 (en) * 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
WO2010069045A1 (en) * 2008-12-18 2010-06-24 Mosaid Technologies Incorporated Error detection method and a system including one or more memory devices
US20110002169A1 (en) 2009-07-06 2011-01-06 Yan Li Bad Column Management with Bit Information in Non-Volatile Memory Systems
US20110258366A1 (en) * 2010-04-19 2011-10-20 Mosaid Technologies Incorporated Status indication in a system having a plurality of memory devices
US9009423B2 (en) * 2010-04-26 2015-04-14 Novachips Canada Inc. Serially connected memory having subdivided data interface
US9239806B2 (en) * 2011-03-11 2016-01-19 Micron Technology, Inc. Systems, devices, memory controllers, and methods for controlling memory
US8856482B2 (en) * 2011-03-11 2014-10-07 Micron Technology, Inc. Systems, devices, memory controllers, and methods for memory initialization
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
CN102508797B (zh) * 2011-10-27 2015-02-11 忆正存储技术（武汉）有限公司 闪存控制扩展模块、控制器、存储系统及其数据传输方法
TWI581267B (zh) * 2011-11-02 2017-05-01 諾瓦晶片加拿大公司 快閃記憶體模組及記憶體子系統
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
US8966151B2 (en) * 2012-03-30 2015-02-24 Spansion Llc Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
US9760149B2 (en) 2013-01-08 2017-09-12 Qualcomm Incorporated Enhanced dynamic memory management with intelligent current/power consumption minimization
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US9792227B2 (en) * 2014-08-19 2017-10-17 Samsung Electronics Co., Ltd. Heterogeneous unified memory
JP6453718B2 (ja) * 2015-06-12 2019-01-16 東芝メモリ株式会社 半導体記憶装置及びメモリシステム
KR102296740B1 (ko) * 2015-09-16 2021-09-01 삼성전자 주식회사 메모리 장치 및 그것을 포함하는 메모리 시스템
FR3041806B1 (fr) * 2015-09-25 2017-10-20 Stmicroelectronics Rousset Dispositif de memoire non volatile, par exemple du type eeprom, ayant une capacite memoire importante, par exemple 16mbits
KR102457820B1 (ko) * 2016-03-02 2022-10-24 한국전자통신연구원 메모리 인터페이스 장치
KR102532528B1 (ko) * 2016-04-07 2023-05-17 에스케이하이닉스 주식회사 메모리 장치 및 이의 동작 방법
KR102731614B1 (ko) * 2016-08-26 2024-11-21 삼성전자주식회사 시리얼 통신으로 메모리를 제공하기 위한 장치 및 방법
KR102669694B1 (ko) * 2016-09-28 2024-05-28 삼성전자주식회사 서로 직렬로 연결된 스토리지 장치들 중 애플리케이션 프로세서에 직접 연결되지 않는 스토리지 장치를 리셋시키는 전자 기기 및 그것의 동작 방법
KR102514717B1 (ko) * 2016-10-24 2023-03-27 삼성전자주식회사 메모리 컨트롤러 및 이를 포함하는 메모리 시스템
KR102336666B1 (ko) * 2017-09-15 2021-12-07 삼성전자 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
KR20190112546A (ko) * 2018-03-26 2019-10-07 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
US10372330B1 (en) 2018-06-28 2019-08-06 Micron Technology, Inc. Apparatuses and methods for configurable memory array bank architectures
US11043488B2 (en) * 2019-01-24 2021-06-22 Western Digital Technologies, Inc. High voltage protection for high-speed data interface
KR102708771B1 (ko) 2020-05-25 2024-09-20 삼성전자주식회사 디스플레이 구동 장치 및 디스플레이 구동 장치를 포함하는 디스플레이 장치
CN118251724A (zh) * 2021-11-19 2024-06-25 株式会社索思未来 存储器电路
KR20230085629A (ko) 2021-12-07 2023-06-14 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법

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Also Published As

Publication number Publication date
JP2012226786A (ja) 2012-11-15
TW200828338A (en) 2008-07-01
KR20090045366A (ko) 2009-05-07
WO2008022454A1 (en) 2008-02-28
CA2659828A1 (en) 2008-02-28
EP2062261A4 (en) 2010-01-06
JP5575474B2 (ja) 2014-08-20
CN102760476A (zh) 2012-10-31
KR101476515B1 (ko) 2014-12-24
KR20120110157A (ko) 2012-10-09
TWI437577B (zh) 2014-05-11
CN101506895A (zh) 2009-08-12
JP2010501916A (ja) 2010-01-21
KR101476463B1 (ko) 2014-12-24
EP2062261A1 (en) 2009-05-27

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Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Free format text: FORMER NAME: MOSAID TECHNOLOGIES INC.

CP01 Change in the name or title of a patent holder

Address after: Ontario, Canada

Patentee after: Examine Vincent Zhi Cai management company

Address before: Ontario, Canada

Patentee before: Mosaid Technologies Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120627

Termination date: 20160822