CN101500367A - Signal processing circuit and method - Google Patents
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- CN101500367A CN101500367A CNA2008100047708A CN200810004770A CN101500367A CN 101500367 A CN101500367 A CN 101500367A CN A2008100047708 A CNA2008100047708 A CN A2008100047708A CN 200810004770 A CN200810004770 A CN 200810004770A CN 101500367 A CN101500367 A CN 101500367A
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Abstract
The invention relates to a signal processing circuit and a method thereof; the method includes the following steps: when a synchronous frequency of a first synchronous signal is beyond the range of the frequency, a second synchronous signal with a selective frequency is generated, wherein the selective frequency is within the range of the frequency; and when the synchronous frequency is within the range of the frequency, in the preset rising edge time of a next preset pulse of the first synchronous signal, the rising edge of a first pulse which corresponds to the next preset pulse in the first synchronous signal is generated; additionally, when the synchronous frequency is within the range of the frequency, according to whether the next preset pulse occurs a detecting result or not before a first time and after the preset rising edge time, the lowering edge of the first pulse is generated. The signal processing circuit and the method thereof can eliminate the image flicker of liquid crystal displays.
Description
Technical field
This case is about a kind of signal processing circuit and method, particularly about a kind of circuit and method that is used for suppressing the water ripple phenomenon of cold cathode fluorescent lamp pipe.
Background technology
Generally when utilizing the cold cathode fluorescent lamp pipe to arrange in pairs or groups the panel of LCD (LCD), because the cold cathode fluorescent lamp pipe can cause the fluctuation of the accurate position of ground connection (GND) in the moment of lighting, if run into synchronizing signal when synchronous again, can cause the current potential instability of LCD, so be easy to generate the phenomenon of ripples line.
Synchronizing signal is that a kind of control signal also is a kind of triggering signal, it may be a pulse wave signal, also may be a kind of sine wave or irregular pulse wave signal, as long as the device of institute's desire control can be reached the unanimity of frequency and phase place, the device of being controlled can be changed by predetermined sequential, and this kind control signal is synchronizing signal.
In the known technology, the method of avoiding this water ripple phenomenon is that the synchronizing signal of the some modulation frequency of cold cathode fluorescent lamp pipe and LCD is synchronous, though and such processing mode has solved the problem of ripples lines by the illusion that causes vision, the another one of but having derived problem; Promptly when inter-process, the synchronizing signal of part LCD control integrated circuit can postpone a pulse.Shown in Fig. 1 (a), it is for the synchronous signal that is used to drive cold cathode fluorescent lamp pipe drive integrated circult of liquid crystal display television; The display frequency of liquid crystal display television figure field (Field) is 60Hz (or 50Hz), and the some modulation frequency of cold cathode fluorescent lamp pipe is 48.5KHz, wherein puts modulation frequency by synchronizing signal V
SYNFrequency control; Because it is the pulse of 48.5KHz that the pairing one-period of frequency 60Hz (or 50Hz) can't just in time hold an integer frequency, therefore, the synchronizing signal that part LCD control integrated circuit is produced can postpone a pulse.
See also Fig. 1 (b), it is the waveform schematic diagram of the tube current of the synchronizing signal cold cathode fluorescent lamp pipe pairing with it of having used LCD.As shown in the figure, as synchronizing signal V
SYNCPulse when omission being arranged because of delay, this omission pulse the some modulating signal of corresponding cold cathode fluorescent lamp pipe also disappear, cause tube voltage to descend and current I
CCFLReduce, and then cause the situation of film flicker.
As how effectively solving because of film flicker phenomenon that pulse caused of sync signal delay, be the mainspring of development this case with easy circuit.
Therefore, this case inventor is in view of the above-mentioned disappearance of having used technology, and this case " signal processing circuit and method " is created in the research through concentrating one's attention on, and a spirit of working with perseverance eventually.
Summary of the invention
One purpose of this case is for proposing a kind of signal processing circuit and method, utilize one first synchronizing signal that is received to produce one second synchronizing signal that drives a cold cathode fluorescent lamp pipe, wherein second synchronizing signal is supplied the pulse that first synchronizing signal is lacked, to eliminate the film flicker phenomenon of LCD.
First of this case is contemplated that and proposes a kind of signal processing method, when it comprises the following steps: that a synchronizing frequency when one first synchronizing signal is outside a frequency range, generation has one second synchronizing signal of a selection frequency, wherein selects frequency within frequency range; When synchronizing frequency is within frequency range,, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse in the predetermined rising edge time of next predetermined pulse of first synchronizing signal; And when synchronizing frequency was within this frequency range, the detecting result according to whether this next predetermined pulse occurs after the time and before a very first time at predetermined rising edge produced the falling edge of first pulse.
Second of this case is contemplated that and proposes a kind of signal processing circuit that it comprises external trigger interruption generator, a timer, a programmable pulse generator and a control unit.Whether external trigger is interrupted the edge of a pulse that generator is detected its one first synchronizing signal that receives, occur to judge first synchronizing signal.The programmable pulse generator produces one second synchronizing signal according to the pre-adjusted value that removes that it had.Control unit is coupled in external trigger and interrupts generator, timer and programmable pulse generator, wherein control unit utilizes external trigger to interrupt the predetermined rising edge time that generator and timer arrive next predetermined pulse of any first synchronizing signal, and control programmable pulse generator produces in second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse.
Another of this case is contemplated that and proposes a kind of signal processing method, comprise the following steps:
In the predetermined rising edge time of next predetermined pulse of one first synchronizing signal, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse; And
According to the detecting result that whether this next predetermined pulse occurs after the time and before a very first time at this predetermined rising edge, produce the falling edge of this first pulse, wherein when a synchronizing frequency of this first synchronizing signal is outside a frequency range, generation has one and selects this second synchronizing signal of frequency, and should select frequency within this frequency range.
Signal processing circuit of the present invention and method can be eliminated the film flicker phenomenon of LCD.
This case must be by following graphic detailed description, with more deep understanding:
Description of drawings
Fig. 1 (a): with the synchronous signal that is used to drive cold cathode fluorescent lamp pipe drive integrated circult of liquid crystal display television;
Fig. 1 (b): the waveform schematic diagram of tube current of having used the synchronizing signal cold cathode fluorescent lamp pipe pairing of LCD with it;
Fig. 2: the block schematic diagram of the application system of this case first signal processing circuit that embodiment carries;
Fig. 3 (a): this case first embodiment carries the waveform schematic diagram that next predetermined pulse occurs in the signal processing circuit;
Fig. 3 (b): this case first embodiment carries next predetermined pulse in the signal processing circuit does not have the waveform schematic diagram that occurs;
Fig. 4: the block schematic diagram of the application system of this case second signal processing circuit that embodiment carries; And
Fig. 5: the schematic flow diagram of this case second signal processing method that embodiment carries.
Embodiment
See also Fig. 2, it is the block schematic diagram of the application system of this case first signal processing circuit that embodiment puies forward.As shown in the figure, the application system 30 of signal processing circuit comprises a control integrated circuit 31, a signal processing circuit 32, a cold cathode fluorescent lamp pipe 331, and the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 of a LCD.
The synchronizing signal V that control integrated circuit 31 is produced
S1In order to the control LCD picture show synchronously, and as an advance signal of control cold cathode fluorescent lamp pipe 331.Signal processing circuit 32 receives synchronizing signal V
S1And adjustment synchronizing signal V
S1, to produce synchronizing signal V
S2The drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 receives synchronizing signal V
S2, light the tube voltage signal V of cold cathode fluorescent lamp pipe 331 with generation
CCFL, synchronizing signal V wherein
S2Frequency as some modulation frequencies of cold cathode fluorescent lamp pipe 331.In addition, synchronizing signal V
S2The one drive integrated circult (not shown) that also can offer a back light source in LED is used.
Signal processing circuit 32 comprises external trigger interruption generator 322, a timer 323, a programmable pulse generator 324 and a control unit 321.Signal processing circuit 32 can be, for example, and a microcontroller (MCU) or a special purpose integrated circuit (ASIC).External trigger is interrupted generator 322 and is received synchronizing signal V
S1And detecting synchronizing signal V
S1The edge, with the triggering that produces disruptive and offer control unit 321, synchronizing signal V wherein
S1Have series of pulses, and design external trigger interruption generator 322 makes it can detect synchronizing signal V
S1Rising edge or falling edge, or one of them of rising edge and falling edge.
External trigger is interrupted the synchronizing signal V that generator 322 is received
S1Comprise series of pulses, and synchronizing signal V
S1Next predetermined pulse do not know whether really can occur.But no matter synchronizing signal V
S1Next predetermined pulse whether occur, signal processing circuit 32 all will be guaranteed the synchronizing signal V that produces
S2In can occur corresponding to one first pulse of next predetermined pulse.
See also Fig. 3 (a) and Fig. 3 (b), Fig. 3 (a) carries the waveform schematic diagram that next predetermined pulse occurs in the signal processing circuit for this case first embodiment, and Fig. 3 (b) carries the waveform schematic diagram that next predetermined pulse in the signal processing circuit does not have appearance for this case first embodiment.Control unit 321 utilizes external trigger to interrupt generator 322 and timer 323 statistics synchronizing signal V
S1The cycle of one group of preceding pulse before next predetermined pulse NPS1 is to obtain synchronizing signal V
S1A typical pulse width, a synchronizing cycle and a synchronizing frequency, wherein synchronizing frequency is the inverse of synchronizing cycle, and the predetermined rising edge time T 1 of next predetermined pulse NPS1 is synchronizing signal V
S2One of rising edge time of final pulse and the summation of synchronizing cycle, or be this sum total near.And the predetermined rising edge time T 1 of next predetermined pulse NPS1 also can be by synchronizing signal V
S1One of rising edge time of final pulse or falling edge time, typical pulse width and synchronizing cycle calculate and get.
Whether control unit 321 utilizes external trigger to interrupt generator 322 and timer 323 and detects next predetermined pulse NPS1 occur after predetermined rising edge time T 1 and before a very first time T2, and the detecting result who whether occurs according to next predetermined pulse NPS1, utilize programmable pulse generator 324 to produce the falling edge of the first pulse TPS1, wherein very first time T2 adds for 1/2nd synchronizing cycle for predetermined rising edge time T 1, or very first time T2 adds the multiplying power of 1/2nd synchronizing cycle for predetermined rising edge time T 1, and usually this multiplying power near 1.
As synchronizing signal V
S1When the falling edge of next predetermined pulse NPS1 before very first time T2, occurring, control unit 321 the falling edge of next predetermined pulse NPS1 after the time at once or a Preset Time afterwards, utilize programmable pulse generator 324 to produce synchronizing signal V
S2In the falling edge of the first pulse TPS1.As synchronizing signal V
S1When the falling edge of next predetermined pulse NPS1 not occurring before very first time T2, control unit 321 can be after very first time T2 at once or a Preset Time afterwards, produces synchronizing signal V
S2In the falling edge of the first pulse TPS1.And control unit 321 removes the falling edge time that adjusted value is controlled the first pulse TPS1 by adjusting the pre-of programmable pulse generator 324, to adjust the width of the first pulse TPS1.
See also Fig. 4, it is the block schematic diagram of the application system of this case second signal processing circuit that embodiment puies forward.The application system 40 of Fig. 4 is the expansion of Fig. 2 application system 30.As shown in Figure 4, the application system 40 of signal processing circuit comprises a control integrated circuit 31, a signal processing circuit 42, a cold cathode fluorescent lamp pipe 331, and the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 of a LCD.
The circuit that application drawing 4 then is described is to carry out method for processing signals.See also Fig. 5, it is for the schematic flow diagram of this case second signal processing method that embodiment carries.In step 502, control unit 321 obtains synchronizing signal V
S1Synchronizing frequency, and check that arbitrary synchronizing frequency is whether in a frequency range (for example outside the 40kHz～50kHz).
In step 504, the synchronizing signal V that is obtained when control unit 321
S1Synchronizing frequency outside frequency range the time, expression synchronizing signal V
S1Synchronizing frequency be abnormal.So control unit 321 control programmable prescaler 325 make programmable prescaler 325 produce the triggering signal V with a selection frequency
S3, wherein select frequency in frequency range (for example between the 40kHz～50kHz), and triggering signal V
S3Comprise series of pulses and offer programmable pulse generator 324, and the duty ratio of this series of pulses is 50% usually.Programmable pulse generator 324 is according to triggering signal V
S3Generation has the synchronizing signal V that selects frequency
S2, and provide it to the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331, wherein control unit 321 is by the pre-adjusted value that removes of setting programmable pulse generator 324, with control synchronizing signal V
S2The width of pulse, and synchronizing signal V
S2Pulse can have 50% duty ratio, or have adjustable pulse duration.
In step 506, the synchronizing signal V that is obtained when control unit 321
S1Synchronizing frequency within frequency range the time, control unit 321 utilizes timer 323 and programmable pulse generator 324, makes programmable pulse generator 324 at synchronizing signal V
S1The predetermined rising edge time T 1 of next predetermined pulse NPS1 produce synchronizing signal V
S2The rising edge of the first pulse TPS1, wherein the first pulse TPS1 is corresponding to next predetermined pulse NPS1.
In step 508, whether control unit 321 utilizes the falling edge that external trigger is interrupted generator 322 and timer 323 next predetermined pulse NPS1 of detecting after predetermined rising edge time T 1 and before a very first time T2 to occur, wherein very first time T2 adds for 1/2nd synchronizing cycle for predetermined rising edge time T 1, or very first time T2 adds the multiplying power of 1/2nd synchronizing cycle for predetermined rising edge time T 1, and usually this multiplying power near 1.
In step 510, as synchronizing signal V
S1After predetermined rising edge time T 1 and when the falling edge of next predetermined pulse NPS1 before very first time T2, occurring, control unit 321 the falling edge of next predetermined pulse NPS1 after the time at once or a Preset Time afterwards, utilize programmable pulse generator 324 to produce synchronizing signal V
S2In the falling edge of the first pulse TPS1.
In step 512, as synchronizing signal V
S1After predetermined rising edge time T 1 and when the falling edge of next predetermined pulse NPS1 before very first time T2, not occurring, control unit 321 after very first time T2 at once or a Preset Time afterwards, generation synchronizing signal V
S2In the falling edge of the first pulse TPS1.And control unit 321 removes the falling edge time that adjusted value is controlled the first pulse TPS1 by adjusting the pre-of programmable pulse generator 324, to adjust the width of the first pulse TPS1, so, the film flicker phenomenon that pulse produced of omitting but optimization ground is eliminated.
In sum, signal processing circuit of this case and method can reach the effect that the invention conception sets really.Just, the above only is the preferred embodiment of this case, is familiar with the personage of this case skill such as, and the equivalence of being done according to this case spirit in the whence is modified or changed, and all should be covered by in the following claim scope.
Claims (15)
1. a signal processing method comprises the following steps:
When a synchronizing frequency of one first synchronizing signal is outside a frequency range, produce and have one second synchronizing signal of selecting frequency, wherein should select frequency within this frequency range;
When this synchronizing frequency is within this frequency range,, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse in the predetermined rising edge time of next predetermined pulse of this first synchronizing signal; And
When this synchronizing frequency was within this frequency range, according at this predetermined rising edge after the time and before a very first time, the detecting result whether this next predetermined pulse occurs produced the falling edge of this first pulse.
2. signal processing method as claimed in claim 1 more comprises the following steps:
By the cycle of the one group preceding pulse of this first synchronizing signal of statistics before this next predetermined pulse, obtain a synchronizing cycle and this synchronizing cycle inverse this synchronizing frequency, wherein rising edge time of a final pulse that should predetermined rising edge time be this second synchronizing signal and the summation of this synchronizing cycle.
3. signal processing method as claimed in claim 1 more comprises the following steps:
When this synchronizing frequency of this first synchronizing signal is outside this frequency range, adjust the pulse duration of this second synchronizing signal; And
When this synchronizing frequency of this first synchronizing signal is within this frequency range, adjust the pulse duration of this first pulse.
4. signal processing method as claimed in claim 1, wherein:
This very first time wherein should be an inverse of this synchronizing frequency for should the predetermined rising edge time adding for a synchronizing cycle of 1/2nd synchronizing cycle, and should the very first time add the multiplying power of this synchronizing cycle of 1/2nd for being scheduled to the rising edge time; And/or
When the falling edge of this next predetermined pulse appearred in this first synchronizing signal before this very first time, the falling edge time of this first pulse was at the Preset Time of falling edge after the time of this next predetermined pulse.
5. signal processing method as claimed in claim 1, wherein:
When the falling edge of this next predetermined pulse does not appear in this first synchronizing signal before this very first time, the Preset Time of the falling edge time of this first pulse after this very first time; And/or
This first synchronizing signal is provided by a control integrated circuit of a LCD.
6. signal processing method as claimed in claim 1, wherein:
This second synchronizing signal offers a drive integrated circult of a cold cathode fluorescent lamp pipe, and the frequency of this second synchronizing signal is as some modulation frequencies of this cold cathode fluorescent lamp pipe; And/or
This second synchronizing signal offers a drive integrated circult of a back light source in LED.
7. signal processing method as claimed in claim 1, wherein:
This method is performed by a microcontroller;
This microcontroller comprises at least one firmware, an external trigger interruption generator, a programmable pulse generator and a timer, and wherein this firmware is controlled the running that this external trigger is interrupted generator, this programmable pulse generator and this timer;
This firmware utilization receives this first synchronizing signal, and utilizes this external trigger interruption generator and this timer to obtain this synchronizing frequency of this first synchronizing signal;
When this synchronizing frequency of this first synchronizing signal was outside this frequency range, this programmable pulse generator produces had a triggering signal of this selection frequency to produce this second synchronizing signal;
When this synchronizing frequency of this first synchronizing signal was outside this frequency range, this firmware was more set a pre-adjusted value that removes of this programmable pulse generator, with the width of the pulse of controlling this second synchronizing signal;
When this synchronizing frequency was within this frequency range, this firmware utilized this timer and this programmable pulse generator, made this programmable pulse generator produce the rising edge of this first pulse of this second synchronizing signal in this predetermined rising edge time; And
When this synchronizing frequency was within this frequency range, this firmware utilized this detecting result, this timer and this programmable pulse generator, made this programmable pulse generator produce the falling edge of this first pulse of this second synchronizing signal.
8. signal processing method as claimed in claim 1, wherein:
This method is performed by a microcontroller;
This microcontroller comprises at least one firmware, external trigger interruption generator, a programmable prescaler, a programmable pulse generator and a timer, and wherein this firmware is controlled the running that this external trigger is interrupted generator, this programmable prescaler, this programmable pulse generator and this timer;
This firmware utilization receives this first synchronizing signal, and utilizes this external trigger interruption generator and this timer to obtain this synchronizing frequency of this first synchronizing signal;
When this synchronizing frequency of this first synchronizing signal was outside this frequency range, this programmable prescaler produced the triggering signal with this selection frequency, and this programmable pulse generator receives this triggering signal to produce this second synchronizing signal;
When this synchronizing frequency of this first synchronizing signal was outside this frequency range, this firmware was more set a pre-adjusted value that removes of this programmable pulse generator, with the width of the pulse of controlling this second synchronizing signal;
When this synchronizing frequency was within this frequency range, this firmware utilized this timer and this programmable pulse generator, made this programmable pulse generator produce the rising edge of this first pulse of this second synchronizing signal in this predetermined rising edge time; And
When this synchronizing frequency was within this frequency range, this firmware utilized this detecting result, this timer and this programmable pulse generator, made this programmable pulse generator produce the falling edge of this first pulse of this second synchronizing signal.
9. signal processing method as claimed in claim 1, wherein this method is performed by a special purpose integrated circuit.
10. signal processing circuit comprises:
Whether one external trigger is interrupted generator, detects the edge of a pulse of its one first synchronizing signal that receives, occur to judge this first synchronizing signal;
One timer;
One programmable pulse generator, the pre-adjusted value that removes according to it had produces one second synchronizing signal; And
One control unit, be coupled in this external trigger and interrupt generator, this timer and this programmable pulse generator, wherein this control unit utilizes this external trigger to interrupt generator and this timer arrives the predetermined rising edge time of next predetermined pulse of any this first synchronizing signal, and controls this programmable pulse generator and produce in this second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse.
11. signal processing circuit as claim 10, wherein this control unit utilizes this external trigger to interrupt generator and this timer, detect this next predetermined pulse at this predetermined rising edge after time and before a very first time and whether occur, utilize this programmable pulse generator to produce the falling edge of this first pulse according to this.
12. the signal processing circuit as claim 10 more comprises:
One programmable prescaler is coupled in this control unit, and according to the frequency divider value that it had, produces a triggering signal that is supplied to the programmable pulse generator, wherein:
This control unit utilizes this external trigger interruption generator and this timer to obtain a synchronizing frequency of this first synchronizing signal;
When this synchronizing frequency was outside a frequency range, this control unit was controlled this programmable prescaler, made this programmable prescaler generation have this triggering signal of a selection frequency, wherein should select frequency within this frequency range; And
This control unit is controlled this programmable pulse generator and is received this triggering signal, and makes this programmable pulse generator produce this second synchronizing signal with this selection frequency.
13. as the signal processing circuit of claim 10, wherein:
This signal processing circuit is a microcontroller; And/or
This first synchronizing signal is provided by a control integrated circuit of a LCD.
14. as the signal processing circuit of claim 10, wherein:
This second synchronizing signal offers a drive integrated circult of a cold cathode fluorescent lamp pipe, and the frequency of this second synchronizing signal is as some modulation frequencies of this cold cathode fluorescent lamp pipe; And/or
This second synchronizing signal offers a drive integrated circult of a back light source in LED.
15. a signal processing method comprises the following steps:
In the predetermined rising edge time of next predetermined pulse of one first synchronizing signal, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse; And
According to the detecting result that whether this next predetermined pulse occurs after the time and before a very first time at this predetermined rising edge, produce the falling edge of this first pulse, wherein when a synchronizing frequency of this first synchronizing signal is outside a frequency range, generation has one and selects this second synchronizing signal of frequency, and should select frequency within this frequency range.
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| CN200810004770A CN101500367B (en) | 2008-01-30 | 2008-01-30 | Signal processing circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810004770A CN101500367B (en) | 2008-01-30 | 2008-01-30 | Signal processing circuit and method |
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| CN101500367A true CN101500367A (en) | 2009-08-05 |
| CN101500367B CN101500367B (en) | 2012-09-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022133969A1 (en) * | 2020-12-25 | 2022-06-30 | 京东方科技集团股份有限公司 | Signal processing method and device, and display device |
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| US6819011B2 (en) * | 2002-11-14 | 2004-11-16 | Fyre Storm, Inc. | Switching power converter controller with watchdog timer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022133969A1 (en) * | 2020-12-25 | 2022-06-30 | 京东方科技集团股份有限公司 | Signal processing method and device, and display device |
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