CN101500367B - Signal processing circuit and method - Google Patents
Signal processing circuit and method Download PDFInfo
- Publication number
- CN101500367B CN101500367B CN200810004770A CN200810004770A CN101500367B CN 101500367 B CN101500367 B CN 101500367B CN 200810004770 A CN200810004770 A CN 200810004770A CN 200810004770 A CN200810004770 A CN 200810004770A CN 101500367 B CN101500367 B CN 101500367B
- Authority
- CN
- China
- Prior art keywords
- synchronizing
- frequency
- pulse
- synchronizing signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000012545 processing Methods 0.000 title abstract description 32
- 230000000630 rising effect Effects 0.000 claims abstract description 43
- 238000003672 processing method Methods 0.000 claims description 13
- 230000001360 synchronised effect Effects 0.000 abstract description 11
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 4
- 101000984044 Homo sapiens LIM homeobox transcription factor 1-beta Proteins 0.000 description 19
- 102100025457 LIM homeobox transcription factor 1-beta Human genes 0.000 description 19
- 208000000175 Nail-Patella Syndrome Diseases 0.000 description 19
- 101000795074 Homo sapiens Tryptase alpha/beta-1 Proteins 0.000 description 12
- 101000662819 Physarum polycephalum Terpene synthase 1 Proteins 0.000 description 12
- 102100029639 Tryptase alpha/beta-1 Human genes 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention relates to a signal processing circuit and a method thereof; the method includes the following steps: when a synchronous frequency of a first synchronous signal is beyond the range of the frequency, a second synchronous signal with a selective frequency is generated, wherein the selective frequency is within the range of the frequency; and when the synchronous frequency is within the range of the frequency, in the preset rising edge time of a next preset pulse of the first synchronous signal, the rising edge of a first pulse which corresponds to the next preset pulse in the first synchronous signal is generated; additionally, when the synchronous frequency is within the range of the frequency, according to whether the next preset pulse occurs a detecting result or not before a first time and after the preset rising edge time, the lowering edge of the first pulse is generated. The signal processing circuit and the method thereof can eliminate the image flicker of liquid crystal displays.
Description
Technical field
This case is about a kind of signal processing circuit and method, particularly about a kind of circuit and method that is used for suppressing the water ripple phenomenon of cold cathode fluorescent lamp pipe.
Background technology
Generally when utilizing the cold cathode fluorescent lamp pipe to arrange in pairs or groups the panel of LCD (LCD); Because the cold cathode fluorescent lamp pipe can cause the fluctuation of the accurate position of ground connection (GND) in the moment of lighting; If when running into synchronized again; Can cause the current potential of LCD unstable, so be easy to generate the phenomenon of ripples line.
Synchronizing signal is that a kind of control signal also is a kind of triggering signal; It possibly be a pulse wave signal; Also possibly be a kind of sine wave or irregular pulse wave signal; As long as can the device of institute's desire control be reached the unanimity of frequency and phase place, the device of being controlled can be changed by predetermined sequential, this kind control signal is synchronizing signal.
In the known technology; The method of avoiding this water ripple phenomenon is with the some modulation frequency of cold cathode fluorescent lamp pipe and the synchronized of LCD; Though and such processing mode has solved the problem of ripples lines by the illusion that causes vision, the another one of but having derived problem; Promptly when inter-process, the synchronizing signal of part LCD control integrated circuit can postpone a pulse.Shown in Fig. 1 (a), it is for the synchronous signal that is used to drive cold cathode fluorescent lamp pipe drive integrated circult of liquid crystal display television; The display frequency of liquid crystal display television figure field (Field) is 60Hz (or 50Hz), and the some modulation frequency of cold cathode fluorescent lamp pipe is 48.5KHz, wherein puts modulation frequency by synchronizing signal V
SYNFrequency control; Because it is the pulse of 48.5KHz that the pairing one-period of frequency 60Hz (or 50Hz) can't just in time hold an integer frequency, therefore, the synchronizing signal that part LCD control integrated circuit is produced can postpone a pulse.
See also Fig. 1 (b), it is the waveform sketch map of the tube current of the synchronizing signal cold cathode fluorescent lamp pipe pairing with it of having used LCD.As shown in the figure, as synchronizing signal V
SYNCPulse when omission being arranged because of delay, this omission pulse the some modulating signal of corresponding cold cathode fluorescent lamp pipe also disappear, cause tube voltage to descend and current I
CCFLReduce, and then cause the situation of film flicker.
As how effectively solve because of film flicker phenomenon that pulse caused of sync signal delay with easy circuit, be the mainspring of development this case.
Therefore, this case inventor is in view of the above-mentioned disappearance of having used technology, and this case " signal processing circuit and method " is created in the research that warp is concentrated, and a spirit of working with perseverance eventually.
Summary of the invention
One purpose of this case is for proposing a kind of signal processing circuit and method; Utilize one first synchronizing signal that is received to produce one second synchronizing signal that drives a cold cathode fluorescent lamp pipe; Wherein second synchronizing signal is supplied the pulse that first synchronizing signal is lacked, to eliminate the film flicker phenomenon of LCD.
First of this case is contemplated that and proposes a kind of signal processing method; When it comprises the following steps: that a synchronizing frequency when one first synchronizing signal is outside a frequency range; Generation has one second synchronizing signal of a selection frequency, wherein selects frequency within frequency range; When synchronizing frequency is within frequency range,, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse in the predetermined rising edge time of next predetermined pulse of first synchronizing signal; And when synchronizing frequency was within this frequency range, the detecting result according to whether this next predetermined pulse occurs after the time and before a very first time at predetermined rising edge produced the falling edge of first pulse.
Second of this case is contemplated that and proposes a kind of signal processing circuit that it comprises an external trigger interruption generating device, a timer, a programmable pulse generator and a control unit.Whether the edge of a pulse of external trigger interruption generating device detecting one first synchronizing signal that it received occurs to judge first synchronizing signal.The programmable pulse generator produces one second synchronizing signal according to the preparatory adjusted value that removes that it had.Control unit is coupled in external trigger interruption generating device, timer and programmable pulse generator; Wherein control unit utilizes external trigger interruption generating device and timer to arrive predetermined rising edge time of next predetermined pulse of any first synchronizing signal, and control programmable pulse generator produces in second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse.
Another of this case is contemplated that and proposes a kind of signal processing method, comprise the following steps:
In the predetermined rising edge time of next predetermined pulse of one first synchronizing signal, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse; And
According to the detecting result that whether this next predetermined pulse occurs after the time and before a very first time at this predetermined rising edge; Produce the falling edge of this first pulse; Wherein when a synchronizing frequency of this first synchronizing signal is outside a frequency range; Generation has one and selects this second synchronizing signal of frequency, and should select frequency within this frequency range.
Signal processing circuit of the present invention and method can be eliminated the film flicker phenomenon of LCD.
This case must be by the detailed description of drawings as hereinafter, with more deep understanding:
Description of drawings
Fig. 1 (a): with the synchronous signal that is used to drive cold cathode fluorescent lamp pipe drive integrated circult of liquid crystal display television;
Fig. 1 (b): the waveform sketch map of tube current of having used the synchronizing signal cold cathode fluorescent lamp pipe pairing of LCD with it;
Fig. 2: the block schematic diagram of the application system of this case first signal processing circuit that embodiment carries;
Fig. 3 (a): this case first embodiment carries the waveform sketch map that next predetermined pulse in the signal processing circuit has appearance;
Fig. 3 (b): this case first embodiment carries next predetermined pulse in the signal processing circuit does not have the waveform sketch map that occurs;
Fig. 4: the block schematic diagram of the application system of this case second signal processing circuit that embodiment carries; And
Fig. 5: the schematic flow diagram of this case second signal processing method that embodiment carries.
Embodiment
See also Fig. 2, it is the block schematic diagram of the application system of this case first signal processing circuit that embodiment puies forward.As shown in the figure, the application system 30 of signal processing circuit comprises a control integrated circuit 31, a signal processing circuit 32, a cold cathode fluorescent lamp pipe 331, and the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 of a LCD.
The synchronizing signal V that control integrated circuit 31 is produced
S1In order to the control LCD picture show synchronously, and as an advance signal of control cold cathode fluorescent lamp pipe 331.Signal processing circuit 32 receives synchronizing signal V
S1And adjustment synchronizing signal V
S1, to produce synchronizing signal V
S2The drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 receives synchronizing signal V
S2, light the tube voltage signal V of cold cathode fluorescent lamp pipe 331 with generation
CCFL, synchronizing signal V wherein
S2Frequency as some modulation frequencies of cold cathode fluorescent lamp pipe 331.In addition, synchronizing signal V
S2The one drive integrated circult (not shown) that also can offer a back light source in LED is used.
The synchronizing signal V that external trigger interruption generating device 322 is received
S1Comprise series of pulses, and synchronizing signal V
S1Next predetermined pulse do not know whether really can occur.But no matter synchronizing signal V
S1Next predetermined pulse whether occur, signal processing circuit 32 all will be guaranteed the synchronizing signal V that produces
S2In can occur corresponding to one first pulse of next predetermined pulse.
See also Fig. 3 (a) and Fig. 3 (b); Fig. 3 (a) carries the waveform sketch map that next predetermined pulse in the signal processing circuit has appearance for this case first embodiment, and Fig. 3 (b) carries the waveform sketch map that next predetermined pulse in the signal processing circuit does not have appearance for this case first embodiment.Control unit 321 utilizes external trigger interruption generating device 322 and timer 323 statistics synchronizing signal V
S1The cycle of one group of preceding pulse before next predetermined pulse NPS1 is to obtain synchronizing signal V
S1A typical pulse width, a synchronizing cycle and a synchronizing frequency, wherein synchronizing frequency is the inverse of synchronizing cycle, and the predetermined rising edge time T 1 of next predetermined pulse NPS1 is synchronizing signal V
S2One of a rising edge time and the summation of synchronizing cycle of final pulse, or be this sum total near.And the predetermined rising edge time T 1 of next predetermined pulse NPS1 also can be by synchronizing signal V
S1One of a rising edge time or falling edge time, typical pulse width and the synchronizing cycle of final pulse calculate and get.
Whether control unit 321 utilizes external trigger interruption generating device 322 and timer 323 after predetermined rising edge time T 1 and before the very first time T2, to detect next predetermined pulse NPS1 to occur; And the detecting result who whether occurs according to next predetermined pulse NPS1; Utilize programmable pulse generator 324 to produce the falling edge of the first pulse TPS1; Wherein very first time T2 adds for 1/2nd synchronizing cycle for predetermined rising edge time T 1; Or very first time T2 adds the multiplying power of 1/2nd synchronizing cycle for predetermined rising edge time T 1, and usually this multiplying power near 1.
As synchronizing signal V
S1When the falling edge of next predetermined pulse NPS1 occurring before the very first time T2, control unit 321 the falling edge of next predetermined pulse NPS1 the time after at once or a Preset Time afterwards, utilize programmable pulse generator 324 generation synchronizing signal V
S2In the falling edge of the first pulse TPS1.As synchronizing signal V
S1When the falling edge of next predetermined pulse NPS1 not occurring before the very first time T2, control unit 321 can be very first time T2 after at once or a Preset Time afterwards, generation synchronizing signal V
S2In the falling edge of the first pulse TPS1.And control unit 321 is by the falling edge time of controlling the first pulse TPS1 in advance except that adjusted value of adjustment programmable pulse generator 324, to adjust the width of the first pulse TPS1.
See also Fig. 4, it is the block schematic diagram of the application system of this case second signal processing circuit that embodiment puies forward.The application system 40 of Fig. 4 is the expansion of Fig. 2 application system 30.As shown in Figure 4, the application system 40 of signal processing circuit comprises a control integrated circuit 31, a signal processing circuit 42, a cold cathode fluorescent lamp pipe 331, and the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 of a LCD.
Signal processing circuit 42 comprises an external trigger interruption generating device 322, a timer 323, a programmable pulse generator 324, a programmable prescaler 325 and a control unit 321.Programmable prescaler 325 is coupled in control unit 321, according to the frequency divider value that it had, produces a triggering signal V who is supplied to programmable pulse generator 324
S3, wherein frequency divider value is controlled the triggering signal V that produces
S3Frequency.
The circuit that application drawing 4 then is described is to carry out method for processing signals.See also Fig. 5, it is for the schematic flow diagram of this case second signal processing method that embodiment carries.In step 502, control unit 321 obtains synchronizing signal V
S1Synchronizing frequency, and check that arbitrary synchronizing frequency is whether in a frequency range (for example outside the 40kHz～50kHz).
In step 504, the synchronizing signal V that is obtained when control unit 321
S1Synchronizing frequency outside frequency range the time, expression synchronizing signal V
S1Synchronizing frequency be abnormal.So control unit 321 control programmable prescaler 325 make programmable prescaler 325 produce the triggering signal V with a selection frequency
S3, wherein select frequency in frequency range (for example between the 40kHz～50kHz), and triggering signal V
S3Comprise series of pulses and offer programmable pulse generator 324, and the duty ratio of this series of pulses is 50% usually.Programmable pulse generator 324 is according to triggering signal V
S3Generation has the synchronizing signal V that selects frequency
S2, and it is offered the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331, wherein control unit 321 removes adjusted value in advance by what set programmable pulse generator 324, with control synchronizing signal V
S2The width of pulse, and synchronizing signal V
S2Pulse can have 50% duty ratio, or have adjustable pulse duration.
In step 506, the synchronizing signal V that is obtained when control unit 321
S1Synchronizing frequency within frequency range the time, control unit 321 utilizes timer 323 and programmable pulse generator 324, makes programmable pulse generator 324 at synchronizing signal V
S1The predetermined rising edge time T 1 of next predetermined pulse NPS1 produce synchronizing signal V
S2The rising edge of the first pulse TPS1, wherein the first pulse TPS1 is corresponding to next predetermined pulse NPS1.
In step 508; Whether the falling edge that control unit 321 utilizes external trigger interruption generating device 322 and timer 323 after predetermined rising edge time T 1 and before a very first time T2, to detect next predetermined pulse NPS1 occurs; Wherein very first time T2 adds for 1/2nd synchronizing cycle for predetermined rising edge time T 1; Or very first time T2 adds the multiplying power of 1/2nd synchronizing cycle for predetermined rising edge time T 1, and usually this multiplying power near 1.
In step 510, as synchronizing signal V
S1When after predetermined rising edge time T 1 and before very first time T2, the falling edge of next predetermined pulse NPS1 occurring; Control unit 321 the falling edge of next predetermined pulse NPS1 after the time at once or a Preset Time afterwards, utilize programmable pulse generator 324 to produce synchronizing signal V
S2In the falling edge of the first pulse TPS1.
In step 512, as synchronizing signal V
S1When after predetermined rising edge time T 1 and before very first time T2, the falling edge of next predetermined pulse NPS1 not occurring, control unit 321 after very first time T2 at once or a Preset Time afterwards, generation synchronizing signal V
S2In the falling edge of the first pulse TPS1.And control unit 321 removing in advance the falling edge time that adjusted value is controlled the first pulse TPS1 by adjustment programmable pulse generator 324; To adjust the width of the first pulse TPS1; So, the film flicker phenomenon that pulse produced of omitting but optimization ground is eliminated.
In sum, signal processing circuit of this case and method can reach the effect that the invention conception sets really.Just, the above is merely the preferred embodiment of this case, is familiar with the personage of this case skill such as, and the equivalence of being done according to this case spirit in the whence is modified or changed, and all should be covered by in the following claim scope.
Claims (9)
1. a signal processing method comprises the following steps:
When a synchronizing frequency of one first synchronizing signal is outside a frequency range, produce have one select frequency one second synchronizing signal, wherein should select frequency within this frequency range;
When this synchronizing frequency is within this frequency range,, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse in the predetermined rising edge time of next predetermined pulse of this first synchronizing signal; And
When this synchronizing frequency was within this frequency range, according at this predetermined rising edge after the time and before a very first time, the detecting result whether this next predetermined pulse occurs produced the falling edge of this first pulse.
2. signal processing method as claimed in claim 1 more comprises the following steps:
By the cycle of the one group preceding pulse of this first synchronizing signal of statistics before this next predetermined pulse; Obtain a synchronizing cycle and this synchronizing cycle this synchronizing frequency reciprocal, rising edge time of a final pulse that should the predetermined rising edge time be this second synchronizing signal wherein and the summation of this synchronizing cycle.
3. signal processing method as claimed in claim 1 more comprises the following steps:
When this synchronizing frequency of this first synchronizing signal is outside this frequency range, adjust the pulse duration of this second synchronizing signal; And
When this synchronizing frequency of this first synchronizing signal is within this frequency range, adjust the pulse duration of this first pulse.
4. signal processing method as claimed in claim 1, wherein:
This very first time wherein should be an inverse of this synchronizing frequency for should the predetermined rising edge time adding for a synchronizing cycle of 1/2nd synchronizing cycle, and should the very first time add the multiplying power of this synchronizing cycle of 1/2nd for being scheduled to the rising edge time; And/or
When the falling edge of this next predetermined pulse appearred in this first synchronizing signal before this very first time, the falling edge time of this first pulse was at the Preset Time of falling edge after the time of this next predetermined pulse.
5. signal processing method as claimed in claim 1, wherein:
When the falling edge of this next predetermined pulse does not appear in this first synchronizing signal before this very first time, the Preset Time of the falling edge time of this first pulse after this very first time; And/or
This first synchronizing signal is provided by a control integrated circuit of a LCD.
6. signal processing method as claimed in claim 1, wherein:
This second synchronizing signal offers a drive integrated circult of a cold cathode fluorescent lamp pipe, and the frequency of this second synchronizing signal is as some modulation frequencies of this cold cathode fluorescent lamp pipe; And/or
This second synchronizing signal offers a drive integrated circult of a back light source in LED.
7. signal processing method as claimed in claim 1, wherein:
This method is performed by a microcontroller;
This microcontroller comprises at least one firmware, an external trigger interruption generating device, a programmable pulse generator and a timer, wherein the running of this firmware control this external trigger interruption generating device, this programmable pulse generator and this timer;
This firmware utilization receives this first synchronizing signal, and utilizes this external trigger interruption generating device and this timer to obtain this synchronizing frequency of this first synchronizing signal;
When this synchronizing frequency of this first synchronizing signal is outside this frequency range, this programmable pulse generator produce have this selection frequency a triggering signal to produce this second synchronizing signal;
When this synchronizing frequency of this first synchronizing signal was outside this frequency range, this firmware was more set one of this programmable pulse generator and is removed adjusted value in advance, with the width of the pulse of controlling this second synchronizing signal;
When this synchronizing frequency was within this frequency range, this firmware utilized this timer and this programmable pulse generator, made this programmable pulse generator produce the rising edge of this first pulse of this second synchronizing signal in this predetermined rising edge time; And
When this synchronizing frequency was within this frequency range, this firmware utilization should be detected result, this timer and this programmable pulse generator, made this programmable pulse generator produce the falling edge of this first pulse of this second synchronizing signal.
8. signal processing method as claimed in claim 1, wherein:
This method is performed by a microcontroller;
This microcontroller comprises at least one firmware, an external trigger interruption generating device, a programmable prescaler, a programmable pulse generator and a timer, wherein the running of this this external trigger interruption generating device of firmware control, this programmable prescaler, this programmable pulse generator and this timer;
This firmware utilization receives this first synchronizing signal, and utilizes this external trigger interruption generating device and this timer to obtain this synchronizing frequency of this first synchronizing signal;
When this synchronizing frequency of this first synchronizing signal was outside this frequency range, this programmable prescaler produced the triggering signal with this selections frequency, and this this triggering signal of programmable pulse generator reception is to produce this second synchronizing signal;
When this synchronizing frequency of this first synchronizing signal was outside this frequency range, this firmware was more set one of this programmable pulse generator and is removed adjusted value in advance, with the width of the pulse of controlling this second synchronizing signal;
When this synchronizing frequency was within this frequency range, this firmware utilized this timer and this programmable pulse generator, made this programmable pulse generator produce the rising edge of this first pulse of this second synchronizing signal in this predetermined rising edge time; And
When this synchronizing frequency was within this frequency range, this firmware utilization should be detected result, this timer and this programmable pulse generator, made this programmable pulse generator produce the falling edge of this first pulse of this second synchronizing signal.
9. signal processing method as claimed in claim 1, wherein this method is performed by a special purpose integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810004770A CN101500367B (en) | 2008-01-30 | 2008-01-30 | Signal processing circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810004770A CN101500367B (en) | 2008-01-30 | 2008-01-30 | Signal processing circuit and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101500367A CN101500367A (en) | 2009-08-05 |
| CN101500367B true CN101500367B (en) | 2012-09-05 |
Family
ID=40947177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810004770A Expired - Fee Related CN101500367B (en) | 2008-01-30 | 2008-01-30 | Signal processing circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101500367B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114982250B (en) * | 2020-12-25 | 2023-12-22 | 京东方科技集团股份有限公司 | Signal processing method and device and display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894463B2 (en) * | 2002-11-14 | 2005-05-17 | Fyre Storm, Inc. | Switching power converter controller configured to provide load shedding |
-
2008
- 2008-01-30 CN CN200810004770A patent/CN101500367B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894463B2 (en) * | 2002-11-14 | 2005-05-17 | Fyre Storm, Inc. | Switching power converter controller configured to provide load shedding |
| US6909266B2 (en) * | 2002-11-14 | 2005-06-21 | Fyre Storm, Inc. | Method of regulating an output voltage of a power converter by calculating a current value to be applied to an inductor during a time interval immediately following a voltage sensing time interval and varying a duty cycle of a switch during the time interval following the voltage sensing time interval |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101500367A (en) | 2009-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI475553B (en) | Backlight control module and backlight control method | |
| KR100537534B1 (en) | Sequential burst mode activation circuit | |
| CN106652919A (en) | Image display method and display apparatus | |
| JP2000241796A (en) | Liquid crystal display device and electronic equipment outputting control signal of liquid crystal display device | |
| CN108597464B (en) | Control device and control method for liquid crystal display | |
| WO2015066973A1 (en) | Liquid crystal display device and backlight drive method therefor | |
| WO2006006404A1 (en) | Liquid crystal display and its light source driving method | |
| RU2627641C1 (en) | Display device and method for backlight control | |
| RU2675047C2 (en) | Backlight unit, method for controlling backlight unit and liquid crystal display | |
| EP1871148A1 (en) | Backlight control apparatus and display apparatus | |
| JP2008070592A (en) | Brightness adjusting device and liquid crystal display | |
| JP6128741B2 (en) | Backlight device, control method for backlight device, and display device | |
| CN101500367B (en) | Signal processing circuit and method | |
| CN100498913C (en) | Liquid crystal display and its light source driving method | |
| CN105958972A (en) | Pwm control circuit and pwm signal generation method | |
| KR100910450B1 (en) | Backlight unit synchronized with image signal for liquid crystal display | |
| CN103093727B (en) | Backlight control signal method of adjustment and device | |
| US20070257878A1 (en) | Light source device for video display, and related method | |
| KR101193305B1 (en) | Dimming control device, apparatus for driving led, and dimming control method | |
| CN111540316B (en) | Circuit device for controlling backlight source and operation method thereof | |
| US8174484B2 (en) | Signal processing circuit and method | |
| JP2008065228A (en) | Light emitting device and liquid crystal display device | |
| TW200809724A (en) | Controlling module and method for LED in color sequential LCOS display system | |
| KR101562613B1 (en) | System and Method for generating Pulse Width Modulation signal | |
| JP2007298664A5 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120905 Termination date: 20210130 |