CN101499441A - Flash Memory and manufacturing method thereof - Google Patents
Flash Memory and manufacturing method thereof Download PDFInfo
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- CN101499441A CN101499441A CNA2008100055047A CN200810005504A CN101499441A CN 101499441 A CN101499441 A CN 101499441A CN A2008100055047 A CNA2008100055047 A CN A2008100055047A CN 200810005504 A CN200810005504 A CN 200810005504A CN 101499441 A CN101499441 A CN 101499441A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 98
- 239000010703 silicon Substances 0.000 claims abstract description 98
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 95
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 238000000034 method Methods 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000007667 floating Methods 0.000 claims abstract description 41
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims description 35
- 239000004020 conductor Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 15
- 230000005641 tunneling Effects 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 13
- 230000002262 irrigation Effects 0.000 claims description 13
- 238000003973 irrigation Methods 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 238000003701 mechanical milling Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims 3
- 239000013078 crystal Substances 0.000 abstract description 8
- 230000008878 coupling Effects 0.000 description 12
- 238000010168 coupling process Methods 0.000 description 12
- 238000005859 coupling reaction Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 7
- 239000002210 silicon-based material Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
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Abstract
The invention provides a method for manufacturing a flash memory; firstly, a substrate which is formed with a plurality of isolation structures is provided; as the top parts of the isolation structures are higher than the substrate, a plurality of openings are formed between two adjacent isolation structures; next, a first silicon semiconductor layer and a second silicon semiconductor layer are respectively formed in sequence in the openings so as to fill the openings; later, part of the isolation structures is removed so as to lead the top parts of the isolation structures to be lower than the top part of the second silicon semiconductor layer; then a silicon crystal grain layer is formed on the first silicon semiconductor layer; finally an inter-grid dielectric layer and a control grid are formed in sequence on the substrate, and the silicon crystal grain layer, the first silicon semiconductor layer and the second silicon semiconductor layer are patterned so as to form a floating grid.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, more particularly, relate to a kind of flash memory and manufacture method thereof.
Background technology
Memory component can repeat the characteristic that data such as deposited, read and erased at action because of having, and the advantage that still renews after outage of the data that deposit in, and widely personal computer and electronic equipment adopt.
Typical memory component is the stacking type grid structure, and it makes floating grid (floating gate) and control grid (control gate) with the polysilicon that mixes.Floating grid is in floating state, does not have any circuit and is attached thereto, and floating grid and control gate interpolar are separated by with dielectric layer between grid, are separated by with tunneling dielectric layer between floating grid and substrate; The control grid then is connected with word line.
(gate coupling ratio is that the decision memory component is operated one of critical nature of usefulness GCR) to the grid coupling coefficient.The grid coupling coefficient of memory component is high more, and then required element operation voltage is just low more.The relation that the electric capacity contact area of grid coupling coefficient and floating grid and control gate interpolar is proportionate, that is the electric capacity contact area is big more between the two, the grid coupling coefficient is also high more.
The method that is used for improving the grid coupling coefficient has following several, comprises the height that increases floating grid, is forming the thickness that increases dielectric layer between the degree of depth that is positioned at the irrigation canals and ditches between floating grid and reduction grid between grid before the dielectric layer etc.Yet to increase the height of floating grid, because the degree of depth of the opening that etch process can form is limited, the height that therefore will increase floating grid will have technical difficulty.Be positioned at the degree of depth of the irrigation canals and ditches between floating grid with increase, it must remove partly substrate, might destroy the channel layer that is positioned at the floating grid below, will influence the reliability of element.As for utilizing the thickness that reduces dielectric layer between grid to improve the method for grid coupling coefficient, the thickness of dielectric layer can reduce the isolation capacity of dielectric layer between grid between the reduction grid, may cause the generation of phenomenons such as leakage current and voltage collapse.
Therefore, how can increase the electric capacity contact area of floating grid and control gate interpolar further, improving the grid coupling coefficient, and then the operation usefulness that promotes memory component is for very important and need the problem of solution badly at present.
Summary of the invention
The invention provides a kind of manufacture method of flash memory, utilize to form one deck silicon grain layer,, therefore can improve the grid coupling coefficient of memory to increase the surface area of floating grid.
The invention provides a kind of flash memory, its floating grid comprises silicon grain layer, in order to increase the electric capacity contact area of floating grid and control gate interpolar, therefore can improve the grid coupling coefficient of memory.
The present invention proposes a kind of manufacture method of flash memory, and the substrate that is formed with a plurality of isolation structures at first is provided, and the top of these isolation structures is higher than substrate, and forms a plurality of openings between the adjacent isolation structure.Then in these openings, form first silicon semiconductor layer and second silicon semiconductor layer in regular turn.Remove the some of these isolation structures then, make the top of these isolation structures be lower than the top of second silicon semiconductor layer.Then on first silicon semiconductor layer, form silicon grain layer, again in forming dielectric layer between grid in the substrate.Then in substrate, form the control grid, and patterned silicon crystal grain layer, first silicon semiconductor layer and second silicon semiconductor layer are to form floating grid.
In an embodiment of the present invention, the method for above-mentioned formation first silicon semiconductor layer and second silicon semiconductor layer comprises the following steps.At first form first silicon semiconductor layer and second silicon semiconductor layer in substrate in regular turn, wherein, second silicon semiconductor layer is filled up opening.Remove opening first silicon semiconductor layer and second silicon semiconductor layer in addition then.
In an embodiment of the present invention, the material of above-mentioned first silicon semiconductor layer comprises unadulterated amorphous silicon, unadulterated polysilicon or unadulterated monocrystalline silicon.
In an embodiment of the present invention, the material of above-mentioned second silicon semiconductor layer comprises the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping.
In an embodiment of the present invention, above-mentionedly remove first silicon semiconductor layer beyond the opening and the method for second silicon semiconductor layer comprises chemical mechanical milling method.
In an embodiment of the present invention, the formation method of above-mentioned silicon grain layer comprises Low Pressure Chemical Vapor Deposition.
In an embodiment of the present invention, the formation method of above-mentioned isolation structure comprises the following steps.At first, in substrate, form one deck tunneling dielectric layer and one deck mask layer in regular turn.Then, patterned mask layer and tunneling dielectric layer, and in substrate, form a plurality of irrigation canals and ditches.In substrate, form a layer insulating then and remove irrigation canals and ditches insulating barrier in addition.Then remove mask layer.
In an embodiment of the present invention, be set forth in the substrate after the step that forms one deck tunneling dielectric layer on and before in substrate, forming the step of one deck mask layer, also be included in and form one deck conductor layer in the substrate.
In an embodiment of the present invention, the step of above-mentioned patterned mask layer and tunneling dielectric layer also comprises patterning conductor layer.
In an embodiment of the present invention, the step of above-mentioned patterned silicon crystal grain layer, first silicon semiconductor layer and second silicon semiconductor layer also comprises patterning conductor layer.
In an embodiment of the present invention, the material of above-mentioned conductor layer comprises the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping.
In an embodiment of the present invention, the material of above-mentioned tunneling dielectric layer comprises silica.
In an embodiment of the present invention, the material of aforementioned mask layer comprises silicon nitride.
In an embodiment of the present invention, the material of above-mentioned insulating barrier comprises silica.
In an embodiment of the present invention, the method for above-mentioned formation insulating barrier comprises chemical vapour deposition technique.
In an embodiment of the present invention, the above-mentioned method that removes irrigation canals and ditches insulating barrier in addition comprises chemical mechanical milling method.
In an embodiment of the present invention, the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between above-mentioned grid.
In an embodiment of the present invention, the material of above-mentioned control grid comprises the polysilicon of doping.
The present invention proposes a kind of flash memory, and it is disposed in the substrate, and it comprises dielectric layer and control grid between the isolation structure that is arranged in substrate, floating grid, grid.Wherein, the top of isolation structure is higher than substrate and is lower than the top of floating grid.Floating grid is disposed in the substrate between the isolation structure, and it comprises first silicon semiconductor layer, second silicon semiconductor layer and silicon grain layer.First silicon semiconductor layer is disposed in the substrate, have the concavity structure, and second silicon semiconductor layer is disposed in the concavity structure, and silicon grain layer then is disposed on first silicon semiconductor layer.Dielectric layer is disposed on the floating grid between grid, and the control grid is disposed between grid on the dielectric layer.
In an embodiment of the present invention, the material of above-mentioned first silicon semiconductor layer comprises unadulterated amorphous silicon, unadulterated polysilicon or unadulterated monocrystalline silicon.
In an embodiment of the present invention, the material of above-mentioned second silicon semiconductor layer comprises the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping
In an embodiment of the present invention, above-mentioned floating grid also comprises conductor layer, between the substrate and first silicon semiconductor layer.
In an embodiment of the present invention, the material of above-mentioned conductor layer comprises the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping.
In an embodiment of the present invention, the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between above-mentioned grid.
In an embodiment of the present invention, the material of above-mentioned control grid comprises the polysilicon of doping.
Utilization of the present invention removes the isolation structure of a part, makes the top of floating grid be higher than isolation structure, to increase the hand capacity of floating grid and control gate interpolar.Make floating grid have silicon grain layer again, significantly increasing the surface area of floating grid, and then improve the grid coupling coefficient of memory component.Therefore, can reduce the required operating voltage of element, be applicable to the semiconductor element that integrated level is high.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 E is the manufacturing process generalized section according to a kind of flash memory of one embodiment of the invention.
Main description of reference numerals
100: substrate
102: tunneling dielectric layer
104: conductor layer
106: mask layer
108: irrigation canals and ditches
108a: isolation structure
110: opening
112: the first silicon semiconductor layer
114: the second silicon semiconductor layer
116: silicon grain layer
118: dielectric layer between grid
120: the control grid
122: floating grid
Embodiment
Figure 1A to Fig. 1 E is the manufacturing process generalized section according to a kind of flash memory of one embodiment of the invention.
Please refer to Figure 1A, substrate 100 at first is provided, this substrate 100 for example is a silicon base.Then, in substrate 100, form one deck tunneling dielectric layer 102, one deck conductor layer 104 and one deck mask layer 106 in regular turn.The material of tunneling dielectric layer 102 for example is a silica, and its formation method for example is a thermal oxidation method.Conductor layer 104 for example is the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping, its formation method for example is after utilizing chemical vapour deposition technique to form the unadulterated silicon material layer of one deck, carry out the ion implantation step forming it, or adopt when participating in the cintest that the mode of implanted dopant forms the silicon material layer that mixes with chemical vapour deposition technique.Certainly, conductor layer 104 also can be other conductor materials, and conductor layer 104 can be looked actual needs and omit and do not form.The material of mask layer 106 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Then, please refer to Figure 1B, after mask layer 106 forms, carry out photoetching and etch process to remove partly mask layer 106.Then, be etching mask with the mask layer 106 that keeps, etched conductors layer 104, tunneling dielectric layer 102 and substrate 100 partly are to form irrigation canals and ditches 108 in substrate 100.In substrate 100, form a layer insulating (not illustrating) then, to fill up irrigation canals and ditches 108.The material of insulating barrier for example is a silica, and its formation method for example is aumospheric pressure cvd method (APCVD) or high density plasma CVD method (HDPCVD).Afterwards, remove irrigation canals and ditches 108 insulating barrier in addition, in substrate 100, form a plurality of isolation structure 108a.The method that removes insulating barrier for example is to serve as to grind stop layer with mask layer 106, carries out chemical mechanical milling tech.
Continue it, please refer to Fig. 1 C, remove mask layer 106, until exposing conductor layer 104 surfaces.When removing mask layer 106, opening 110 is formed between the adjacent isolation structure 108a.The method that removes mask layer 106 for example is to carry out a wet etch process.
Subsequently, in substrate 100, form first silicon semiconductor layer 112 and second silicon semiconductor layer 114 in regular turn, to fill up opening 110.The material of first silicon semiconductor layer 112 for example is unadulterated amorphous silicon, unadulterated polysilicon or unadulterated monocrystalline silicon, and its formation method for example is a chemical vapour deposition technique.The material of second silicon semiconductor layer 114 for example is the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping, its formation method for example is after utilizing chemical vapour deposition technique to form the unadulterated silicon material layer of one deck, carry out the ion implantation step forming it, or adopt when participating in the cintest that the mode of implanted dopant forms the silicon material layer that mixes with chemical vapour deposition technique.
Continue it, please refer to Fig. 1 D, remove opening 110 first silicon semiconductor layer 112 and second silicon semiconductor layer 114 in addition.The method that removes for example is to serve as to grind stop layer with isolation structure 108a, carries out chemical mechanical milling tech.
Then, remove partly isolation structure 108a, make its top be lower than the top of second silicon semiconductor layer 114.The method that removes part isolation structure 108a comprises carries out etch process, for example wet etch process or dry etch process.Wet etch process for example is to be etchant with hydrofluoric acid.
Then, on first silicon semiconductor layer 112, form silicon grain layer 116.The formation method of silicon grain layer 116 for example is a Low Pressure Chemical Vapor Deposition.What deserves to be mentioned is that because silicon crystal grain has the characteristic of selective growth on unadulterated silicon materials, so silicon grain layer 116 is formed on first silicon semiconductor layer 112.
Then, in forming dielectric layer 118 between one deck grid in the substrate 100.The material of dielectric layer 118 for example is a silicon oxide/silicon nitride/silicon oxide between grid.The formation method of dielectric layer 118 for example is earlier to form silicon oxide layer at the bottom of one deck with thermal oxidation method between these grid, then, utilizes chemical vapour deposition technique to form one deck silicon nitride layer again, forms the top silicon oxide layer thereafter again on silicon nitride layer.Afterwards, in substrate 100, form control grid 120.The method that forms control grid 120 for example is to form one deck conductor layer (not illustrating), this conductor layer of patterning then earlier in substrate 100.The material of conductor layer for example is the polysilicon of metal, doping or multi-crystal silicification metal etc., and its formation method is looked the difference of material and adopted methods such as physical vaporous deposition (evaporation, sputter) or chemical vapour deposition technique.
Continue it, patterned silicon crystal grain layer 116, first silicon semiconductor layer 112, second silicon semiconductor layer 114 and conductor layer 104 are to form floating grid 122.In another embodiment, if do not form conductor layer 104, then 122 of floating grids are made of patterned silicon grain layer 116, first silicon semiconductor layer 112 and second silicon semiconductor layer 114.The follow-up technology of finishing memory is known by those skilled in the art, does not repeat them here.
In sum, utilization of the present invention removes the mode of part isolation structure, exposes the control grid of a part, and the electric capacity contact area between control grid and floating grid is increased.Moreover, the silicon crystal grain that utilization has spherical surface is attached to floating grid, and the surface area of floating grid is increased, and then makes the electric capacity contact area multiplication of control grid and floating grid, therefore can improve the grid coupling coefficient of memory, and then reduce required element operation voltage.Therefore, the present invention can promote the operation usefulness of memory and be applicable to the semiconductor element that integrated level is high.
Though the present invention discloses as above with preferred embodiment; but it is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can carry out some and change and retouching, thus protection scope of the present invention when with appended claim the person of being defined be as the criterion.
Claims (25)
1. the manufacture method of a flash memory comprises:
Substrate is provided, has been formed with a plurality of isolation structures in this substrate, the top of described isolation structure is higher than this substrate, and forms a plurality of openings between the adjacent described isolation structure;
In described opening, form first silicon semiconductor layer and second silicon semiconductor layer in regular turn;
Remove the some of described isolation structure, make the top of described isolation structure be lower than the top of this second silicon semiconductor layer;
On this first silicon semiconductor layer, form silicon grain layer;
In forming dielectric layer between grid in this substrate; And
In this substrate, form the control grid, and this silicon grain layer of patterning, this first silicon semiconductor layer and this second silicon semiconductor layer are to form floating grid.
2. the manufacture method of flash memory according to claim 1, the method that wherein forms first silicon semiconductor layer and second silicon semiconductor layer in described opening in regular turn comprises:
In this substrate, form this first silicon semiconductor layer;
Form this second silicon semiconductor layer in this substrate, this second silicon semiconductor layer is filled up described opening; And
Remove described opening this first silicon semiconductor layer and this second silicon semiconductor layer in addition.
3. the manufacture method of flash memory according to claim 2, wherein the material of this first silicon semiconductor layer comprises unadulterated amorphous silicon, unadulterated polysilicon or unadulterated monocrystalline silicon.
4. the manufacture method of flash memory according to claim 2, wherein the material of this second silicon semiconductor layer comprises the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping.
5. the manufacture method of flash memory according to claim 2 wherein removes this first silicon semiconductor layer beyond the described opening and the method for this second silicon semiconductor layer and comprises chemical mechanical milling method.
6. the manufacture method of flash memory according to claim 1, wherein the formation method of this silicon grain layer comprises Low Pressure Chemical Vapor Deposition.
7. the manufacture method of flash memory according to claim 1, the formation method of wherein said isolation structure comprises:
In this substrate, form tunneling dielectric layer and mask layer in regular turn;
This mask layer of patterning and this tunneling dielectric layer, and in this substrate, form a plurality of irrigation canals and ditches;
Form insulating barrier in this substrate, this insulating barrier fills up described irrigation canals and ditches;
Remove described irrigation canals and ditches this insulating barrier in addition; And
Remove this mask layer.
8. the manufacture method of flash memory according to claim 7 wherein in after the step that forms tunneling dielectric layer in this substrate and form the step of mask layer in this substrate before, also is included in this substrate and forms conductor layer.
9. the manufacture method of flash memory according to claim 8, wherein the step of this mask layer of patterning and this tunneling dielectric layer also comprises this conductor layer of patterning.
10. the manufacture method of flash memory according to claim 8, wherein the step of this silicon grain layer of patterning, this first silicon semiconductor layer and this second silicon semiconductor layer also comprises this conductor layer of patterning.
11. the manufacture method of flash memory according to claim 8, wherein the material of this conductor layer comprises the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping.
12. the manufacture method of flash memory according to claim 7, wherein the material of this tunneling dielectric layer comprises silica.
13. the manufacture method of flash memory according to claim 7, wherein the material of this mask layer comprises silicon nitride.
14. the manufacture method of flash memory according to claim 7, wherein the material of this insulating barrier comprises silica.
15. the manufacture method of flash memory according to claim 7, the method that wherein forms this insulating barrier comprises chemical vapour deposition technique.
16. the manufacture method of flash memory according to claim 7, the method that wherein removes described irrigation canals and ditches this insulating barrier in addition comprises chemical mechanical milling method.
17. the manufacture method of flash memory according to claim 1, wherein the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between these grid.
18. the manufacture method of flash memory according to claim 1, wherein the material of this control grid comprises the polysilicon of doping.
19. a flash memory is disposed in the substrate, comprising:
A plurality of isolation structures are disposed in this substrate, and the top of described isolation structure is higher than this substrate;
Floating grid is disposed in this substrate between the described isolation structure, and the top of this floating grid is higher than described isolation structure, and this floating grid comprises:
First silicon semiconductor layer is disposed in this substrate, has the concavity structure;
Second silicon semiconductor layer is disposed in this concavity structure; And
Silicon grain layer is disposed on this first silicon semiconductor layer;
Dielectric layer between grid is disposed on this floating grid; And
The control grid is disposed between these grid on the dielectric layer.
20. flash memory according to claim 19, wherein the material of this first silicon semiconductor layer comprises unadulterated amorphous silicon, unadulterated polysilicon or unadulterated monocrystalline silicon.
21. flash memory according to claim 19, wherein the material of this second silicon semiconductor layer comprises the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping.
22. flash memory according to claim 19, wherein this floating grid also comprises conductor layer, between this substrate and this first silicon semiconductor layer.
23. flash memory according to claim 22, wherein the material of this conductor layer comprises the polysilicon of doped amorphous silicon, doping or the monocrystalline silicon of doping.
24. flash memory according to claim 19, wherein the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between these grid.
25. flash memory according to claim 19, wherein the material of this control grid comprises the polysilicon of doping.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100055047A CN101499441A (en) | 2008-02-03 | 2008-02-03 | Flash Memory and manufacturing method thereof |
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| CNA2008100055047A CN101499441A (en) | 2008-02-03 | 2008-02-03 | Flash Memory and manufacturing method thereof |
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| CN101499441A true CN101499441A (en) | 2009-08-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658979A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and forming method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658979A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and forming method thereof |
| CN104658979B (en) * | 2013-11-19 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and forming method thereof |
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Open date: 20090805 |