CN101499244B - Impulse driving method and circuit of LCD - Google Patents
Impulse driving method and circuit of LCD Download PDFInfo
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- CN101499244B CN101499244B CN2008100049760A CN200810004976A CN101499244B CN 101499244 B CN101499244 B CN 101499244B CN 2008100049760 A CN2008100049760 A CN 2008100049760A CN 200810004976 A CN200810004976 A CN 200810004976A CN 101499244 B CN101499244 B CN 101499244B
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Abstract
A pulse driving method of a liquid crystal display is used for driving an array of pixel of a liquid crystal display panel and includes the step of providing a group of pulse control signals for a source driver. The source driver is used for driving the array of pixel according to the pulse control signals. The pulse control signals include a command signal which comprises a data voltage polarity determination field and a command field; wherein, the data voltage polarity determination field provides a polarity datum of voltage polarity to determine the output of the source driver according to a time sequence; the command field and the data polarity determination field are continuously and alternately output, wherein, the command field is allowed to join in a dynamic instruction needing action.
Description
Technical field
The present invention relates to a kind of Driving technique of LCD, and particularly relate to the technology of a kind of source drive and gate driving.
Background technology
LCD (LCD) for example is thin film transistor (TFT) (Thing film transistor, TFT) LCD, existing very general application.Because the image of LCD is that the pel array that is made of a plurality of pixel shows, each pixel shows the color of a correspondence according to the sequential of frame.In order to reach the demonstration that drives pixel, it needs the various control signal, generally is to do with gate drivers and source electrode driver to intersect control.
Traditional Thin Film Transistor-LCD (TFT LCD) is to adopt to keep kenel (hold-type) to come display image, and it is when writing pixel voltage at every turn, keeps a frame period, but this kind display mode may produce the fuzzy defective of dynamic image.Therefore conventional art proposes pulsed (impulse-type) Driving technique, can effectively overcome above-mentioned shortcoming.
Fig. 1 shows the panel system structural representation of traditional TFT LCD.Consult Fig. 1, TFT LCD has a display panel 100, constitutes a pel array with a plurality of pixels 102 on the display panel 100.In order to drive these pixels 102, it generally is the pixel gray level data that show by source electrode driver 106 input desires.Gate drivers 104 is used for the sequential start scanning linear, so that pixel display pixel luma data.Gate drivers 104 is to be controlled by time schedule controller (timing controller) 108 with source electrode driver 106.
Fig. 2 shows the sequential control of conventional ADS driving method.Consult Fig. 1 and Fig. 2, general operation includes the interface that data transmittal and routing form is RSDS (Reduced Swing Differential Signaling) or mini-LVDS (Low-Voltage Differential Signaling).Time schedule controller 108 is for example sent one group of control signal 110 of timing control signals such as STH/TP/RVS and pixel data respectively to source electrode driver 106, and wherein, the use of STH is at the RSDS transmission form.In addition, time schedule controller 108 is also sent timing control signal such as STV/CPV/OE 112 to gate drivers 104, in order to controlling the required voltage of all pixel capacitances on the TFT LCD panel 100 in proper order, and panel 100 is different thereby present different gray scale variation according to added voltage.As shown in the figure, its pixel drive data input sequence is p
n(x, y), p
n(x+1, y), p
n(x+2, y) ... p
n(x, y+1), p
n(x+1, y+1), p
n(x+2, y+1) ... p
N+1(x, y), p
N+1(x+1, y), p
N+1(x+2, y) ... p
N+1(x, y+1), p
N+1(x+1, y+1), p
N+1(x+2, y+1) ..., promptly be to follow single direction to import in regular turn.Realize the concrete practice of this kind scan mode, be to transmit the horizontal direction synchronizing signal in regular turn and gate driver 104 transmits the vertical direction synchronizing signal in regular turn by source electrode driver 106, therefore, horizontal-drive signal is to adopt one-level one-level serial connection to form at source electrode driver 106 and vertical synchronizing signal at gate drivers 104.
Wherein, STH is the horizontal-drive signal of RSDS data kenel source electrode driver.For mini-LVDS data kenel, be to be contained in the data in the horizontal-drive signal of source electrode driver 106 then.TP is the voltage output control signal of source electrode driver 106, and RVS is the polarity of voltage specification signal of source electrode driver 106.STV is the vertical synchronizing signal of gate drivers 104.CPV is the clock signal of gate drivers 104.OE is the output enable control signal.As shown in Figure 1, OE connects all gate drivers 104, thereby the output enable of all gate drivers is all consistent.
Yet in response to different driving mechanisms, above-mentioned mode is not unique feasible mode.The dealer still continues to seek other more resilient type of drive, with can be in response to other different operation mechanism.
Summary of the invention
The present invention proposes the circuit structure of a kind of pulsed drive method and source electrode driver and clock generator.In addition, the present invention also proposes new system interface agreement, not needing essence to improve under the prerequisite of system transmissions data volume, can reach the pulsed drive purpose, for example can realize the hardware configuration of low cost and low power consumption.
The invention provides a kind of pulse drive method of LCD, in order to drive a pel array of a display panels.The method comprises provides set of pulses control signal to the one source pole driver.Source electrode driver is according to this group pulse control signal, in order to drive this pel array.This group pulse control signal comprises a command signal.Command signal comprises a data voltage polarity determination field and an instruction field, and data voltage polarity determination field provides a polarity data of a polarity of voltage of this source electrode driver output of decision according to a sequential.Instruction field, with the alternately output continuously of this data voltage polarity determination field, wherein, this instruction field allows to add a dynamic instruction that needs action.
According to an embodiment, in aforesaid driving method, a time point of data voltage polarity determination field is to voltage output control signal that should source electrode driver.Again for example, instruction field is between adjacent two these data voltage polarity determination field.
According to an embodiment, in aforesaid driving method, data voltage polarity determination field is not independently signal input.
According to an embodiment, in aforesaid driving method, command signal also comprises voltage output control field, with the Controlling Source driver to export a view data.
According to an embodiment, in aforesaid driving method, instruction field is in order to the display brightness of a plurality of pixels of difference of adjusting this pel array.
According to an embodiment, comprise also in aforesaid driving method providing other output enable signal of branch that wherein, this output enable signal has the alternately output of one first output enable and one second output enable to dividing other gate drivers; And providing a vertical synchronizing signal to this gate drivers, this vertical synchronizing signal comprises one first vertical synchronizing signal and one second vertical synchronizing signal in a frame, to should first output enable and the sequential of this second output enable.
According to an embodiment, in aforesaid driving method, first output enable enables when being the transmission image content, and this second output enable enables when being setting voltage value.
The present invention provides a kind of pulse driving circuit of LCD again, in order to drive a pel array of a display panels.This circuit comprises time schedule controller and one source pole driver.Time schedule controller provides one group of control signal, comprises a clock signal, the voltage output control signal (TP) of one source pole driver, and a command signal.Wherein, command signal comprises a data voltage polarity determination field, and a polarity data of a polarity of voltage of this source electrode driver output of decision is provided according to a sequential; And an instruction field, with the alternately output continuously of this data voltage polarity determination field section, wherein, this instruction field allows to add a dynamic instruction that needs action.Source electrode driver receives this group control signal, comprises this command signal is untied, to carry out respective operations.
According to an embodiment, in aforesaid driving circuit, for example time schedule controller comprises that a reception interface unit to receive input data, and will import the data clock that data decoding obtains this group control signal; And an instruction circuit unit, also receive this data clock comprises this command signal with generation this group control signal.Or command signal can be that the basis generation also can by other clock source (as inner or outside clock generating unit).That is to say that it must be that the basis produces by data clock that the present invention is not limited to command signal.Source electrode driver comprises a reception interface unit, gives follow-up use to receive this data clock that this time schedule controller sends; And a command detection device, receive this data clock and this command signal, to produce an instruction enable signal.
According to an embodiment, in aforesaid driving circuit, for example the instruction circuit unit of time schedule controller comprises a command generator, receives this data clock to produce a command content.One control signal generator receives data clock and instruction content, produces with correspondence to comprise that command signal gives source electrode driver.
According to an embodiment, in aforesaid driving circuit, for example this instruction circuit unit of time schedule controller comprise one first clock divider with this data clock divided by one first parameter, obtain one first frequency reducing clock; One command generator receives the first frequency reducing clock, to produce a command content; One control signal generator receives data clock and produces a data voltage polar signal at least with correspondence; And a logical block, receive command content and data voltage polar signal, output instruction signal after combination.
According to an embodiment, in aforesaid driving circuit, for example the command detection device of source electrode driver also comprises a second clock divider, and this data clock that receives is first divided by one second parameter, to obtain one second frequency reducing clock, produce this instruction enable signal.Again, for example first parameter more than or equal to second parameter.
According to an embodiment, in aforesaid driving circuit, for example the instruction circuit unit of time schedule controller comprises one first clock divider, with this data clock divided by one first parameter, obtain one first frequency reducing clock.One command generator receives the first frequency reducing clock, to produce a command content.One phase-modulator is done phase modulation (PM) with this command content again.One control signal generator receives this data clock and produces a data voltage polar signal at least with correspondence.One logical block, the data voltage polar signal of the command content of receiving phase modulator output and the output of control signal generator, this command signal of output after combination.
According to an embodiment, in aforesaid driving circuit, for example this command detection device of source electrode driver also comprises a second clock divider, and this data clock that receives is first divided by one second parameter, to obtain one second frequency reducing clock, produce the instruction enable signal.For example first parameter is more than or equal to this second parameter again.
According to an embodiment, in aforesaid driving circuit, the TP signal of the corresponding source electrode driver of a time point of data voltage polarity determination field for example.
According to an embodiment, in aforesaid driving circuit, for example instruction field is between adjacent two data polarity of voltage determination field.
According to an embodiment, in aforesaid driving circuit, for example data voltage polarity determination field is not independently signal input.
According to an embodiment, in aforesaid driving circuit, for example command signal also comprises voltage output control field, with the Controlling Source driver to export a view data.
According to an embodiment, in aforesaid driving circuit, for example instruction field comprises the display brightness adjustment in order to a plurality of pixels of difference of setting this pel array.
According to an embodiment, in aforesaid driving circuit, for example time schedule controller more provides other output enable signal of branch to dividing other gate drivers, and wherein, the output enable signal has the alternately output of one first output enable and one second output enable; And one vertical synchronizing signal give gate drivers, vertical synchronizing signal comprises one first vertical synchronizing signal and one second vertical synchronizing signal, the sequential of corresponding first output enable and second output enable in a frame.
According to an embodiment, in aforesaid driving circuit, enable when for example first output enable is the transmission image content, second output enable enables when being setting voltage value.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 shows the panel system structural representation of traditional TFT LCD.
Fig. 2 shows the sequential control of conventional ADS driving method.
Fig. 3 shows according to one embodiment of the invention, the signal sequence synoptic diagram of the pulse drive method of LCD.
Fig. 4 shows according to one embodiment of the invention, the pulse driving circuit block schematic diagram of LCD.
Fig. 5 shows according to one embodiment of the invention, the pulse driving circuit block schematic diagram of LCD.
Fig. 6 shows according to one embodiment of the invention, the pulse driving circuit block schematic diagram of LCD.
Fig. 7 shows according to one embodiment of the invention, the panel system structural representation of TFT LCD.
Fig. 8 shows according to one embodiment of the invention, the synoptic diagram of command protocols.
Fig. 9 shows according to one embodiment of the invention, at the gate driving mode synoptic diagram of Fig. 7 structure employing.
Figure 10 shows according to one embodiment of the invention, according to the drive waveforms synoptic diagram that driving mechanism adopted that proposes.
Figure 11 shows according to one embodiment of the invention, according to the another kind of drive waveforms synoptic diagram that driving mechanism adopted that proposes.
Figure 12 shows according to one embodiment of the invention, and the present invention adopts a practical application synoptic diagram of cmd signal mechanism.
The reference numeral explanation
100: display panel
102: pixel
104: gate drivers
106: source electrode driver
108: time schedule controller
110,112: control signal
114: the instruction setting signal
The 116:TP signal
The 118:STH signal
120: the data input
122: reception interface unit
124: command generator
126: source electrode driver
128: transmit interface unit
130: receiving element
132: the command detection device
134,138: clock divider
140: phase-modulator
The 200:RVS district
202: instruction field
204: time schedule controller
206: source electrode driver
208: gate drivers
210: command protocols
210a, 210b, 210c, 210d, 210e: command content
212: clock
214: white space
300: the frame period
300a, 300b: pixel value
302: the pixel setting value.
Embodiment
The present invention proposes the circuit structure of pulsed drive method and source electrode driver and clock generator.In addition, the present invention also proposes new system interface agreement, not needing essence to improve under the prerequisite of system transmissions data volume, can reach the pulsed drive purpose, for example can realize the hardware configuration of low cost and low power consumption.Below for some embodiment, as explanation of the present invention, but the present invention is not restricted to illustrated embodiment.
Fig. 3 shows according to one embodiment of the invention, the signal sequence synoptic diagram of the pulse drive method of LCD.Consult Fig. 3, source electrode driver control method of the present invention comprises removing traditional RVS control signal, and increases an instruction setting signal (CMD) 114 newly, and instruction setting signal 114 definitions are divided into data voltage polarity determination field, for example are RVS districts 200; And instruction field 202.When in the period in RVS district 200, cmd signal 114 is specified the output voltage polarity.When in the period of instruction field 202, cmd signal 114 is as instruction setting effect.Other control signal for example can be prolonged the method that RSDS or mini-LVDS control are arranged with tradition.Therefore TP signal 116 is learnt the polarity of voltage that is determined by RVS district 200 in the period in RVS district 200.In addition for example signal STH 118 under the use of RSDS, the initiating terminal of corresponding instruction field 202, the action of log-on data input 120, it for example is that the data with a sweep trace line# are that a frame is imported.
Fig. 4 shows according to one embodiment of the invention, the pulse driving circuit block schematic diagram of LCD.Consult Fig. 4, present embodiment is more described at the time schedule controller 204 and the structure of source electrode driver 206.Time schedule controller 204 generally can provide multiple signal to source electrode driver with gate driver.The one of the multiple circuit design of doing in this mechanism of only describing the control signal that cooperates Fig. 3.For time schedule controller 204, for example increase a command generator (command generator) 124, and time schedule controller 204 can output one instruction (CMD) signal.In addition, also cooperating in the source electrode driver 206 increases a command detection device (command detector) 132, in order to when instruction check device 132 obtains an effective instruction, sends corresponding instruction enable signal (command enable) immediately.
Thin portion, time schedule controller 204 comprises a reception interface unit (LVDS/RX) 122, receive input data and will import data decoding obtain a data clock (data clock, CLKA).One instruction circuit unit for example comprises command generator 124 and control signal generator 126, also receives the data clock by reception interface unit output, comprises that with generation one group of control signal of cmd signal is given source electrode driver 206.Again for example, by the data clock of reception interface unit 122 outputs, can send it receiving element 130 of source electrode driver 206 to, to obtain desired data clock, for follow-up use by a transmission interface unit 128.Again, following for the command generator 124 of a plurality of embodiment be for example directly with the data clock of reception interface unit 122 outputs as the basis, yet the input of command generator 124 also can be produced for the basis by other clock source (as inner or outside clock generating unit).That is to say that it must be that the basis produces by data clock that the present invention is not limited to command signal.
Fig. 5 shows according to one embodiment of the invention, the pulse driving circuit block schematic diagram of LCD.Consult Fig. 5, present embodiment also is to describe with regard to time schedule controller 204 and another project organization of source electrode driver 206 earlier, and wherein, the circuit box operation that also can cooperate other again is to promote degree of stability, and still basic design mechanism is still identical with the design of Fig. 4.
At this embodiment, for example may cause the command reception mistake owing to the frequency of data transfer clock CLKA and CLKB is too high for avoiding, in time schedule controller 204, for example can increase by a frequency eliminator again, for example being n clock divider 134 doubly, promptly is CLKA/n, to reduce the instruction transmission frequency.Relatively for example also increasing another frequency eliminator at source electrode driver 206, for example is m clock divider 138 doubly, promptly is CLKB/m, is used as the clock of command detection device 132, and wherein, for example n 〉=m can make source electrode driver 206 with higher frequency sample command content.As in the instruction circuit unit of time schedule controller 204, for example the cmd signal of command generator 124 outputs is done with the RVS that is produced by control signal generator 126 or the computing of logic, in the field of correspondence with output cmd signal or RVS signal.Certainly, or logical operation also can replace by other reciprocity circuit.
Fig. 6 shows according to one embodiment of the invention, the pulse driving circuit block schematic diagram of LCD.Consult Fig. 6, present embodiment also is to describe with regard to time schedule controller 204 and another project organization of source electrode driver 206 earlier, wherein, circuit compared to Fig. 5, but for example for the adjustment system transmission delay, also can cooperate newly-increased phase-modulator (phase modulator) 140 that can modulation instructions again, receive the correctness of instruction to guarantee source electrode driver.
Fig. 7 shows according to one embodiment of the invention, the panel system structural representation of TFT LCD.Consult Fig. 7, utilize aforesaid time schedule controller 204 and source electrode driver 206, can drive the pixel of display panel 100.Yet, type of drive between gate drivers 208 and the time schedule controller 204 for example also can cooperate modification, wherein, with three gate drivers 208 is example, for example respectively by three output enable OE1, OE2, OE3 by time schedule controller 204 controls.The quantity of gate drivers 208 can be set according to actual needs.That is to say that the interface of time schedule controller and source electrode driver adopts the new instruction type structure that proposes.
Fig. 8 shows according to one embodiment of the invention, the synoptic diagram of command protocols.The clock 212 of the instruction check device 132 of source electrode driver for example can be the clock that RSDS clock, mini-LVDS clock or frequency eliminator are exported.Command protocols 210 for example can comprise two kinds of instructions that transmit setting command (SET command) 210b and download instruction (LOAD command) 210e, continues respectively after leading (preamble) 210a, 210d, or does not need leadingly also can.Continuing is a setting value 210c behind setting command 210b, specifies the respective value of output voltage as download instruction 210e, and its value also can comprise polarity.This command protocols mode can be the instruction of various appropriate formats, need not be defined in illustrated embodiment.Cmd signal of the present invention allows definition to send the different instruction of multiple needs, that is to say and can send dynamic instruction, changes according to actual needs, fixedly specification.
Fig. 9 shows according to one embodiment of the invention, at the gate driving mode synoptic diagram of Fig. 7 structure employing.Vertical synchronizing signal STV of the present invention for example is to insert another vertical sync pulse STV_2 between the frame period of two traditional vertical sync pulse STV_1, and three gate drivers is controlled by output enable signal OE1, OE2, OE3 respectively.Each output enable OE1, OE2, OE3 signal have OEA and OEB two lattice zones, corresponding vertical sync pulse STV_1 and vertical sync pulse STV_2 for each frame period branch.So make when vertical sync pulse STV_1 is passed to gate drivers, to correspond to OEA, enable when for example being correspondence transmission image content.When vertical sync pulse STV_2 is passed to gate drivers, correspond to OEB in addition, enable when for example being corresponding setting voltage value.That is to say that STV_1 corresponds to OEA, STV_2 corresponds to OEB.Each frame period for example also has a white space 214, does not produce effect.
Figure 10 shows according to one embodiment of the invention, according to the drive waveforms synoptic diagram that driving mechanism adopted that proposes.For example output enable signal OEA and OEB be when low level, output enable (or anti-phase also can).TP pulse 116 is for example prolonged and is used traditional approach, with reference to the RVS field 200 of cmd signal 114, makes source electrode driver output scanning line line# (0), line# (1), line# (2) in regular turn ... the data that wait.Again and cooperate the OEA signal as output enable.Yet before data did not remain to TP116 pulse next time as yet, source electrode driver received effective instruction 202, exported setting voltage (setting value) with being about to source electrode driver, and cooperated the OEB signal to do output enable.Because OEA and OEB control different gate drivers respectively, can make transmission image content and setting value write the different position of display respectively.RSDS or mini-LVDS data 120 and horizontal synchronization (STH) signal 118 that is used for RSDS, can as the sequential input.
Figure 11 shows according to one embodiment of the invention, according to the another kind of drive waveforms synoptic diagram that driving mechanism adopted that proposes.Consult Figure 11, the method for itself and Figure 10 is similar, yet traditional TP signal promptly is the voltage output control pulse, be merged in cmd signal 114, so cmd signal 114 also redefines more kinds of instructions, wherein, can for example comprise voltage output control,, and comprise the polarity appointment with replacement TP signal.For example according to aforesaid mechanism,, export in order to the given transmission image content corresponding to a kind of instruction in line# (0,1...) zone.Corresponding to " setting value " interval another kind instruction, export in addition in order to the given settings magnitude of voltage.Yet cmd signal of the present invention can define multiple instruction to satisfy more demands for control.
Figure 12 shows according to one embodiment of the invention, and the present invention adopts a practical application synoptic diagram of cmd signal mechanism.For example the pixel value in each frame period can remain to the pixel value that is updated next time.For example a frame period 300 is an example for 16m, and the brightness of pixel is the pixel value p (x of corresponding real image in the time of 300a
0, y
0), and can be a fixing less pixel setting value 302 in the time of 300b.The big I of pixel setting value 302 is set by the instruction area of cmd signal.The variation of respective pixel value, the brightness variation of demonstration becomes the display format of similar pulse also along with there being brightness to change.Certainly, the present invention allows more kinds of type of drive by the mechanism of cmd signal, and Figure 12 only is an embodiment, rather than unique application.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (24)
1. the pulse drive method of a LCD in order to drive a pel array of a display panels, comprising:
Provide set of pulses control signal to the one source pole driver, this source electrode driver is according to this group pulse control signal, and in order to drive this pel array, wherein, this group pulse control signal comprises a command signal, and this command signal comprises:
One data voltage polarity determination field provides a polarity data of a polarity of voltage of this source electrode driver of decision output according to a sequential; And
One instruction field, with the alternately output of this data voltage polarity determination field, wherein, this instruction field allows to add a dynamic instruction that needs action.
2. the pulse drive method of LCD as claimed in claim 1, wherein, a time point of this data voltage polarity determination field is to voltage output control signal that should source electrode driver.
3. the pulse drive method of LCD as claimed in claim 2, wherein, this instruction field is between adjacent two these data voltage polarity determination field.
4. the pulse drive method of LCD as claimed in claim 1, wherein, this data voltage polarity determination field is dependent signal input.
5. the pulse drive method of LCD as claimed in claim 1, wherein, this command signal also comprises:
One voltage output control field is to control this source electrode driver to export a view data.
6. the pulse drive method of LCD as claimed in claim 1, wherein, this instruction field is in order to the display brightness of a plurality of pixels of difference of adjusting this pel array.
7. the pulse drive method of LCD as claimed in claim 1 also comprises:
Provide other output enable signal of branch to dividing other gate drivers, wherein, this output enable signal has the alternately output of one first output enable and one second output enable; And
Provide a vertical synchronizing signal to this gate drivers, this vertical synchronizing signal comprises one first vertical synchronizing signal and one second vertical synchronizing signal in a frame, to should first output enable and the sequential of this second output enable.
8. the pulse drive method of LCD as claimed in claim 7, wherein, this first output enable enables when being the transmission image content, and this second output enable enables when being setting voltage value.
9. the pulse driving circuit of a LCD in order to drive a pel array of a display panels, comprising:
Time schedule controller provides one group of control signal, comprises a clock signal, the voltage output control signal of one source pole driver, and a command signal, and wherein, this command signal comprises:
One data voltage polarity determination field provides a polarity data of a polarity of voltage of this source electrode driver of decision output according to a sequential; And
One instruction field, with the alternately output of this data voltage polarity determination field, wherein, this instruction field allows to add a dynamic instruction that needs action; And
The one source pole driver receives this group control signal, comprises this command signal is untied, to carry out respective operations.
10. the pulse driving circuit of LCD as claimed in claim 9, wherein, this time schedule controller comprises:
One reception interface unit receives input data, and will import the data clock that data decoding obtains this group control signal; And
One instruction circuit unit also receives this data clock or another clock and comprises this group control signal of this command signal with generation,
Wherein, this source electrode driver comprises:
One reception interface unit is given follow-up use to receive this data clock that this time schedule controller sends; And
One command detection device receives this data clock and this command signal, to produce an instruction enable signal.
11. the pulse driving circuit of LCD as claimed in claim 10, wherein, this instruction circuit unit of this time schedule controller comprises:
One command generator receives this data clock, to produce a command content; And
One control signal generator receives this data clock and this command content, produces with correspondence to comprise that this command signal is to this source electrode driver.
12. the pulse driving circuit of LCD as claimed in claim 10, wherein, this instruction circuit unit of this time schedule controller comprises:
One first clock divider, with this data clock divided by one first parameter, obtain one first frequency reducing clock;
One command generator receives this first frequency reducing clock, to produce a command content;
One control signal generator receives this data clock and produces a data voltage polar signal at least with correspondence; And
One logical block receives this command content and this data voltage polar signal, this command signal of output after combination.
13. the pulse driving circuit of LCD as claimed in claim 12, wherein, this command detection device of this source electrode driver also comprises a second clock divider, this data clock that receives is first divided by one second parameter, to obtain one second frequency reducing clock, produce this instruction enable signal.
14. the pulse driving circuit of LCD as claimed in claim 13, wherein, this first parameter is more than or equal to this second parameter.
15. the pulse driving circuit of LCD as claimed in claim 10, wherein, this instruction circuit unit of this time schedule controller comprises:
One first clock divider, with this data clock divided by one first parameter, obtain one first frequency reducing clock;
One command generator receives this first frequency reducing clock, to produce a command content;
One phase-modulator is done phase modulation (PM) with this command content again;
One control signal generator receives this data clock and produces a data voltage polar signal at least with correspondence; And
One logical block receives this command content of this phase-modulator output and this data voltage polar signal of this control signal generator output, this command signal of output after combination.
16. the pulse driving circuit of LCD as claimed in claim 15, wherein, this command detection device of this source electrode driver also comprises a second clock divider, this data clock that receives is first divided by one second parameter, to obtain one second frequency reducing clock, produce this instruction enable signal.
17. the pulse driving circuit of LCD as claimed in claim 16, wherein, this first parameter is more than or equal to this second parameter.
18. the pulse driving circuit of LCD as claimed in claim 9, wherein, a time point of this data voltage polarity determination field is to this voltage output control signal that should source electrode driver.
19. the pulse driving circuit of LCD as claimed in claim 18, wherein, this instruction field is between adjacent two these data voltage polarity determination field.
20. the pulse driving circuit of LCD as claimed in claim 9, wherein, this data voltage polarity determination field is dependent signal input.
21. the pulse driving circuit of LCD as claimed in claim 9, wherein, this command signal also comprises:
One voltage output control field is to control this source electrode driver to export a view data.
22. the pulse driving circuit of LCD as claimed in claim 9, wherein, this instruction field comprises the display brightness adjustment in order to a plurality of pixels of difference of setting this pel array.
23. the pulse driving circuit of LCD as claimed in claim 9, wherein, this time schedule controller more provides:
Divide other output enable signal to give and divide other gate drivers, wherein, this output enable signal has the alternately output of one first output enable and one second output enable; And
One vertical synchronizing signal is given this gate drivers, and this vertical synchronizing signal comprises one first vertical synchronizing signal and one second vertical synchronizing signal in a frame, to should first output enable and the sequential of this second output enable.
24. the pulse driving circuit of LCD as claimed in claim 23, wherein, this first output enable enables when being the transmission image content, and this second output enable enables when being setting voltage value.
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| CN102930840A (en) * | 2012-08-09 | 2013-02-13 | 京东方科技集团股份有限公司 | Liquid crystal display driving circuit as well as driving method and LCD (Liquid Crystal Display) thereof |
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| CN104125521A (en) * | 2014-07-08 | 2014-10-29 | 苏州乐聚一堂电子科技有限公司 | Intelligent headphone wire with illuminating function |
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| CN101499244A (en) | 2009-08-05 |
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