CN101488743B - Ground bounce effect resisting output circuit - Google Patents

Abstract

The invention discloses an output circuit with the ground-bounce resistance effect, which is characterized in that a PMOS threshold voltage-regulating circuit (105) is used for adjusting the threshold voltages of PMOS output transistors (101), (102) and an NMOS threshold voltage-regulating circuit (106) is used for regulating the threshold voltages of NMOS output transistors (103), (104). When an output of the output circuit is converted from a higher electric level to a lower electric lever, the threshold voltages of the PMOS output transistors (101), (102) are increased, and the threshold voltages of the NMOS output transistors (103), (104) are decreased, thereby the change rate of a pull-down circuit, the ground-bounce effect on a ground wire, the power consumption and the pull-down delay are reduced; and when an output of the output circuit is converted from a lower electric lever to a higher electric lever, the threshold voltages of the PMOS output transistors (101), (102) are decreased, and the threshold voltages of the NMOS output transistors (103), (104) are increased, thereby the change rate of a pull-up circuit, the ground-bounce effect on the ground wire, the power consumption and the pull-up delay are reduced.

Description

A kind of output circuit of ground bounce effect resisting

Technical field

The present invention relates to semiconductor integrated circuit, be specifically related to a kind of output circuit that is used for digital circuit with ground bounce effect resisting.

Background technology

The power line of semiconductor integrated circuit inside and ground wire and nonideal power supply and ground.This is because power-line network and the distribution of earth cord network and the encapsulation of semiconductor integrated circuit of semiconductor integrated circuit, a lot of parasitic electrical quantitys (comprising stray inductance, electric capacity, resistance etc.) have been introduced, the particularly introducing of stray inductance has brought serious problems of Signal Integrity for semiconductor integrated circuit inside.There is uncoupling electric capacity between semiconductor integrated circuit internal electric source and the ground wire, there is package inductance between power supply on the circuit board and the encapsulation shell power supply, there is stray inductance on the sheet between encapsulation shell power supply and the semiconductor integrated circuit internal electric source, there is package inductance between ground wire on the circuit board and the encapsulation shell ground wire, has stray inductance on the sheet between the inner ground wire of encapsulation shell line ground and semiconductor integrated circuit.In general package inductance stray inductance on the sheet, for different packing forms, its package inductance also is differentiated, as for DIP encapsulation (dual in-line package), the package inductance of its single pin is 2-18nH; For PGA encapsulation (contact pin grid array packages), the package inductance of its single pin is 4-6nH; And for the encapsulation of table card, the package inductance of its single pin is 1-12nH.

In the power line of semiconductor integrated circuit and ground wire, there is bigger transient current to change, this transient current produces AC voltage drop through package inductance, will cause the semiconductor integrated circuit internal electric source different with power supply and ground wire voltage on the circuit board with ground wire voltage.This phenomenon is called ground bounce effect, and this effect has been introduced ground bullet noise in power supply and ground wire.Because often producing bigger transient current when work, output circuit (output that comprises imput output circuit) changes, so the ground bounce effect that output circuit was introduced when working is the topmost source that semiconductor integrated circuit ground plays noise.Fig. 1 is the circuit diagram that has comprised the output circuit of stray inductance (mainly being package inductance).Among the figure stray inductance on package inductance and the sheet is combined into a stray inductance, L5 is that stray inductance, the L6 on the power line is the stray inductance on the ground wire; MP1 and MN1 are efferent duct, and in order to drive bigger load, efferent duct generally all has very big breadth length ratio; Predrive circuit is the control circuit of efferent duct.When the output of output circuit changes, there is bigger transient current to flow through stray inductance, will produce ground bounce effect.Being changed to low level with output by high level is example, and this moment, efferent duct MP1 turn-offed, and MN1 opens, and produces electric current I n in the state transformation process:

$\mathrm{In}=\frac{K}{2}{(V_{\mathrm{GS}}-V_T)}^2,$

Here K=u _nC _Ox(W/L), u _nBe electron mobility, Cox is the gate capacitance of unit are, and W/L is the breadth length ratio of NM1, V _GSBe the gate source voltage of NM1, V _TThreshold voltage for NM1.This electric current flows through stray inductance L6, produces ground and plays noise Vn:

$V_n=L_g\frac{{\mathrm{dI}}_n}{\mathrm{dt}}$

If have N output current that this type of state variation takes place simultaneously in the semiconductor integrated circuit, producing ground bullet noise Vn can be expressed as:

$V_n={\mathrm{NL}}_g\frac{{\mathrm{dI}}_n}{\mathrm{dt}}$

Hence one can see that, and ground plays noise Vn and current changing rate Be directly proportional.Because current changing rate can $t=\frac{t_r}{2}$ (t _rBe the rise time) time maximum, play noise Vn, max so can produce at this moment the biglyyest:

$V_{n,\max }{=V}_K+\frac{V_r{t}_r}{2V_{G,\mathrm{MN}1}{\mathrm{NL}}_{6}K}[1-\sqrt{1+\frac{{4V}_{G,\mathrm{MN}1}{\mathrm{NL}}_{6}K}{t_r}}]$

V wherein _K=V _{G, MN1}-V _T, V _{G, MN1}Grid voltage for NM1.

Ground bounce effect has weakened the output circuit performance greatly, and ground wire voltage raises because ground bounce effect makes, power line voltage reduces, and the gate source voltage of efferent duct is reduced, thereby drive current is reduced by square law.Even more serious is when output circuit drives the TTL circuit, owing to the rising of ground wire voltage and the reduction of power line voltage, to make the low level signal of output circuit output and the requirement that high level signal does not reach Transistor-Transistor Logic level, thereby produce logic error.

For overcoming ground bounce effect, can improve output circuit.Fig. 2 is existing a kind of output circuit that has the ground bounce effect resisting ability, and wherein the breadth length ratio of transistor MP2 is less than transistor MP3, and the breadth length ratio of transistor MN2 is less than transistor MN3.The ground bounce effect resisting principle of this circuit is: when output signal by low level when high level is changed, MN2, MN3 turn-off, MP2 opens earlier, open again through MP3 after two inverter delay, because ground plays noise Vn and is directly proportional with current changing rate, MP2 has a little electric current earlier to drawing on the output node after opening, and MP3 opens afterwards has a big electric current again to drawing on the output node, though circuit delay has certain loss, significantly reduced the rate of change of pull-up current; When output signal by high level during to low transition, MP2, MP3 turn-off, MN2 opens earlier, open again through MN3 after two inverter delay, same owing to ground bullet noise Vn is directly proportional with current changing rate, MN2 has a little electric current drop-down to output node earlier after opening, and MN3 opens afterwards has a big electric current drop-down to output node again, has significantly reduced the rate of change of pull-down current.But this circuit still has bigger shortcoming: at first be when output level changes, PMOS output transistor and nmos output transistor will be opened within a certain period of time simultaneously, this not only causes bigger current changing rate, causes bigger ground bullet noise, also will produce bigger power consumption; Secondly because output transistor is divided into two, another conducting again after the first conducting, the decreased performance that this will make output circuit causes bigger delay.

Summary of the invention

The purpose of this invention is to provide a kind of new output circuit with ground bounce effect resisting, this circuit can also reduce the delay and the power consumption of circuit relatively except having stronger anti-ground resilience energy power, especially under the deep submicron process condition, have more performance.

For reaching above purpose, the present invention takes following technical scheme to be achieved:

A kind of output circuit of ground bounce effect resisting, comprise a PMOS transistor that connects node (G) on the predrive circuit, first nmos pass transistor that connects the predrive circuit lower node, the transistorized grid of a PMOS is connected with the transistorized grid of the 2nd PMOS by inverter; The grid of first nmos pass transistor is connected by the grid of inverter with second nmos pass transistor, it is characterized in that, the transistorized tagma of a described PMOS, the transistorized tagma of the 2nd PMOS are connected with the PMOS threshold voltage respectively and adjust circuit; The tagma of the tagma of described first nmos pass transistor, second nmos pass transistor is connected with the NMOS threshold voltage respectively and adjusts circuit, when the upper and lower node of predrive circuit is high level by low transition, the PMOS threshold voltage adjusts circuit (105) and NMOS threshold voltage adjustment circuit (106) increases the transistorized threshold voltage of first, second PMOS, and the threshold voltage of first, second nmos pass transistor reduces; When the upper and lower node of predrive circuit is converted to low level by high level, the PMOS threshold voltage adjusts circuit (105) and NMOS threshold voltage adjustment circuit (106) reduces the transistorized threshold voltage of first, second PMOS, the threshold voltage of first, second nmos pass transistor increases, realize the ground bounce effect resisting of output circuit, and reduce power consumption and delay.

In the such scheme, described PMOS threshold voltage is adjusted circuit and is comprised the 3rd PMOS transistor, and its source electrode connection is adjusted the transistorized source electrode of PMOS; The connection of the 3rd PMOS transistor drain is adjusted the transistorized tagma of PMOS, and is adjusted the transistorized grid of PMOS by the connection of first electric capacity; The transistorized grid of the 3rd PMOS is adjusted the transistorized grid of PMOS by the connection of first inverter.

Described NMOS threshold voltage is adjusted circuit and is comprised the 3rd nmos pass transistor, and its source electrode connects the source electrode that is adjusted nmos pass transistor; The drain electrode of the 3rd nmos pass transistor connects the tagma that is adjusted nmos pass transistor, and connects the grid that is adjusted nmos pass transistor by second electric capacity; The grid of the 3rd nmos pass transistor connects the grid that is adjusted nmos pass transistor by second inverter.

Output circuit of the present invention compared with prior art, its advantage is, adjust circuit and PMOS threshold voltage adjustment circuit owing to used the NMOS threshold voltage, when the level of output node E during by high step-down, the transistorized threshold voltage of a PMOS rises, the threshold voltage of first nmos pass transistor descends; When the level of output node E during by low uprising, the transistorized threshold voltage of a PMOS descends, the threshold voltage of first nmos pass transistor rises.So just improve the anti-ground resilience energy power of output circuit, reduced the level conversion time of output node simultaneously, accelerated the operating rate of output circuit.

Description of drawings

Fig. 1 is the schematic diagram that has comprised the output circuit of stray inductance.

Fig. 2 is existing a kind of output circuit structure figure that has ground bounce effect resisting.

Fig. 3 is the output circuit structure figure of the ground bounce effect resisting that proposes of the present invention.

Fig. 4 is the specific embodiment of Fig. 3, comprising PMOS and NMOS threshold voltage adjust the concrete schematic diagram of circuit.

Embodiment

The present invention is described in further detail below in conjunction with drawings and the specific embodiments.

The output circuit of ground bounce effect resisting proposed by the invention as shown in Figure 3, comprise the PMOS transistor 101 that connects node G on the predrive circuit, the nmos pass transistor 103 that connects predrive circuit lower node F, PMOS transistor 101 is connected with PMOS transistor 102 by two inverters; Nmos pass transistor 103 is connected with nmos pass transistor 104 by two inverters.The tagma of the tagma of PMOS transistor 101, PMOS transistor 102 is connected with the PMOS threshold voltage respectively and adjusts circuit 105; The tagma of the tagma of nmos pass transistor 103, nmos pass transistor 104 is connected with the NMOS threshold voltage respectively and adjusts circuit 106, as the upper and lower node F of predrive circuit, when G is converted to low level by high level, the PMOS threshold voltage is adjusted circuit 105 reduces the threshold voltage of PMOS transistor 101,102, and the NMOS threshold voltage is adjusted circuit 106 increases the threshold voltage of nmos pass transistor 103,104; When the threshold voltage rising of nmos pass transistor, by formula

u _nBe electron mobility, (W/L) _nBreadth length ratio for nmos pass transistor), as can be known, the pull-down current of nmos pass transistor 103,104 in transfer process will descend, and make it very fast and end, and so promptly reduce the current changing rate in the transfer process, reduce the power consumption in the transfer process again.When the PMOS transistor threshold voltage descends, by formula

u _pBe hole mobility, (W/L) _pBe the transistorized breadth length ratio of PMOS), as can be known, the pull-up current I of output node E _PIncrease, this will reduce output circuit on draw late, improve the performance of output circuit.

In like manner, as the upper and lower node F of predrive circuit, when G is high level by low transition, the NMOS threshold voltage is adjusted circuit 106 descends the threshold voltage of nmos pass transistor 103,104, and the PMOS threshold voltage is adjusted circuit 105 rises the threshold voltage of PMOS transistor 101,102.When the threshold voltage rising of PMOS transistor 101,102, the pull-up current of PMOS transistor in transfer process will descend, and make it very fast and end, and so promptly reduce the current changing rate in the transfer process, reduce the power consumption in the transfer process again.When the threshold voltage of nmos pass transistor 103,104 descended, the pull-down current of output node E increased, and this will reduce the drop-down delay of output circuit, improved the performance of output circuit.

The PMOS threshold voltage is adjusted circuit 105 specifically can be referring to Fig. 4 with NMOS threshold voltage adjustment circuit 106.

As shown in Figure 4, be the operation principle (is the same in the operation principle that is adjusted on the PMOS transistor 102) that example illustrates PMOS threshold voltage adjustment circuit 105 to be adjusted PMOS transistor 101:

1. when the level of node G was high level by low transition, PMOS transistor 101 turn-offed, because the voltage at electric capacity 203 two ends can not suddenly change, the voltage of node A is raised to more than the VDD, the transistorized body source voltage of PMOS V _SB(V _B-V _S) greater than 0.According to the bulk effect principle as can be known, the pass of the transistorized threshold voltage of PMOS and its body source voltage is:

$V_{\mathrm{TP}}=V_{\mathrm{TP}0}+\mathrm{\γ}(\sqrt{\left|2{\mathrm{\φ}}_F\right|+V_{\mathrm{SB}}}-\sqrt{\left|2{\mathrm{\φ}}_F\right|})$ (wherein $\mathrm{\γ}=\frac{\sqrt{2q{\mathrm{\ϵ}}_{\mathrm{Si}}{N}_{\mathrm{Sub}}}}{C_{\mathrm{ox}}},$ Be the body threshold value factor; V _SBBe the transistorized body source voltage of PMOS; V _T0Be V _SB=0 o'clock threshold voltage; φ _FFermi potential for the substrate semiconductor material; ε _SiDielectric constant for Si; N _SubBe substrate doping; C _OxGrid oxygen electric capacity for unit are)

Hence one can see that, V _TPGreater than V _TP0, the PMOS threshold voltage increases.Pass through the inverting function of inverter 201 afterwards, the voltage of Node B descends, and transistor 202 is opened, and the level of node A is pulled to VDD, thereby avoids excessive sub-threshold leakage current when PMOS transistor 101 turn-offs.

2. when the level of node G was converted to low level by high level, PMOS transistor 101 was opened, and the voltage of the inverting function Node B of process inverter 201 rises, and transistor 203 turn-offs, and node A suspends.Because the voltage at electric capacity 203 two ends can not suddenly change, the voltage of node A is pulled down to below the VDD, the transistorized body source voltage of PMOS V _SBLess than 0.According to the bulk effect principle as can be known, at this moment, V _TPLess than V _TP0, the PMOS threshold voltage reduces, by formula

$I_p=\frac{K}{2}{(V_{\mathrm{GS}}-V_{\mathrm{TP}})}^2$ (K=u _pC _Ox(W/L) _p, u _pBe hole mobility, (W/L) _pBe the transistorized breadth length ratio of PMOS) as can be known, the pull-up current Ip of PMOS increases.

Adjusting circuit 106 for the NMOS threshold voltage, is that example illustrates its operation principle (is the same in the operation principle that is adjusted on the nmos pass transistor 104) to be adjusted nmos pass transistor 103:

1. when the level of node F was converted to low level by high level, nmos pass transistor 103 turn-offed, because the voltage at electric capacity 303 two ends can not suddenly change, the voltage of node C is pulled down to zero level, the source bulk voltage V of nmos pass transistor _BS(V _S-V _B) greater than 0.According to the bulk effect principle as can be known, the pass of the threshold voltage of nmos pass transistor and its source bulk voltage is:

$V_{\mathrm{TN}}=V_{\mathrm{TN}0}+\mathrm{\γ}(\sqrt{\left|2{\mathrm{\φ}}_F\right|+V_{\mathrm{BS}}}-\sqrt{\left|2{\mathrm{\φ}}_F\right|})$ (V _TN0Be V _SB=0 o'clock threshold voltage)

Hence one can see that, V _TNGreater than V _TN0, the NMOS threshold voltage increases.Pass through the inverting function of inverter 301 afterwards, the voltage of node D rises, and transistor 302 is opened, and C is pulled to zero level with node, thereby avoids excessive sub-threshold leakage current when nmos pass transistor 103 turn-offs.

2. when the level of node F was high level by low transition, nmos pass transistor 103 was opened, and through the inverting function of inverter 301, the voltage of node D rises, and transistor 302 turn-offs, and node C suspends.Because the voltage at electric capacity 303 two ends can not suddenly change, the voltage of node C is pulled to zero level, the source bulk voltage V of nmos pass transistor _BSLess than 0.According to the bulk effect principle as can be known, at this moment, V _TNLess than V _TN0, the NMOS threshold voltage reduces, by formula

$I_n=\frac{K}{2}{(V_{\mathrm{GS}}-V_{\mathrm{TN}})}^2$ (K=u _nC _Ox(W/L) _n, u _nBe electron mobility, (W/L) _nBreadth length ratio for nmos pass transistor) as can be known, the pull-down current I of NMOS _nIncrease.

Embodiment circuit as shown in Figure 4, when output signal Dout by high level during to low transition, connect the upper and lower node G of predrive, the voltage of F turns to high level by low level, this moment, the PMOS transistor 101 turn-offed, after last one tunnel two inverter delay, PMOS transistor 102 turn-offs; Nmos pass transistor 103 is opened simultaneously, and after two inverter delay in next road, nmos pass transistor 104 is opened, and this has reduced the ground bounce effect on the ground wire to a certain extent.By above the PMOS threshold voltage is adjusted analysis that circuit 105 and NMOS threshold voltage adjust circuit 106 as can be known, because the voltage at electric capacity 203,303 two ends can not suddenly change, the threshold voltage of PMOS transistor 101,102 is increased, thereby reduced the rate of change of electric current, further reduce ground bullet noise, reduced power consumption; The threshold voltage of nmos pass transistor 103,104 reduces, thereby has reduced the delay of output circuit.

When output signal Dout by low level when high level is changed, the voltage of node G, F turns to low level by high level, this moment, the PMOS transistor 101 was opened, after last one tunnel two inverter delay, PMOS transistor 102 is opened; Nmos pass transistor 103 turn-offs simultaneously, and after two inverter delay in next road, nmos pass transistor 104 turn-offs, and this has reduced the ground bounce effect on the power line to a certain extent.By above the PMOS threshold voltage is adjusted analysis that circuit 105 and NMOS threshold voltage adjust circuit 106 as can be known, because the voltage at electric capacity 203,303 two ends can not suddenly change, the threshold voltage of nmos pass transistor 103,104 is increased, thereby reduced the rate of change of electric current, further reduce ground bullet noise, reduced power consumption; The threshold voltage of PMOS transistor 101,102 reduces, thereby has reduced the delay of output circuit.

Claims (1)

1. the output circuit of a ground bounce effect resisting, comprise a PMOS transistor (101) that connects node (G) on the predrive circuit, first nmos pass transistor (103) that connects predrive circuit lower node (F), the grid of a PMOS transistor (101) is connected with the grid of the 2nd PMOS transistor (102) by first and second inverters of series connection; The grid of first nmos pass transistor (103) is connected with the grid of second nmos pass transistor (104) by third and fourth inverter of series connection, it is characterized in that the tagma of the tagma of a described PMOS transistor (101), the 2nd PMOS transistor (102) is connected with the PMOS threshold voltage respectively and adjusts circuit (105); The tagma of the tagma of described first nmos pass transistor (103), second nmos pass transistor (104) is connected with the NMOS threshold voltage respectively and adjusts circuit (106); The PMOS threshold voltage adjust circuit (105) and NMOS threshold voltage adjustment circuit (106) on predrive circuit (G), when lower node (F) is high level by low transition, the threshold voltage of first, second PMOS transistor (101), (102) is increased, and the threshold voltage of first, second nmos pass transistor (103), (104) reduces; (G), lower node (F) are when being converted to low level by high level on predrive circuit, the threshold voltage of first, second PMOS transistor (101), (102) is reduced, the threshold voltage of first, second nmos pass transistor (103), (104) increases, thereby realize the ground bounce effect resisting of output circuit, and reduce power consumption and delay;

Described PMOS threshold voltage is adjusted circuit (105) and is comprised the 3rd PMOS transistor (202), and its source electrode connection is adjusted the transistorized source electrode of PMOS; The drain electrode connection of the 3rd PMOS transistor (202) is adjusted the transistorized tagma of PMOS, and is adjusted the transistorized grid of PMOS by first electric capacity (203) connection; The grid of the 3rd PMOS transistor (202) is adjusted the transistorized grid of PMOS by the 5th inverter (201) connection;

Described NMOS threshold voltage is adjusted circuit (106) and is comprised the 3rd nmos pass transistor (302), and its source electrode connects the source electrode that is adjusted nmos pass transistor; The drain electrode of the 3rd nmos pass transistor (302) connects the tagma that is adjusted nmos pass transistor, and connects the grid that is adjusted nmos pass transistor by second electric capacity (303); The grid of the 3rd nmos pass transistor (302) connects the grid that is adjusted nmos pass transistor by hex inverter (301).

Images