CN203086426U - CMOS delay circuit - Google Patents

Abstract

According to the embodiments of the utility model, a CMOS delay circuit is provided. A delay unit is disposed between two random adjacent CMOS inverter, which are serially connected together, therefore a temperature drift of the CMOS delay circuit can be effectively controlled in an ideal range, and the high precision requirement of the temperature drift, which possibly exists in the actual circuit design, can be satisfied.

Description

The CMOS delay circuit

Technical field

Each execution mode of the present utility model relates to electronic circuit, and relates more specifically to a kind of CMOS delay circuit.

Background technology

In electronic circuitry design, often to use the CMOS inverter.As is known to the person skilled in the art, for the CMOS inverter, the lag characteristic of CMOS inverter is subjected to technology, voltage, temperature various effects of operation conditions such as (being PVT).What Fig. 1 showed prior art is composed in series the schematic diagram of delay cell by the CMOS inverter.Shown in the dotted line amplifier section among Fig. 1, conventional CMOS inverter is made up of two metal-oxide-semiconductor field effect transistors usually, and wherein PM1 is the PMOS pipe, and NM1 is the NMOS pipe.The grid source threshold voltage of NMOS pipe be on the occasion of, the grid source threshold voltage of PMOS pipe is a negative value.

The carrier mobility μ of MOSFET can be represented by formula (1):

$\mathrm{\μ}\left(T\right)=\mathrm{\μ}\left(T_0\right)\×{\left[\frac{T_0}{T}\right]}^{3/2}---\left(1\right)$

T wherein ₀Be room temperature, T is actual Kelvin; μ refers to carrier mobility;

For MOSFET, its threshold voltage vt h can be represented by formula (2) with the relation of temperature:

$\mathrm{Vth}\left(T\right)=\mathrm{Vth}\left(T_0\right)-\∂\left({T-T}_0\right)---\left(2\right)$

T is wherein arranged ₀=300K,

Vth is the threshold voltage of MOSFET.

The conducting resistance R of MOSFET _OnBe expressed from the next:

$\mathrm{Ron}=\frac{1}{\mathrm{\μ}{C}_{\mathrm{OX}}\frac{W}{L}\left|(V_{\mathrm{GS}}-V_{\mathrm{th}})\right|}---\left(3\right)$

Wherein, R _OnBe the conducting resistance of MOSFET, V _GSBe gate source voltage, W/L is the breadth length ratio of metal-oxide-semiconductor, C _OXCoefficient for gate capacitance.

When for example in phase-locked loop or oscillator etc., the circuit of the N that is cascaded a CMOS inverter will produce time-delay, corresponding time-delay T _Delay(INV) can represent by formula (4):

T _delay(INV)≈N×R _out×(C _out+C _in) (4)

Wherein, R _OutThe output resistance of expression inverter, C _OutThe output capacitance of representing CMOS inverter at the corresponding levels, C _InThe input capacitance of expression next stage inverter, N=2n represents the number of inverter.Usually, NMOS pipe in the CMOS inverter and PMOS pipe always another pipe of pipe conducting end, therefore, and R _OutCan equal above-mentioned conducting resistance haply.

By top formula (1)-(4) as can be known, for the sequence circuit of N CMOS inverter series connection, time corresponding postpones T _{Delay (INV)}To increase along with the rising of temperature, and reduce along with decrease of temperature.That is to say that under the influence of said temperature, the time delay of above-mentioned CMOS inverter may produce temperature and float, and can change within a large range; And if under the situation that the PVT operating mode all changes, situation may be bad more.Especially, in the circuit application that requires accurately control time-delay, this is that those skilled in the art do not expect.

Therefore, need now a kind ofly can suppress the CMOS delay circuit that temperature is floated.

The utility model content

A purpose of the present utility model is to solve the temperature that the CMOS delay circuit exists in the prior art at least and floats problem.According to CMOS delay circuit of the present utility model, can effectively the temperature of CMOS delay circuit be floated and be controlled within the ideal range, thereby satisfy the high-precision requirement that temperature is floated that may exist in the side circuit design.

According to an aspect of the present utility model, a kind of CMOS delay circuit is provided, comprise: delay cell, be configured between the CMOS inverter of at least two series connection, the temperature delay characteristic of described delay cell is opposite with the temperature delay characteristic of described CMOS inverter.

According to an embodiment of the present utility model, described delay cell comprises a RC circuit, and described RC circuit comprises a resistance R and a capacitor C, and described resistance R is connected between described two CMOS inverters, one end of described capacitor C is connected other end ground connection with an end of described resistance R.

According to an embodiment of the present utility model, described resistance R is the resistance that is negative temperature coefficient.

According to an embodiment of the present utility model, described resistance is P type polysilicon resistance.

According to an embodiment of the present utility model, one or more delay cells be configured in any two adjacent and the series connection the CMOS inverter between.

Description of drawings

When the detailed description of reading in conjunction with the accompanying drawings hereinafter exemplary embodiment, these and other purpose, feature and advantage will become apparent, in the accompanying drawings:

Fig. 1 shows the schematic diagram of the CMOS inverter delay circuit of prior art;

Fig. 2 shows the schematic diagram according to the improved CMOS delay circuit of each embodiment of the utility model; And

Fig. 3 shows the schematic diagram according to the CMOS delay circuit that comprises the RC circuit of the utility model preferred embodiment.

Embodiment

Fig. 2 shows the schematic diagram according to the improved CMOS delay circuit of each embodiment of the utility model.This delay circuit comprises the CMOS inverter 210 of N series connection, and wherein N can equal 2n.In an example, this delay circuit also comprises the delay cell 220 between two CMOS inverters that are arranged in adjacent arbitrarily and series connection.This delay cell 220 is the temperature delay characteristic opposite with described CMOS inverter 210.As previously discussed, the temperature delay characteristic of the CMOS inverter 210 of existing N series connection is the rising along with temperature, and postponing increases, and promptly is positive temperature delay characteristic.And the delay cell 220 in this example of the present utility model is the negative temperature lag characteristic, and promptly along with the rising of temperature, the delay of delay cell 220 reduces.

The delay (for example process corner, temperature and/or the supply voltage by metal-oxide-semiconductor determines) that is appreciated that the total delay that improves delay circuit or delays time and will not only depend on series connection CMOS inverter itself also depends on the delay of delay cell 220.And because delay cell 220 and CMOS inverter 210 are opposite temperature delay characteristic, delay cell 220 is floated the temperature of compensation CMOS inverter 210, thereby the temperature that suppresses whole delay circuit is floated.It will be understood by those skilled in the art that the delay cell that can implement arbitrary structures, form or quantity, it all drops within the protection range of the present utility model.

Fig. 3 shows the CMOS delay circuit that comprises the RC circuit according to the utility model preferred embodiment.This delay circuit comprises N CMOS inverter 210 and is arranged in delay cell 220 between any two CMOS inverters of series connection that wherein N can equal 2n.This delay cell 220 comprises the RC circuit.Resistance R is connected in series between two CMOS inverters, and capacitor C one end connects resistance R, other end ground connection.R is a negative temperature coefficient resister.

The delay or the time-delay that comprise the CMOS delay circuit of RC circuit can be illustrated by formula (5):

T _delay(new)＝T _delay(INV)+T _delay(RC) (5)

Wherein, T _{Delay (RC)}≈ R*C.

Described negative temperature coefficient resister R is along with the rising of temperature, and the charge carrier number increases, and resistance value reduces; Otherwise along with the reduction of temperature, the charge carrier number reduces, and resistance value increases.Thus, the RC circuit is the negative temperature lag characteristic.And T _{Dclay (INV)}Be positive temperature delay characteristic as previously mentioned, therefore when the RC circuit that will be the negative temperature lag characteristic is cascaded with the CMOS inverter that is positive temperature delay characteristic, the RC circuit compensation temperature of series connection CMOS inverter float, suppressed the temperature drift of whole delay circuit effectively.The RC circuit is the preferred embodiment of delay cell, and in addition because the RC circuit structure is simple, its favourable part is and is unlikely the complexity that increases original delay circuit.

According to the preferred embodiment of the utility model, the resistance R in the RC circuit is a P type polysilicon resistance, and the resistance value of this P type polysilicon resistance is along with temperature rises, and resistance value reduces.Table 1 shows the resistance-temperature characteristic of P type polysilicon resistance.

Table 1

By table 1 as seen, this P type polysilicon resistance is negative temperature characteristic, and then the RC circuit of its formation also will be the negative temperature lag characteristic, thereby is opposite temperature delay characteristic with the CMOS inverter, realizes the compensation that CMOS inverter temperature is floated.

Can accurately design each parameter in the delay cell (such as the RC circuit), float with the temperature of compensation CMOS inverter substantially.

Following table 2 shows the example that design has the comparison of the utility model delay circuit of 30ns time-delay and existing delay circuit.This table 2 is that these two delay circuits are tested under identical PVT (technology, temperature and voltage) operating mode, wherein each self-test these two delay circuits under condition of different temperatures time-delay and the temperature of having calculated them float the delay scope.It should be appreciated by those skilled in the art that this table 2 does not constitute any restriction to the utility model scope.

Table 2

Design time-delay=30ns	The delay circuit that adds the RC compensation	The delay circuit that has only inverter
			PVT (technology, temperature, voltage)	Time-delay (ns)	Time-delay (ns)
tt 40 5	31.48	29.68
			tt2 40 5	31.48	29.68
ff -40 5	30.4	18
			ss 160 4.5	35.97	50
ff2 160 4.5	30.8	39.4
			ss2 -40 5.5	35.69	21.96
ss3 -40 4.5	35.3	28.9
			fs 160 5.5	35.55	44.4
sf -40 4.5	31.73	24.9
			Excursion	8％	38.90％

As seen from the above table, the temperature of existing delay circuit is floated the delay scope can be near 40%, than existing delay circuit, delay circuit of the present utility model temperature can be floated the delay scope for example be controlled at effectively ± 10%, even within the littler ideal range.Thus, to float the advantage of delay scope be conspicuous to the temperature that realizes according to delay circuit of the present utility model.

In practice, those skilled in the art can float the process corner parameter of the continuous feedback adjusting of number range such as CMOS according to the temperature of reality test, and/or the parameter value of the resistance of RC circuit and/or electric capacity, thereby make delay cell such as the RC circuit substantially the temperature of compensation CMOS inverter float, to satisfy the high-precision requirement of the scope of in the practical application temperature being floated.

According to each embodiment of the present utility model, improved delay circuit is applicable to the temperature range of high temperature or low temperature.Can be applied to a variety of IC circuit, for example in Switching Power Supply, phase-locked loop (PLL) and/or the oscillator (OSC).

According to embodiment of the present utility model, can test the delay unit amount of arranging between two CMOS inverters of effect selection according to reality, and/or adjust the value of the parameter in the delay cell (in the RC circuit).

Although described and illustrated embodiment of the present utility model here, those of ordinary skills will imagine in the scope of the inventive embodiments that various other means of being used for one or more advantage of carrying out function described herein and/or obtaining result described herein and/or advantage described herein and/or structure and variation that each is such and/or modification be considered as here describing easily.More generally, the person skilled in the art will easily understand all parameters described herein, yardstick, material and configuration be for example and actual parameter, yardstick, material and/or configuration will depend on the utility model instruction and be applied to one of them or a plurality of concrete application.

Those skilled in the art will be familiar with or can only use routine experiment to establish the many equivalent embodiment of concrete inventive embodiments described herein.Therefore will understand and only present previous embodiment and in the scope of appended claims and equivalents thereof, can use the mode except specific descriptions and claimed mode to realize inventive embodiments by example.The inventive embodiments of present disclosure relates to each individual characteristics described herein, system, product, material, kit and/or method.In addition, if how such two or more feature, system, product, material, kit and/or method be not internally inconsistent, then in the invention scope of present disclosure, comprise any combination of such feature, system, product, material, kit and/or method.

As all definition that define here and use should be understood to arrange dictionary definition, by reference and its ordinary meaning of the term of definition in the document of combination and/or definition.

As here in specification and the indefinite article that in claims, uses "/a kind of " unless clearly indicate and then should be understood to mean " at least one/a kind of " on the contrary.As here in specification and the phrase " at least one " that in claims, uses should be understood to mean when the tabulation of quoting one or more key element at least one key element of selecting in any one or a plurality of key element in the key element from key element is enumerated, but any combination that may not be included at least one key element in the key element of specifically enumerating in the key element tabulation one by one and not get rid of the key element in the key element tabulation.This definition also allow to exist alternatively the key element that in the key element tabulation of quoting, specifically identifies at phrase " at least one ", no matter be and the relevant or irrelevant key element of those key elements of concrete sign.Therefore, as unrestricted example, " at least one among A and the B " (perhaps equivalence is " at least one among A and/or the B " for " at least one among A or the B " or equivalence) can refer at least one A in one embodiment, comprise that a plurality of A do not have B and have (and comprise alternatively except B key element) alternatively; Refer at least one B in another embodiment, comprise a plurality of B alternatively and do not have A and have (and comprise alternatively except A key element); Refer in another embodiment at least one A, alternatively comprise a plurality of A and at least one B, comprise a plurality of B (and comprising other key element alternatively) alternatively; Or the like.

Unless also should be appreciated that clearly indication on the contrary, in the claimed here any method that comprises a plurality of steps or action, the step of method or the order of action may not be limited to the step of record method or the order of action.In addition, any label that occurs between the bracket in claims or other symbol only provide and are not intended to for convenience and limit by any way.

Claims (5)

1. CMOS delay circuit comprises:

Delay cell is configured between the CMOS inverter of two series connection at least, and the temperature delay characteristic of described delay cell is opposite with the temperature delay characteristic of described CMOS inverter.

2. circuit according to claim 1, wherein said delay cell comprises a RC circuit, and described RC circuit comprises a resistance R and a capacitor C, and described resistance R is connected between described two CMOS inverters, one end of described capacitor C is connected other end ground connection with an end of described resistance R.

3. circuit according to claim 2, wherein said resistance R are the resistance that is negative temperature coefficient.

4. circuit according to claim 3, wherein said resistance are P type polysilicon resistance.

5. according to each described circuit in the claim 1 to 4, wherein one or more delay cells are configured between the CMOS inverter of any two adjacent and series connection.

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