CN207053480U

CN207053480U - Input and output drive circuit

Info

Publication number: CN207053480U
Application number: CN201720770237.7U
Authority: CN
Inventors: 陆敏
Original assignee: Hefei Can Core Technology Co Ltd
Current assignee: Hefei Can Core Technology Co Ltd
Priority date: 2017-06-29
Filing date: 2017-06-29
Publication date: 2018-02-27
Anticipated expiration: 2027-06-29

Abstract

The utility model provides a kind of input and output drive circuit, and it includes：Output pin；Power end；Earth terminal；First output driving transistor, its source electrode are connected with power end, and its drain electrode is connected with output pin；First electric capacity, it is connected between the grid of output pin and the first output driving transistor；Second output driving transistor, its source electrode are connected with earth terminal, and its drain electrode is connected with output pin；Second electric capacity, it is connected between the grid of output pin and the second output driving transistor；First predrive circuit, its input receive input signal, and its output end is connected with the grid of the first output driving transistor；Second predrive circuit, its input receive input signal, and its output end is connected with the grid of the second output driving transistor.So, the rising and falling time (or flip-flop transition) of output signal is unrelated with external load capacitance.

Description

Input and output drive circuit

【Technical field】

It the utility model is related to imput output circuit field, more particularly to a kind of input and output drive circuit.

【Background technology】

Integrated circuit (IC) is referred to as IO (input＆output) circuit with the extraneous circuit for carrying out signal transmission.I/O circuit one As be made up of the drive circuit of realizing output function and the receiving circuit for realizing input function.Due to the load capacitance outside IO Capacitance is unknown, it is possible to which excursion is very big, causes the flip-flop transition of the output signal of IO drive circuit may also can be with The change of load capacitance and change.And some I/O circuits have clear and definite regulation to the excursion of the flip-flop transition of output signal, It may can now can not meet these regulations.

For example the excursion of USB1.1 Low speed mode (low-speed mode) external capacitive will reach 200pf ~600pf, rise and fall time need to reach 75~300ns, and the space for so leaving other specification change for is just very small.

Fig. 1 shows a kind of existing IO drive circuits.As shown in figure 1, include in chip output transistor MN11, MP11 and prime PMOS and NMOS predrives circuit (pre-driver).

MP11 gate nodes are referred to as N11, and MN11 gate nodes are referred to as N21.

Work as N11=0, during N21=0, MP11 is opened, and MN11 is closed, the conducting resistance RMP11 that power end VDD passes through MP11 External load capacitance CL1 on output pin IO is charged, the signal on output pin IO since 0 toward VDD according toSpeed toward rise.

Work as N11=VDD, during N21=VDD, MP1 is closed, and MN1 is opened, the conducting resistance that earth terminal VSS passes through MN11 RMN11 discharges the external load capacitance CL1 on output pin IO, the signal on output pin IO since VDD toward 0 according toSpeed toward decline.

It can be seen that the speed of its raising and lowering is all strong related to external load capacitance CL1.If external loading is electric It is very big to hold CL excursions, rise and fall time excursion will be caused very big.Because outputs of some IO to drive circuit is turned over The excursion for turning the time requires smaller, and the excursion of output end load capacitance is bigger, if done using conventional Method, because the output switching activity time can change with the change of output end load capacitance, so leave process corner, voltage, temperature model for The change remaining enclosed is with regard to smaller, it may be difficult to ensures all process corners, voltage, temperature range all meets to require.

【Utility model content】

One of the purpose of this utility model is to provide a kind of input and output drive circuit, the rising of its output signal and under Drop time (or flip-flop transition) does not change with the change of external load capacitance.

In order to solve the above problems, according to one side of the present utility model, the utility model provides a kind of input and output Drive circuit, it includes：Output pin；Power end；Earth terminal；First output driving transistor, its source electrode are connected with power end, Its drain electrode is connected with output pin；First electric capacity, it is connected between the grid of output pin and the first output driving transistor； Second output driving transistor, its source electrode are connected with earth terminal, and its drain electrode is connected with output pin；Second electric capacity, it is connected to Between the grid of output pin and the second output driving transistor；First predrive circuit, its input receive input signal, its Output end is connected with the grid of the first output driving transistor；Second predrive circuit, its input receive input signal, and its is defeated Go out end with the grid of the second output driving transistor to be connected.

Further, the first output driving transistor is PMOS transistor, and the second output driving transistor is NMOS crystal Pipe.

Further, the first predrive circuit includes the second PMOS transistor, the second nmos pass transistor and the first current source, Wherein, the source electrode of the second PMOS transistor is connected with power end, drain electrode and the second PMOS transistor of the second nmos pass transistor Drain electrode is connected, and as the output end of the first predrive circuit, the input of the source electrode of the second nmos pass transistor and the first current source End is connected, and the output end of the first current source is connected with earth terminal, the grid of the second PMOS transistor and the second nmos pass transistor Grid is connected, and as the input of the first predrive circuit.

Further, the second predrive circuit includes the 3rd PMOS transistor, the 3rd nmos pass transistor and the second current source, Wherein, the input of the second current source is connected with power end, the source electrode of the 3rd PMOS transistor and the output end of the second current source It is connected, the drain electrode of the 3rd nmos pass transistor is connected with the drain electrode of the 3rd PMOS transistor, and as the defeated of the second predrive circuit Go out end, the source electrode of the 3rd nmos pass transistor is connected with earth terminal, the grid of the 3rd PMOS transistor and the 3rd nmos pass transistor Grid is connected, and as the input of the second predrive circuit.

Further, the input and output drive circuit is located in integrated circuit.

Further, the moment of high level is turned by low level in input signal INPUT, the second nmos pass transistor is opened, the Two PMOS transistors are closed, and the 3rd nmos pass transistor is opened, and the 3rd PMOS transistor is closed, in input signal INPUT by high electricity Flat turn low level moment, the second nmos pass transistor are closed, and the second PMOS transistor is opened, and the 3rd nmos pass transistor is closed, the Three PMOS transistors are opened.

Further, the output pin is connected with external load capacitance.

Compared with prior art, in the utility model, the rising and falling time (or flip-flop transition) of output signal with External load capacitance is unrelated, so leaves process corner for, voltage, the change remaining of temperature range is with regard to bigger, it is easier to ensures institute There are process corner, voltage, temperature range all meets to require.

【Brief description of the drawings】

It is required in being described below to embodiment in order to illustrate more clearly of the technical scheme of the utility model embodiment The accompanying drawing used is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present utility model Example, for those of ordinary skill in the art, without having to pay creative labor, can also be according to these accompanying drawings Obtain other accompanying drawings.Wherein：

Fig. 1 shows a kind of circuit diagram of existing input and output drive circuit；

Fig. 2 is the circuit diagram of input and output drive circuit in one embodiment in the utility model.

【Embodiment】

To enable above-mentioned purpose of the present utility model, feature and advantage more obvious understandable, below in conjunction with the accompanying drawings and tool Body embodiment is described in further detail to the utility model.

" one embodiment " or " embodiment " referred to herein refers to may be included at least one realization side of the utility model Special characteristic, structure or characteristic in formula." in one embodiment " that different places occur in this manual not refers both to Same embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.

Fig. 1 shows the circuit structure diagram of input and output drive circuit in one embodiment in the utility model.Institute Input and output drive circuit is stated in an integrated circuit (or chip).Input and output drive circuit in the utility model Output signal rising and falling time (or flip-flop transition) it is unrelated with external load capacitance, so leave process corner for, electricity Pressure, the change remaining of temperature range is with regard to bigger, it is easier to ensures all process corners, voltage, temperature range all meets to require.

The input and output drive circuit includes：The output pin IO of the integrated circuit, the output pin are connected with External load capacitance CL；Power end VDD；Earth terminal；First output driving transistor MP1, its source electrode are connected with power end VDD, Its drain electrode is connected with output pin IO；First electric capacity C1, it is connected to output pin IO's and the first output driving transistor MP1 Between grid (node can be referred to as N1 nodes)；Second output driving transistor MN1, its source electrode are connected with earth terminal, its Drain electrode is connected with output pin IO；Second electric capacity C2, it is connected to output pin IO and the second output driving transistor MN1 grid Between pole (node can be referred to as N2 nodes)；First predrive circuit 210, its input receive input signal INPUT, its Output end is connected with the first output driving transistor MP1 grid；Second predrive circuit 220, its input receive input letter Number, its output end is connected with the second output driving transistor MN1 grid.First output driving transistor is PMOS (P- Channel Metal Oxide Semiconductor) transistor, the second output driving transistor is NMOS (N-channel Metal Oxide Semiconductor) transistor.

First predrive circuit 210 includes the second PMOS transistor MP2, the second nmos pass transistor MN2 and the first current source I1.Wherein, the second PMOS transistor MP2 source electrode is connected with power end VDD, the second nmos pass transistor MN2 drain electrode and second PMOS transistor MP2 drain electrode is connected, and as the output end of the first predrive circuit 210, the second nmos pass transistor MN2 source Pole is connected with the first current source I1 input, and the first current source I2 output end is connected with earth terminal, the second PMOS transistor MP2 grid and the second nmos pass transistor MN2 grid are connected, and as the input of the first predrive circuit 210.

Second predrive circuit 220 includes the 3rd PMOS transistor MP3, the 3rd nmos pass transistor MN3 and the second current source I2.Wherein, the second current source I2 input is connected with power end VDD, the 3rd PMOS transistor MP3 source electrode and the second electric current Source I2 output end is connected, and the 3rd nmos pass transistor MN3 drain electrode is connected with the 3rd PMOS transistor MP3 drain electrode, and conduct The output end of second predrive circuit 220, the 3rd nmos pass transistor MN3 source electrode are connected with earth terminal, the 3rd PMOS transistor MP3 grid and the 3rd nmos pass transistor MN3 grid are connected, and as the input of the second predrive circuit 220.First is pre- The input of the input of drive circuit 210 and the second predrive circuit 220 is connected.

Just analyze below the input and output drive circuit in the utility model be how to realize flip-flop transition not with External capacitive load changes and changed.

Turn the moment of high level by low level in input signal INPUT, the second nmos pass transistor MN2 is opened, the 2nd PMOS Transistor MP2 is closed, and the 3rd nmos pass transistor MN3 is opened, and the 3rd PMOS transistor MP3 is closed.Due to the 3rd nmos pass transistor MN3 conducting electric current, so its electric current can be very big, causes node N2 moments to be pulled to low low not by the current limliting of constant-current source, Second output driving transistor MN1 is closed.But due to MN2 conducting electric current by the first current source I1 current limliting so that node N1 is low (low) by slowly drawing, and so as to which the first output driving transistor MP1 can be slowly opened, its speed can be examined so Amount:

It is I1's (the first current source I1 current value) that an electric current can be now formed between node N1 and earth terminal VSS Discharge path, it can be obtained by the formula of capacitor charge and discharge:

I1 × t=C1 × (V_N1-V_IO) (1),

Wherein C1 be the first electric capacity capacitance, V_N1For node N1 magnitude of voltage, V_IOFor output pin IO magnitude of voltage,

Amplifying formula by MP1 common-source stage can obtain:

V_IO=-V_N1×(g_MP1×R_out) (2)

Wherein g_MP1For MP1 mutual conductance, R_outFor MP1 output resistance,

Simultaneous equations (1) and (2), can be obtained：

WhereinIt it is exactly the rise time of the output signal of output pin, it is seen that the current value of itself and the first current source I1 is relevant with the first electric capacity C1, unrelated with external capacitive load C L.

The fall time of the output signal of output pin can similarly be obtained only and the current value I2 of the second current source and second is electric It is relevant to hold C2, it is unrelated with external capacitive load C L.

As long as it follows that circuit indoor design good I1, I2, C1, C2, it is possible to fix under output pin IO rising The time is dropped, it is not changed with CL change.

It is pointed out that one skilled in the art specific embodiment of the present utility model is done it is any Change the scope all without departing from claims of the present utility model.Correspondingly, the scope of claim of the present utility model It is not limited only to previous embodiment.

Claims

1. a kind of input and output drive circuit, it is characterised in that it includes：

Output pin；

Power end；

Earth terminal；

First output driving transistor, its source electrode are connected with power end, and its drain electrode is connected with output pin；

First electric capacity, it is connected between the grid of output pin and the first output driving transistor；

Second output driving transistor, its source electrode are connected with earth terminal, and its drain electrode is connected with output pin；

Second electric capacity, it is connected between the grid of output pin and the second output driving transistor；

First predrive circuit, its input receive input signal, its output end and the grid phase of the first output driving transistor Even；

Second predrive circuit, its input receive input signal, its output end and the grid phase of the second output driving transistor Even.

2. input and output drive circuit according to claim 1, it is characterised in that the first output driving transistor is PMOS Transistor, the second output driving transistor are nmos pass transistor.

3. input and output drive circuit according to claim 1, it is characterised in that the first predrive circuit includes second PMOS transistor, the second nmos pass transistor and the first current source,

Wherein, the source electrode of the second PMOS transistor is connected with power end, the drain electrode of the second nmos pass transistor and the 2nd PMOS crystal The drain electrode of pipe is connected, and as the output end of the first predrive circuit, the source electrode of the second nmos pass transistor and the first current source Input is connected, and the output end of the first current source is connected with earth terminal, the grid of the second PMOS transistor and the 2nd NMOS crystal The grid of pipe is connected, and as the input of the first predrive circuit.

4. input and output drive circuit according to claim 3, it is characterised in that the second predrive circuit includes the 3rd PMOS transistor, the 3rd nmos pass transistor and the second current source,

Wherein, the input of the second current source is connected with power end, and the source electrode of the 3rd PMOS transistor is defeated with the second current source Go out end to be connected, the drain electrode of the 3rd nmos pass transistor is connected with the drain electrode of the 3rd PMOS transistor, and is used as the second predrive circuit Output end, the source electrode of the 3rd nmos pass transistor is connected with earth terminal, the grid and the 3rd NMOS crystal of the 3rd PMOS transistor The grid of pipe is connected, and as the input of the second predrive circuit.

5. input and output drive circuit according to claim 1, it is characterised in that the input and output drive circuit is located at In integrated circuit.

6. input and output drive circuit according to claim 4, it is characterised in that

Turn the moment of high level by low level in input signal INPUT, the second nmos pass transistor is opened, and the second PMOS transistor is closed Closing, the 3rd nmos pass transistor is opened, and the 3rd PMOS transistor is closed,

Low level moment is turned by high level in input signal INPUT, the second nmos pass transistor is closed, and the second PMOS transistor is opened Open, the 3rd nmos pass transistor is closed, and the 3rd PMOS transistor is opened.

7. input and output drive circuit according to claim 1, it is characterised in that the output pin is connected with outside negative Carry electric capacity.