CN101488472A - Method for manufacturing metal line of semiconductor device - Google Patents
Method for manufacturing metal line of semiconductor device Download PDFInfo
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- CN101488472A CN101488472A CNA2008101853557A CN200810185355A CN101488472A CN 101488472 A CN101488472 A CN 101488472A CN A2008101853557 A CNA2008101853557 A CN A2008101853557A CN 200810185355 A CN200810185355 A CN 200810185355A CN 101488472 A CN101488472 A CN 101488472A
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- pattern
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- photoresist pattern
- dielectric
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Provided is a method of manufacturing a metal interconnection of a semiconductor device. According to the method, a first dielectric is formed on a semiconductor substrate having a device thereon, and a second dielectric and a metal layer pattern are formed on the first dielectric. Then, a first polymer pattern surrounding a photoresist pattern is formed on the second dielectric, and a via hole is formed in the second dielectric by etching using the first polymer pattern as a mask. The photoresist pattern and the polymer pattern are removed, and a contact is formed by filling the via hole. In the invention, the size of the contact is less than the interval or hole in the photoresist pattern, and the full margin can be obtained in the forming period of the photoresist pattern, thus the yield of the semiconductor device can be increasred, the less hole can be obtained without additional devices.
Description
Technical field
The present invention relates to a kind of manufacture method of metal interconnecting piece of semiconductor device.
Background technology
Metal interconnecting piece is as interconnecting part, power delivery part and signal Transmission Part between the transistor in the integrated circuit (IC).
Owing to the Highgrade integration of design rule along with recent semiconductor device reduces, thereby the narrowed width of metal interconnecting piece, the degree of depth deepen, and promptly depth-to-width ratio increases.
A demand of development semiconductor device is: in the formation minimization defective of each metal interconnect layer.
Summary of the invention
The embodiment of the invention provides a kind of manufacture method of metal interconnecting piece of semiconductor device.
In one embodiment, a kind of manufacture method of metal interconnecting piece of semiconductor device may further comprise the steps: have in the above and form first dielectric on the Semiconductor substrate of device; On this first dielectric, form second dielectric and metal layer pattern; On this second dielectric, form first polymer pattern that surrounds the photoresist pattern; Use this first polymer pattern to carry out etch process, on this Semiconductor substrate, to form through hole as mask; After forming this through hole, remove this photoresist pattern and this second polymer pattern; And, form contact by filling this through hole.
In one embodiment, a kind of manufacture method of metal interconnecting piece of semiconductor device may further comprise the steps: have thereon and form first dielectric on the Semiconductor substrate of device; On this first dielectric, form metal layer pattern; On this metal layer pattern, form second dielectric; Form the photoresist pattern on this second dielectric, this photoresist pattern limits a plurality of through holes; Form first polymer pattern that surrounds this photoresist pattern; By using this first polymer pattern and this photoresist pattern as mask and this second dielectric of etching, to form described through hole; After forming described through hole, remove this photoresist pattern and this first polymer pattern; And, form contact by using conductor filled described through hole.
In accompanying drawing and following description, set forth the details of one or more embodiment.For those of ordinary skills, by specification, accompanying drawing and claims, other feature is conspicuous.
Therefore the present invention does not need extra equipment to obtain the littler hole of size owing to the KrF lithographic equipment that uses known technology forms the photoresist pattern.
Description of drawings
Fig. 1 is the cutaway view that the example fabrication method of metal interconnecting piece is shown according to the embodiment of the invention to Fig. 8.
Embodiment
Hereinafter, will be described in detail with reference to the attached drawings manufacture method according to the metal interconnecting piece of the embodiment of the invention.
Should be appreciated that when one deck (perhaps film) be regarded as be positioned at another the layer or substrate " on " time, its can be located immediately at another the layer or substrate on, also can have the intermediate layer.
In the accompanying drawings, the thickness in layer and zone or size can be used to make diagram clear.In addition, can exaggerate relative size between element size and the element, understand the present invention with better.
Fig. 1 is the cutaway view that the example fabrication method of metal interconnecting piece is shown according to the embodiment of the invention to Fig. 8.
As shown in Figure 1, interlayer dielectric 20 is formed on the Semiconductor substrate 10, be formed with one or more devices on Semiconductor substrate 10, and metal layer pattern 25 is formed on the interlayer dielectric 20.Can be formed on the Semiconductor substrate 10 as devices such as transistor, diode, electric capacity, resistance.Dielectric layer can comprise foot (lowermost), conformal (conformal) etching stopping layer (as silicon nitride), conformal buffer and/or gap packed layer are (as silicon rich silicon oxide (SRO), TEOS (silica that forms by CVD as tetraethoxysilane and oxygen), the mixture of undoped silicate glass (USG) or above-mentioned substance) and body dielectric layer (bulk dielectric layer) (as one or more silicon oxide layer (BSG of doped with boron and/or phosphorus, PSG and/or BPSG)).Perhaps, the body dielectric layer can comprise low K dielectrics, as fluorosilicate glass (FSG), silicon oxide carbide (SiOC) or hydrogenated silicon oxycarbide (SiOCH), wherein any one all can comprise the low k dielectric layer of low k dielectric layer in the top that is positioned at middle etch stop layer (as silicon nitride) above and below and bottom.Dielectric layer can also comprise cover layer, as the mixture of TEOS, USG, plasma silane (plasma silane) (silicon dioxide that forms by plasma assisted CVD as the silicon dioxide of forming by silicon and oxygen) or above-mentioned substance, as the bilayer (bilayer) of the plasma silane on USG or the TEOS or the bilayer of the USG on the TEOS.
By on interlayer dielectric 20, forming metal level and, obtaining metal layer pattern 25 with its patterning.
Metal level can comprise that aluminium or aluminium alloy (as have percentage by weight and reach 4% copper, percentage by weight reaches the aluminium that 2% titanium and/or percentage by weight reach 1% silicon), its by on existing adhesive and/or barrier layer (as Ti and/or TiN, for example Ti goes up TiN (TiN-on-Ti) bilayer) go up sputter and deposit, and/or by existing adhesive, block piece, mound shape inhibition part (hillock suppression) and/or anti-reflecting layer (antireflective layers) are (as Ti, TiN, WN, the mixture of TiW alloy or above-mentioned substance, for example Ti goes up the TiN bilayer or Ti goes up the TiW bilayer) cover, can form by sputter or chemical vapor deposition (CVD).
As shown in Figure 2, second dielectric layer 30 is formed on the metal layer pattern 25.Second dielectric layer 30 can comprise the number of plies and/or the material identical with dielectric layer 20.
Then, as shown in Figure 3, photoresist pattern 100 is formed on the dielectric 30.
As shown in Figure 4, first polymeric layer 40 is formed on dielectric 30 and the photoresist pattern 100.First polymeric layer 40 has covered photoresist pattern 100, and can form by the rotation coating.First polymeric layer 40 surrounds the top and the sidepiece (as sidewall) of photoresist pattern 100.
First polymeric layer 40 can comprise thermosetting (thermosetting) material.For example, first polymeric layer 40 can by polyurethane (polyurethane, PU), phenolic resins, melmac or alkyd resins form, but be not limited to this.Some can also can be suitable for according to the epoxy resin that step described herein removes.
As shown in Figure 5, the second polymer layer 45 is formed between the photoresist pattern 100 and first polymeric layer 40, to form the second polymer layer 45.
By the Technology for Heating Processing on Semiconductor substrate 10, can between the photoresist pattern 100 and first polymeric layer 40, form the second polymer layer, thereby obtain second polymer pattern 45, wherein Semiconductor substrate 10 comprises the photoresist pattern 100 and first polymeric layer 40.The baking process of serviceability temperature between 90 ℃ to 300 ℃ can be carried out Technology for Heating Processing.Because the photoresist pattern 100 and first reaction of polymeric layer 40 during Technology for Heating Processing, thereby form the second polymer layer.
As shown in Figure 6, remove first polymeric layer 40 that is positioned on second polymer pattern 45.Can remove first polymeric layer 40 on second polymer pattern 45 by developing process (developing process).
When removing first polymeric layer 40, do not remove second polymer pattern 45 by developing process.The photoresist pattern 100 and second polymer pattern 45 remain on the Semiconductor substrate 10 that has removed first polymeric layer 40.At this moment, second polymer pattern 45 surrounds photoresist pattern 100.
In addition, the interval between second polymer pattern 45 is less than the interval between the photoresist pattern 100.That is, the size in the hole between the photoresist pattern 100 reduces because of the thickness of second polymer pattern 45 of encirclement photoresist pattern 100.
As shown in Figure 7, use second polymer pattern 45, go up in Semiconductor substrate 10 (more particularly, being second dielectric layer 30) and carry out etch process, to form the through hole 50 of exposing metal layer pattern 25 as mask.
Because the width in the hole between second polymer pattern 45 is less than the interval between the photoresist pattern 100, so the width of the through hole 50 that forms by etch process is less than the interval between the photoresist pattern.
That is, during the formation of photoresist pattern 100 resist of KrF (KrF) photoetching (as be used for), can obtain sufficient nargin (margin).By form surrounding the second polymer layer of photoresist pattern 100, to dwindle the interval between the photoresist pattern 100, contact big or small relative little that just can make formation after a while.
The metal interconnecting layer 70 that is arranged in dielectric 30 comprises metal layer pattern 25 and contact 60, in obtain metal interconnecting layer 70 by removing the photoresist pattern 100 and second polymer pattern 45 and filling vias 50 to form contact 60.By using the through hole 50 in tungsten (W) filling dielectric 30 and carrying out flatening process, can form contact 60.Tungsten can deposit by CVD, and is formed on existing adhesive and/or barrier layer (as Ti, TiN and/or TiW, for example Ti goes up the TiN bilayer).Ti, TiN and TiW layer can deposit by CVD or sputter.
According to the manufacture method of the metal interconnecting piece of above-mentioned semiconductor device, littler than interval in the photoresist pattern or hole by the size that forms the second polymer layer to surround the photoresist pattern, can make the contact that forms after a while.
In addition, during the formation of photoresist pattern, can obtain sufficient nargin.Therefore, can increase finished semiconductor device product rate.
In addition, owing to KrF (KrF) lithographic equipment that uses known technology forms the photoresist pattern, therefore do not need extra equipment to obtain the littler hole of size.
" embodiment ", " embodiment " that mention in this manual, " exemplary embodiment " etc. means that all described in conjunction with the embodiments specific feature, structure or characteristic are at least one embodiment of the present invention involved.These words that occur everywhere at this specification might not all refer to same embodiment.In addition, when describing specific feature, structure or characteristic, think that then it falls into those skilled in the art and can implement in conjunction with other embodiment in the scope of these features, structure or characteristic in conjunction with arbitrary embodiment.
Though above reference a plurality of exemplary embodiments of the present invention and embodiment is described it should be understood that those of ordinary skills can derive other any variation and the embodiment in the spirit and scope that drop on this open principle.More specifically, can be open at this, various changes and variation are carried out in the arrangement in assembly and/or the subject combination arrangement in the scope of accompanying drawing and appended claims.Except the change and variation of assembly and/or arrangement, to those skilled in the art, other application of the present invention also are conspicuous.
Claims (17)
1. the manufacture method of the metal interconnecting piece of a semiconductor device, this method comprises the steps:
Have thereon and form first dielectric on the Semiconductor substrate of device;
On this first dielectric, form second dielectric and metal layer pattern;
On this second dielectric, form first polymer pattern that surrounds the photoresist pattern;
Use this first polymer pattern as mask and etching, to form through hole;
After forming this through hole, remove this photoresist pattern and this first polymer pattern; And
By filling this through hole, form contact.
2. the method for claim 1, the step that wherein forms this first polymer pattern comprises:
On this second dielectric, form the photoresist pattern;
On this photoresist pattern, form the second polymer layer;
By between this photoresist pattern and this second polymer layer, forming first polymeric layer, form this first polymer pattern; And
Remove this second polymer layer that is positioned on this first polymer pattern.
3. method according to claim 2 wherein by carry out Technology for Heating Processing on this Semiconductor substrate with this photoresist pattern and this second polymer layer, forms this first polymer pattern.
4. method according to claim 3 is wherein carried out this Technology for Heating Processing 90 ℃ to 300 ℃ temperature.
5. method according to claim 2 wherein removes this second polymer layer by developing process.
6. method according to claim 1, wherein this second polymer layer comprises thermosets.
7. method according to claim 1 wherein when forming this through hole, exposes this metal layer pattern.
8. method according to claim 1, wherein this first polymer pattern surrounds the top and the sidepiece of this photoresist pattern.
9. method according to claim 1, wherein this first polymer pattern is spaced.
10. method according to claim 1, wherein this photoresist pattern is formed on the respective regions between a plurality of metal layer patterns.
11. the manufacture method of the metal interconnecting piece of a semiconductor device, this method comprises the steps:
Have thereon and form first dielectric on the Semiconductor substrate of device;
On this first dielectric, form metal layer pattern;
On this metal layer pattern, form second dielectric;
Form the photoresist pattern on this second dielectric, this photoresist pattern limits a plurality of through holes;
Form first polymer pattern that surrounds this photoresist pattern;
By using this first polymer pattern and this photoresist pattern as mask and this second dielectric of etching, to form described through hole;
After forming described through hole, remove this photoresist pattern and this first polymer pattern; And
By using conductor filled described through hole, form contact.
12. method according to claim 11, the step that wherein forms this first polymer pattern comprises:
On this photoresist pattern, form the second polymer layer;
By heating this photoresist pattern and this second polymer layer, this first polymer pattern of the formation at the interface between this photoresist pattern and this second polymer layer; And
Remove this second polymer layer that retains.
13. method according to claim 12, wherein this photoresist pattern and this second polymer layer are 90 ℃ to 300 ℃ temperature heating.
14. method according to claim 12, the step that wherein removes this second polymer layer that retains comprises this second polymer layer that develops.
15. method according to claim 12, wherein this second polymer layer comprises thermosets.
16. method according to claim 11 wherein forms this through hole to expose this metal layer pattern.
17. method according to claim 11, wherein this first polymer pattern surrounds the top and the sidewall of this photoresist pattern.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070135955A KR20090068082A (en) | 2007-12-22 | 2007-12-22 | Method for manufacturing metal line of semiconductor device |
| KR1020070135955 | 2007-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101488472A true CN101488472A (en) | 2009-07-22 |
Family
ID=40789067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008101853557A Pending CN101488472A (en) | 2007-12-22 | 2008-12-22 | Method for manufacturing metal line of semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20090162793A1 (en) |
| KR (1) | KR20090068082A (en) |
| CN (1) | CN101488472A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468227A (en) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor structure |
| CN103346119A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for decreasing critical size of copper-connection groove |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569168A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Manufacturing method of metal interconnection line |
| US10727045B2 (en) * | 2017-09-29 | 2020-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing a semiconductor device |
| CN110112056A (en) * | 2019-04-25 | 2019-08-09 | 中国科学院上海微系统与信息技术研究所 | A kind of preparation method of integrated morphology and thus obtained copper interconnecting line and dielectric material integrated morphology |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4583860B2 (en) * | 2004-10-04 | 2010-11-17 | 富士通株式会社 | Resist pattern thickening material, resist pattern forming method, semiconductor device and manufacturing method thereof |
-
2007
- 2007-12-22 KR KR1020070135955A patent/KR20090068082A/en not_active Application Discontinuation
-
2008
- 2008-12-16 US US12/336,486 patent/US20090162793A1/en not_active Abandoned
- 2008-12-22 CN CNA2008101853557A patent/CN101488472A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468227A (en) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor structure |
| CN103346119A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for decreasing critical size of copper-connection groove |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090162793A1 (en) | 2009-06-25 |
| KR20090068082A (en) | 2009-06-25 |
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Open date: 20090722 |