CN102569168A - Manufacturing method of metal interconnection line - Google Patents
Manufacturing method of metal interconnection line Download PDFInfo
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- CN102569168A CN102569168A CN2010106025663A CN201010602566A CN102569168A CN 102569168 A CN102569168 A CN 102569168A CN 2010106025663 A CN2010106025663 A CN 2010106025663A CN 201010602566 A CN201010602566 A CN 201010602566A CN 102569168 A CN102569168 A CN 102569168A
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Abstract
The invention provides a manufacturing method of a metal interconnection line. The manufacturing method comprises the following steps of: providing a semiconductor substrate; forming a metal layer on the surface of the semiconductor substrate; forming an anti-reflection layer on the surface of the metal layer; forming a photoresist layer on the surface of the anti-reflection layer, wherein an opening for exposing the anti-reflection layer is formed in the photoresist layer; etching the anti-reflection layer and the metal layer in sequence along the opening to form a metal interconnection line; etching the anti-reflection layer and the metal layer in sequence along the opening to form a metal interconnection line; etching along the opening to form a groove from which the semiconductor substrate is exposed; removing the anti-reflection layer and the photoresist layer above the metal interconnection line; and filling a medium layer into the groove. According to the manufacturing method, the stability of a metal interconnection line manufacturing process is enhanced under the condition of not increasing manufacturing cost and process complexity.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the manufacture method of metal interconnecting wires.
Background technology
In semi-conductor industry, interconnection structure is used to be provided at device and the wiring between the whole encapsulation on the IC chip.Usually, at first form the for example device of FET (FET), then at last part technology (BEOL, back-end-of-line) the middle interconnection structure that forms at semiconductor substrate surface.Said interconnection structure generally includes at least a dielectric material, is formed with metal interconnecting wires and contact plunger in this dielectric material.
The manufacture method of existing metal interconnecting wires please refer to Fig. 1～shown in Figure 5.At first, with reference to figure 1, Semiconductor substrate 100 is provided, said Semiconductor substrate 100 surfaces are formed with device layer, form metal level 101 on said Semiconductor substrate 100 surfaces then.The thickness range of said metal level 101 is 4000～6000 dusts.
Then, please refer to Fig. 2, form photoresist layer 102 on said metal level 101 surfaces.Said photoresist layer 102 utilizes exposure, develops and make.Be formed with opening in the said photoresist layer 102, said opening exposes part metals layer 101.The thickness range of said photoresist layer 102 is 4000～10000 dusts.
Then, please refer to Fig. 3, carry out etching technics along said opening, remove the metal level 101 that said opening exposes, until exposing said Semiconductor substrate 100, remaining metal level forms metal interconnecting wires 103.Has the opening that exposes said Semiconductor substrate 100 between the said metal interconnecting wires 103.
Then, please refer to Fig. 4, carry out cineration technics, remove said photoresist layer 102.
Then, please refer to Fig. 5, fill dielectric layer 104 in the opening between said metal interconnecting wires 103.
, publication number can find more information in being the one Chinese patent application of CN101752279A about existing metal interconnecting wires.
In reality, find, in the manufacture craft of existing metal interconnecting wires, have following problem: the thickness of photoresist layer 102 that is used for mask is bigger than normal, thereby the problem of peeling off or curling of photoresist layer takes place easily; And because photoresist layer 102 thickness are bigger than normal, utilize mask with pattern when mask is transferred to photoresist layer 102, the position of the position of the opening that said photoresist layer 102 in, forms and actual needs formation opening is inconsistent; With said photoresist layer 102 is mask, and the opening pattern that in said metal level 1021, forms is undesirable, and this has caused the critical size (CD) of said opening bigger than normal; The thickness of photoresist layer 102 is excessive, makes that said photoresist layer 102 is difficult to remove; After metal interconnecting wires 103 forms, there is cavity (void) in the dielectric layer 104 of filling between the metal interconnecting wires 103, influence insulation effect between the metal interconnecting wires.Therefore, the manufacture craft of existing metal interconnecting wires is unstable.
Summary of the invention
The problem that the present invention solves has provided a kind of manufacture method of metal interconnecting wires, has improved the stability of metal interconnecting wires manufacture craft.
For addressing the above problem, the invention provides a kind of manufacture method of metal interconnecting wires, comprising:
Semiconductor substrate is provided;
Form metal level at said semiconductor substrate surface;
Form anti-reflecting layer at said layer on surface of metal;
Form photoresist layer on said anti-reflecting layer surface, be formed with the opening that exposes said anti-reflecting layer in the said photoresist layer;
Along said opening said anti-reflecting layer of etching and metal level successively, form metal interconnecting wires;
Carry out etching along said aperture position, be formed with the groove that exposes Semiconductor substrate;
Remove the anti-reflecting layer and the photoresist layer of said metal interconnecting wires top;
In said groove, fill dielectric layer alternatively, the material of said anti-reflecting layer is an organic film.
Alternatively, the thickness range of said anti-reflecting layer is 100～3000 dusts.
Alternatively, said metal layer thickness scope is 2000～2500 dusts, and the thickness of said photoresist layer is no more than 4000 dusts.
Alternatively, the material of said metal level is aluminium or aluminium-containing alloy.
Alternatively, also comprise: the step that between said metal level and Semiconductor substrate, forms the adhesiving metal layer.
Alternatively, also comprise: the step that between said metal level and said anti-reflecting layer, forms the adhesiving metal layer.
Alternatively, the material of said adhesiving metal layer is titanium layer/titanium nitride layer or tantalum layer/tantalum nitride layer.
Alternatively, the thickness range of said adhesiving metal layer is 30～500 dusts.
Alternatively, said dielectric layer utilizes chemical vapor deposition method to make.
Compared with prior art, the present invention has the following advantages:
The present invention at first forms metal level at semiconductor substrate surface; Form anti-reflecting layer and photoresist layer at said layer on surface of metal then; Carrying out exposure technology with the design transfer in the mask to photoresist layer the time; Said anti-reflecting layer can absorb reflection ray; The difference of the size of the opening in the opening that reduces to form in the said photoresist layer and the said mask to reduce the difference with the size of the metal interconnecting wires that defines in the metal interconnecting wires of said photoresist layer making and the mask, has improved the precision and the stability of technology;
Further optimally, said metal layer thickness scope is 2000～2500 dusts, and the thickness of corresponding said photoresist layer is no more than 4000 dusts; Said metal level is in above-mentioned thickness range, and is little to the resistance influence of the metal interconnecting wires made, and; Compared with prior art; The thickness of said photoresist layer reduces greatly, and that therefore improves photoresist layer peels off (peeling) or the problem of curl (scrumming), has improved the stability of technology; Because said metal layer thickness is reduced to 2000～2500 dusts; The degree of depth of the groove between the metal interconnecting wires of corresponding formation reduces; Under the constant situation of the width of said groove, reduced the depth-to-width ratio of said groove, thereby helped the deposition of dielectric layer; Can prevent because the cavitation that the depth-to-width ratio of said groove forms in said dielectric layer greatly insulate the adjacent metal interconnection line effectively;
Further optimally; The present invention is forming the adhesiving metal layer between said Semiconductor substrate and the metal level and between said metal level and the anti-reflecting layer; Said adhesiving metal layer is used to improve the adhesiveness between said metal level and Semiconductor substrate, said metal level and the anti-reflecting layer, and can also reduce the contact resistance between metal level and the Semiconductor substrate at the adhesiving metal layer between said Semiconductor substrate and the metal level;
Further optimally, the material aluminium or the aluminium-containing alloy of said metal level are compared with copper interconnecting line, have reduced the cost of metal interconnecting wires, and have improved the stability of technology.
Description of drawings
Fig. 1～Fig. 5 is the manufacture method cross-sectional view of existing metal interconnecting wires;
Fig. 6 is the manufacture method schematic flow sheet of metal interconnecting wires of the present invention;
Fig. 7～Figure 12 is the manufacture method cross-sectional view of the metal interconnecting wires of one embodiment of the present of invention.
Embodiment
The technology of existing making metal interconnecting wires is unstable.Discover through the inventor, cause the reason of the problems referred to above to be: the metal layer thickness that is used to make metal interconnecting wires is bigger than normal.During the said metal level of etching, in order can effectively to protect the metal level that does not need etching, thereby photoresist layer also need satisfy certain thickness, thereby can guarantee the metal level that does not need etching the to remove process-induced damage that can not be etched.Therefore; Reduce the metal layer thickness that is used to make metal interconnecting wires; Can reduce the thickness of photoresist layer, thereby eliminate owing to the thickness of the photoresist layer photoresist layer that brings bigger than normal is peeled off, curled, aperture position and physical location is inconsistent, photoresist layer is difficult to problems such as removal.Reduce the metal layer thickness that is used to make metal interconnecting wires; The corresponding attenuating of the degree of depth of the opening between the metal interconnecting wires that forms; Under the constant situation of the width of said opening, reduced the depth-to-width ratio of said opening, thereby helped the filling of dielectric layer; In said opening, form the cavity in the time of can preventing cvd dielectric layer technology, improve the insulation effect between the metal interconnecting wires.
But the inventor considers, reduces to be used to make the metal layer thickness of metal interconnecting wires, can cause the resistance of interconnection line to increase, thereby increases the RC time constant of device.Along with further dwindling of the characteristic size of semiconductor device, the metal layer thickness technology of metal interconnecting wires that causes bigger than normal that is used to make metal interconnecting wires is unsettled more serious, if simply reduce metal layer thickness, possibly increase the RC time constant of device.If adopt the less copper interconnecting line of resistance value to replace existing common aluminum interconnecting; Can reduce the resistance of metal interconnecting wires; Reduce the RC time constant of device, but this will make the manufacturing cost of metal interconnecting wires improve greatly, and improve the complexity of technology.How under the situation that does not increase technology cost and process complexity, solve above-mentioned metal interconnecting wires manufacture craft problem of unstable, and the RC time constant that does not influence device is that the present invention pays close attention to.
In order to address the above problem, the inventor proposes a kind of manufacture method of metal interconnecting wires, and said method comprises:
Step S1 provides Semiconductor substrate;
Step S2 forms metal level at said semiconductor substrate surface;
Step S3 forms anti-reflecting layer at said layer on surface of metal;
Step S4 forms photoresist layer on said anti-reflecting layer surface, is formed with the opening that exposes said anti-reflecting layer in the said photoresist layer;
Step S5 along said opening said anti-reflecting layer of etching and metal level successively, forms metal interconnecting wires;
Step S6 carries out etching along said aperture position, is formed with the groove that exposes Semiconductor substrate;
Step S7 removes the anti-reflecting layer and the photoresist layer of said metal interconnecting wires top;
Step S8 fills dielectric layer in said groove.
Below in conjunction with specific embodiment technical scheme of the present invention is at length explained.
For technical scheme of the present invention is described better, please combine the manufacture method cross-sectional view of metal interconnecting wires of one embodiment of the present of invention of Fig. 7～shown in Figure 12.
At first, please refer to Fig. 7, Semiconductor substrate 200 is provided.The material of said Semiconductor substrate 200 can be silicon, germanium silicon or silicon-on-insulator.In the present embodiment, the material of said Semiconductor substrate 200 is a silicon.
Said Semiconductor substrate 200 surfaces also are formed with device layer, are formed with devices such as transistor, diode in the said device layer.
Then, on said Semiconductor substrate 200, make the first adhesiving metal layer 205, metal level 201 and the second adhesiving metal layer 206 successively.The said first adhesiving metal layer 205, metal level 201 and the second adhesiving metal layer 206 are positioned at said device layer top; Said metal level 201 is used for the metal interconnecting wires made in subsequent process steps, and said metal interconnecting wires is used for the device that forms in the said device layer is connected with external electric.
As an embodiment; The said first adhesiving metal layer 205 is used to improve the adhesiveness between said metal level 201 and the Semiconductor substrate 200; Reduce the contact resistance between said metal level 201 and the Semiconductor substrate 200, the thickness range of the said first adhesiving metal layer 205 is 30～500 dusts.In the present embodiment, the material of the said first adhesiving metal layer 205 is titanium layer/titanium nitride layer, and said titanium nitride layer is positioned on the said Semiconductor substrate 200, and said titanium layer is positioned on the said titanium nitride layer, and said metal level 201 is positioned on the said titanium layer.In other embodiment, the material of the said first adhesiving metal layer 205 can also be tantalum layer/tantalum nitride layer.
The said second adhesiving metal layer 206 is used to improve the anti-reflecting layer of said metal level 201 and follow-up formation and the adhesiveness between the first adhesiving metal layer 205.The thickness range of the said second adhesiving metal layer 206 is 30～500 dusts.The material of the said second adhesiving metal layer 206 is titanium layer/titanium nitride layer or tantalum layer/tantalum nitride layer.Wherein said titanium layer is positioned on the said metal level 201, and said titanium nitride layer is positioned on the said titanium layer, and said anti-reflecting layer is positioned on the said titanium nitride layer; Or said tantalum layer is positioned on the said metal level 201, and said tantalum nitride layer is positioned on the said tantalum layer, and the anti-reflecting layer of said follow-up formation is positioned on the said tantalum nitride layer.
The material of said metal level 201 is aluminium or aluminium-containing alloy, and this metal level 201 is used for making metal interconnecting wires in follow-up step.Compare as metal interconnecting wires with utilizing copper, it is low to utilize the metal level of aluminium or aluminium-containing alloy to make the cost of metal interconnecting wires, and technology is simple.As preferred embodiment, the material of said metal level 201 is an albronze, and wherein the content of copper is 5%.Utilize albronze as metal level, can prevent junction spiking.
The thickness range of said metal level 201 is 2000～2500 dusts.Because said metal level 201 will be removed unwanted part through etching technics; Remainder forms metal interconnecting wires; In order to protect the metal level (this part promptly forms metal interconnecting wires behind etching technics) that need not carry out etching, need form photoresist layer at the described layer on surface of metal that need not carry out etching.The thickness of photoresist layer depends on the thickness of metal level 201, and the thickness of this metal level 201 is big more, and the thickness of photoresist layer is big more.Because the thickness range of this present invention's metal level 201 is 2000～2500 dusts; In above-mentioned thickness range; The thickness of the required photoresist layer that is used to protect is no more than 4000 dusts; Thereby compare with the photoresist layer of existing 4000～10000 dusts, the present invention greatly reduces the thickness of photoresist layer.
Need to prove; Though comparing to some extent with the metal layer thickness of prior art, the thickness of said metal level 201 reduces, in the scope of said thickness 2000～2500 dusts, little to the resistance influence of the metal interconnecting wires of final making; In the scope that technology allows; Can obviously not increase the resistance of the metal interconnecting wires of final making, thus less to the RC time constant influence of device, can ignore basically.
Then, please refer to Fig. 8, form anti-reflecting layer 207 on the said second adhesiving metal layer 206 surface.Said anti-reflecting layer 207 materials are organic film, and its thickness range is 100～3000 dusts.Carrying out exposure technology with the design transfer in the mask to photoresist layer the time; Said anti-reflecting layer 207 can absorb reflection ray; Reduce the difference of the size of interior opening that forms of said photoresist layer and the opening in the said mask; With the difference of the size of the metal interconnecting wires that defines in the metal interconnecting wires that reduces to make and the mask, improved the precision and the stability of technology with said photoresist layer.
Then, please refer to Fig. 9, form photoresist layer 202, be formed with the opening that exposes said anti-reflecting layer 207 in the said photoresist layer 202 on said anti-reflecting layer 207 surfaces.Said photoresist layer 202 utilizes spin coating or spraying coating process to make, and utilize exposure, developing process with the figure transfer on the mask in photoresist layer 202, thereby in said photoresist layer the said opening that exposes anti-reflecting layer 207 of formation in 202.Because the below is provided with anti-reflecting layer 207, when exposure technology was carried out, said anti-reflecting layer 207 can reflection ray, and the difference of the size of the opening that the opening that reduces to form in the said photoresist layer and said mask are interior has improved the precision of exposure technology.
The thickness of said photoresist layer 202 is no more than 4000 dusts.In above-mentioned thickness range, the thickness of said photoresist layer 202 is even, difficult peeling off or the phenomenon of curling, and utilize etching technics to remove easily, do not have residual problem.
Then; Please refer to Figure 10; Along the opening in the said photoresist layer 202, the said anti-reflecting layer of etching 207, second contact metal layer 206, metal level 201 and first contact metal layer 205 successively are until exposing opening lower semiconductor substrate 200; In said second contact metal layer 206, metal level 201 and remaining first contact metal layer 205, form groove, the remaining metal level 201 of said groove both sides is as metal interconnecting wires.
Because said metal level 201 thickness compared with prior art reduce greatly, thereby under the constant situation of width, reduced the difficulty of etching technics.
Then, please refer to Figure 11, remove said photoresist layer and anti-reflecting layer.The removal method of said photoresist layer and anti-reflecting layer can be dry etching or wet-etching technology.In the present embodiment, said photoresist layer and anti-reflecting layer utilize dry etch process.Said dry etch process is utilized said photoresist layer of plasma bombardment and anti-reflecting layer surface, converts said photoresist layer or anti-reflecting layer into the gas removal.
Then, please refer to Figure 12, carry out chemical vapor deposition method, form dielectric layer 208 in the groove between said second contact metal layer 206, metal level 201 and first contact metal layer 205.Said dielectric layer 208 is used for the electrical insulation between the adjacent metal layer 201.The material of said dielectric layer 208 is silica, silicon nitride, silicon nitride or silicon oxynitride.Because the degree of depth of said groove equals the thickness sum of second contact metal layer 206, metal level 201 and first contact metal layer 205; The thickness of said second contact metal layer 206 and first contact metal layer 205 is less; The thickness range of said metal level 201 is 2000～2500 dusts, and therefore said second contact metal layer 206, metal level 201 and first contact metal layer, 205 sums compared with prior art also reduce greatly, and therefore the degree of depth of said groove reduces greatly; Under the constant situation of the width of groove; The depth-to-width ratio of said groove reduces, thereby more helps the carrying out of chemical vapor deposition method, prevents to form the cavity in the said dielectric layer 208.
To sum up; The manufacture method of metal interconnecting wires provided by the invention; The present invention at first forms metal level at semiconductor substrate surface, forms anti-reflecting layer and photoresist layer at said layer on surface of metal then, is carrying out exposure technology with the design transfer in the mask to photoresist layer the time; Said anti-reflecting layer can absorb reflection ray; The difference of the size of the opening in the opening that reduces to form in the said photoresist layer and the said mask to reduce the difference with the size of the metal interconnecting wires that defines in the metal interconnecting wires of said photoresist layer making and the mask, has improved the precision and the stability of technology; In a preferred embodiment of the invention, said metal layer thickness scope is 2000～2500 dusts, and the thickness of corresponding said photoresist layer is no more than 4000 dusts; Said metal level is in above-mentioned thickness range, and is little to the resistance influence of the metal interconnecting wires made, and; Compared with prior art; The thickness of said photoresist layer reduces greatly, and that therefore improves photoresist layer peels off (peeling) or the problem of curl (scrumming), has improved the stability of technology; Because said metal layer thickness is reduced to 2000～2500 dusts; The degree of depth of the groove between the metal interconnecting wires of corresponding formation reduces; Under the constant situation of the width of said groove, reduced the depth-to-width ratio of said groove, thereby helped the deposition of dielectric layer; Can prevent because the cavitation that the depth-to-width ratio of said groove forms in said dielectric layer greatly insulate the adjacent metal interconnection line effectively; The present invention is also forming the adhesiving metal layer between said Semiconductor substrate and the metal level and between said metal level and the anti-reflecting layer; Said adhesiving metal layer is used to improve the adhesiveness between said metal level and Semiconductor substrate, said metal level and the anti-reflecting layer, and can also reduce the contact resistance between metal level and the Semiconductor substrate at the adhesiving metal layer between said Semiconductor substrate and the metal level;
Further optimally, the material aluminium or the aluminium-containing alloy of said metal level are compared with copper interconnecting line, have reduced the cost of metal interconnecting wires, and have improved the stability of technology.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. the manufacture method of a metal interconnecting wires is characterized in that, comprising:
Semiconductor substrate is provided;
Form metal level at said semiconductor substrate surface;
Form anti-reflecting layer at said layer on surface of metal;
Form photoresist layer on said anti-reflecting layer surface, be formed with the opening that exposes said anti-reflecting layer in the said photoresist layer;
Along said opening said anti-reflecting layer of etching and metal level successively, form metal interconnecting wires;
Carry out etching along said aperture position, be formed with the groove that exposes Semiconductor substrate;
Remove the anti-reflecting layer and the photoresist layer of said metal interconnecting wires top;
In said groove, fill dielectric layer.
2. the manufacture method of metal interconnecting wires as claimed in claim 1 is characterized in that, the material of said anti-reflecting layer is an organic film.
3. the manufacture method of metal interconnecting wires as claimed in claim 1 is characterized in that, the thickness range of said anti-reflecting layer is 100～3000 dusts.
4. the manufacture method of metal interconnecting wires as claimed in claim 1 is characterized in that, said metal layer thickness scope is 2000～2500 dusts, and the thickness of said photoresist layer is no more than 4000 dusts.
5. the manufacture method of metal interconnecting wires as claimed in claim 1 is characterized in that, the material of said metal level is aluminium or aluminium-containing alloy.
6. the manufacture method of metal interconnecting wires as claimed in claim 1 is characterized in that, also comprises: the step that between said metal level and Semiconductor substrate, forms the adhesiving metal layer.
7. the manufacture method of metal interconnecting wires as claimed in claim 1 is characterized in that, also comprises: the step that between said metal level and said anti-reflecting layer, forms the adhesiving metal layer.
8. like the manufacture method of claim 6 or 7 described metal interconnecting wires, it is characterized in that the material of said adhesiving metal layer is titanium layer/titanium nitride layer or tantalum layer/tantalum nitride layer.
9. like the manufacture method of claim 6 or 7 described metal interconnecting wires, it is characterized in that the thickness range of said adhesiving metal layer is 30～500 dusts.
10. the manufacture method of metal interconnecting wires as claimed in claim 1 is characterized in that, said dielectric layer utilizes chemical vapor deposition method to make.
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| CN2010106025663A CN102569168A (en) | 2010-12-23 | 2010-12-23 | Manufacturing method of metal interconnection line |
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| CN2010106025663A CN102569168A (en) | 2010-12-23 | 2010-12-23 | Manufacturing method of metal interconnection line |
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| CN103730412A (en) * | 2014-01-07 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Metal interconnecting wire formation method |
| CN104979270A (en) * | 2014-04-03 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure formation method |
| CN105514030A (en) * | 2016-01-21 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | Forming method of semiconductor structure |
| CN110931373A (en) * | 2019-12-11 | 2020-03-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
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| CN110931373A (en) * | 2019-12-11 | 2020-03-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
| CN110931373B (en) * | 2019-12-11 | 2021-11-19 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
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Application publication date: 20120711 |