CN101477977A - Wafer stage encapsulation structure and lead pad electric signal leading process - Google Patents
Wafer stage encapsulation structure and lead pad electric signal leading process Download PDFInfo
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- CN101477977A CN101477977A CN 200910028182 CN200910028182A CN101477977A CN 101477977 A CN101477977 A CN 101477977A CN 200910028182 CN200910028182 CN 200910028182 CN 200910028182 A CN200910028182 A CN 200910028182A CN 101477977 A CN101477977 A CN 101477977A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention provides an electrical signal leading-out method of the lead bonding pad of a wafer-level package structural device by adopting the multi-step and precision depth control wafer dicing technology. The method is characterized in that the wafer-level package structure comprises an upper layer structure, a middle layer structure and a lower layer support, wherein, a bonding ring is arranged on the periphery of the middle layer structure, the lead bonding pad of a chip structure is distributed on the lower layer support, and the lead bonding pad is positioned on the outer side of the bonding ring; the upper layer structure, the middle layer structure and the lower layer support of the package structure are bonded as a whole body through an MEMS key by adopting the bonding ring; and multi-step dicing and breaking are performed to a wafer, so as to ensure that a signal lead bonding pad is exposed, and chips and a follow-up circuit are mutually connected by adopting the lead bonding technology. Through reasonable design of the position of the chip lead, the method carries out double-surface, multi-step, controlled depth and accurate positioning dicing the wafer, ensures that the lead bonding pad is directly exposed, and realizes the chip interconnection by utilizing the lead bonding technology. The method has the advantages that the unit structures inside the chips are protected, the yield from the wafer level to the independent chip is greatly improved, the package volume of the device is reduced, and simultaneously the interconnection between chips and leads is realized without the complex etching technologies, such as flip chip bonding, through holes and the like.
Description
Technical field
The present invention relates to a kind of wafer-level package structure and lead pad electric signal leading process thereof, particularly be positioned at the wafer level packaging dress device electric signal leading process of chip structure periphery at lead pad.
Background technology
A kind of interconnection technique is a face-down bonding technique in the prior art.Face-down bonding technique is that the I/O end at chip utilizes planar technique to make the solder bump soldered ball, chip is faced down, directly be mounted on the substrate, utilize reflow soldering process to make between chip soldered ball and the substrate pads and form solder joint, realize electricity, heat, the mechanical connection of chip and substrate.The shortcoming of this technology is that there are thermal mismatching in the thermal coefficient of expansion of chip and the thermal coefficient of expansion of base plate, and therefore when chip operation, thermal expansion mismatch is serious.Under thermal cycle loads, produce very big periodicity plastic deformation in the solder joint, germinating crack and expansion make the very fast fatigue failure of solder joint.
Another kind of technology is a metal column interconnection parallel-plate structure.Tow sides at silicon chip respectively have one deck ceramic copper-clad plate parallel to each other (DBC) up and down.Be etched with corresponding circuit on the DBC plate in advance.Be welded between the bottom surface of silicon chip on the DBC plate, and the electrode in silicon chip front is to draw by the metal column of Direct Bonding, is electrically connected, promptly finished between the silicon chip and the interconnection between the DBC plate up and down by metal column with last DBC plate formation.This technology should be considered the heat coupling between the different materials, considers the technology coupling between the different metal post again.Therefore the interconnection process based on this technology is quite complicated.
A kind of technology that also has is the interconnection (TSV) that penetrates silicon chip.Form little through hole and realize metallization in the hole by position suitable on silicon or silicon wafer, form the electrical interconnection on chip two sides.Such electrical connection can be finished stacked die by the technology that is similar to flipchip-bumped and directly interconnect.This technology relates to many-sided process detail, except the making of silicon through hole itself, also will consider the realization of conductive interconnection line in the through hole and the formation of conductive interconnection line and silicon substrate electric insulation, so its complex manufacturing technology, and technology realizes that difficulty is big.
It is Wire Bonding Technology that a kind of technology is arranged again, and this technology adopts presses the method for spun gold to realize that chip is to the interconnection between substrate or the lead frame.The characteristics of this technology are that technology is mature and stable relatively, easily realize.But some is contained the chip of movable structure and specific (special) requirements, directly utilize this technology, be unfavorable for the protection of chip structure.
Summary of the invention
Purpose of the present invention is intended to overcome above-mentioned existing defective, the wafer level packaging device electric signal leading process that a kind of lead pad is positioned at the chip structure periphery is proposed, utilize depth controlled, pinpoint multistep footpath scribing technology to carry out two-sided scribing along the scribing mark of chip bonding ring periphery and chip lead pad periphery respectively, accurately control the scribing degree of depth simultaneously, make blade stop downward cutting at the certain position place of superstructure and lower layer support substrate, avoided that current enter chip internal in the scribing process.Utilize the sliver technology at last, the chip signal lead pad is exposed, technologies such as utilization lead-in wire bonding realize the interconnection of chip and subsequent conditioning circuit.This method also is applicable to the metal interconnected of stacked device architecture.
Technical solution of the present invention: wafer-level package structure is characterized in that it being to comprise superstructure, middle level structure and lower layer support; Wherein the middle level structure is with a bonding ring outward, is distributed with the lead pad of chip structure on the lower layer support, and described lead pad is positioned at the outside of bonding ring; The superstructure of encapsulating structure, middle level structure and lower layer support utilize the bonding ring to be bonded to one by MEMS; Disk is carried out multistep footpath scribing, sliver, the signal lead pad is exposed, utilize wire bonding method chip and subsequent conditioning circuit interconnection.
The lead pad electric signal leading process of wafer-level package structure is characterized in that this method comprises the steps:
1) on described disk lower layer support layer, pastes glued membrane;
2) accurately locate from top to bottom at the multistep of the superstructure upper edge of described disk chip superstructure footpath scribing mark, the degree of depth is accurately controlled, multistep footpath scribing and make blade stop downward cutting in 30 μ m-50 μ m places from bottom to top in superstructure, makes last remainder connection;
3) glued membrane on the described disk lower layer support is removed, on superstructure, paste glued membrane;
4) the scribing mark on the chip lower layer support material of the lower layer support upper edge of described disk accurately locate from top to bottom, the accurate controlled scribing of the degree of depth, and make blade stop downward cutting in depths, 30 μ m-50 μ m position from bottom to top in the lower layer support structure, last remainder is connected;
5) glued membrane on the described disk superstructure is removed;
Above-mentioned described sequence of process steps also can be:
1) on described disk superstructure, pastes glued membrane;
2) the scribing mark on the chip lower layer support material of the lower layer support layer upper edge of described disk carries out scribing, and makes blade stop downward cutting in 30-50 μ m position from bottom to top in the lower layer support structure, and last remainder is connected;
3) glued membrane on the described disk superstructure is removed, on described disk lower layer support layer, paste glued membrane;
4) the multistep footpath scribing mark in the superstructure upper edge of described disk chip superstructure carries out multistep footpath scribing and makes blade stop downward cutting in 30-50 μ m place from bottom to top in superstructure, and last remainder is connected;
5) glued membrane on the described disk lower layer support layer is removed;
6) described disk sliver is become separate unit, the signal lead pad is exposed;
7) described chip adopts lead-in wire bonding mode and subsequent conditioning circuit to interconnect.
Advantage of the present invention: the lead pad electric signal leading process of wafer-level package structure provided by the invention has reduced technology and has realized difficulty, has made things convenient for the wire bonds of chip and subsequent conditioning circuit.Compare with existing lead-in wire bonding interconnection technique; the present invention is by the reasonable distribution design to chip structure; contain chip unit movable structure, that need avoid the steam contact at some; adopt multistep footpath, depth controlled, pinpoint scribing and sliver technology; protected the chip internal movable structure; avoided of the damage of follow-up manufacture crafts such as traditional scribing, encapsulation, improved process yield, further reduced the encapsulation volume of device simultaneously device architecture.
Description of drawings
Accompanying drawing 1 is the wafer-level package structure chip unit.
Accompanying drawing 2 is enlarged diagrams of disk group.
Accompanying drawing 3 is scribing enlarged diagrams of disk group.
Accompanying drawing 4 is wafer level packaging chip and circuit interconnection schematic diagram.
Among the figure 1 is middle level structure, the 2nd, bonding ring, the 3rd, lead pad, the 4th, lower layer support, the 5th, superstructure, the 6th, micro groove, the 7th, cutter, the 8th, the scribing alignment mark, the 9th of superstructure, the scribing alignment mark, the 10th of lower layer support, spun gold.
Embodiment
Below be embodiment provided by the invention, specify in conjunction with Fig. 1, Fig. 2, Fig. 3.
Described superstructure material is a glass, described middle level structural material is a silicon, described lower layer support material is a glass, and the scribing correspondence position is made multistep footpath scribing mark on described superstructure material, and the scribing correspondence position is made the scribing mark on described lower layer support material.
Described superstructure material is a silicon, described middle level structural material is a silicon, described lower layer support material is a glass, and the scribing correspondence position is made multistep footpath scribing mark on described superstructure material, and the scribing correspondence position is made the scribing mark on described lower layer support material.
Multistep on described superstructure material footpath scribing mark is positioned at position directly over the chip bonding ring peripheral leads pad, and the scribing mark on the described lower layer support material is positioned in the middle of the adjacent bonding ring.
Described bonding ring bottom is etched with a micro groove, and the signal metal lead-in wire on the described chip lower layer support is by this micro groove and the interconnection of chip middle level inside configuration.Described signal metal lead-in wire height≤4 μ m, the height of described micro groove is slightly larger than the height of metal lead wire, and width is slightly larger than the width of metal lead wire.
Described disk is carried out two-sided, depth controlled, accurately locatees multistep footpath scribing.
This method comprises the steps:
1) on described disk lower layer support layer, pastes glued membrane;
2) accurately locate from top to bottom at the multistep of the superstructure upper edge of described disk chip superstructure footpath scribing mark, the degree of depth is accurately controlled, multistep footpath scribing and make blade stop downward cutting in 50 μ m places from bottom to top in superstructure, makes last remainder connection;
3) glued membrane on the described disk lower layer support is removed, on superstructure, paste glued membrane;
4) the scribing mark on the chip lower layer support material of the lower layer support upper edge of described disk accurately locate from top to bottom, the accurate controlled scribing of the degree of depth, and make blade stop downward cutting in depths, 50 μ m position from bottom to top in the lower layer support structure, last remainder is connected;
5) glued membrane on the described disk superstructure is removed;
Above-mentioned described sequence of process steps also can be:
1) on described disk superstructure, pastes glued membrane;
2) the scribing mark on the chip lower layer support material of the lower layer support layer upper edge of described disk carries out scribing, and makes blade stop downward cutting in 30-50 μ m position from bottom to top in the lower layer support structure, and last remainder is connected;
3) glued membrane on the described disk superstructure is removed, on described disk lower layer support layer, paste glued membrane;
4) the multistep footpath scribing mark in the superstructure upper edge of described disk chip superstructure carries out multistep footpath scribing and makes blade stop downward cutting in 30-50 μ m place from bottom to top in superstructure, and last remainder is connected;
5) glued membrane on the described disk lower layer support layer is removed;
6) described disk sliver is become separate unit, the signal lead pad is exposed;
Described chip unit adopts lead-in wire bonding mode and subsequent conditioning circuit to interconnect.
Described blade adopts the thick resinoid bond cutting blade of 300 μ m, makes blade stop downward cutting in 30 μ m-50 μ m places from bottom to top in described superstructure and lower layer support structure respectively.
The present invention has realized that in conjunction with two-sided, depth controlled, pinpoint multistep footpath scribing technology the lead pad electric signal of wafer-level package structure is drawn, and has protected chip structure, has improved process yield, and technology is simple, easily realization.This method also is suitable for the metal interconnected of stacked device architecture simultaneously.
Two-sided, the depth controlled of wafer-level package structure of the present invention, the footpath scribing of pinpoint multistep, concrete implementation step is as follows:
Described disk is placed on the horizontal table top of smooth cleaning, lower layer support 4 material face up, the one side that glued membrane is had viscosity covers on lower layer support 4 materials gently.Evenly heating is attached on the glued membrane disk securely, and the vibration that produces when reducing scribing is to the influence of chip structure.
Select the thick resinoid bond cutting blade scribing of 300 μ m for use, the disk that posts glued membrane is loaded on the scribing machine, with the aligning scribing mark 8 on the cutter 7 aligning superstructures, as shown in Figure 2, at a plurality of different scribing step footpaths, accurate scribing parameter is set, make blade stop downward cutting in 50 μ m degree of depth places from bottom to top in superstructure, begin to carry out scribing, as shown in Figure 3.
After finishing the scribing of superstructure, the glued membrane on lower layer support 4 materials is taken off gently water stain on the drying wafer.Described disk is placed on the horizontal table top of smooth cleaning, superstructure 5 is faced up, the one side that glued membrane is had viscosity covers on upper strata structure 5 materials gently.Evenly heating is attached on the glued membrane disk securely.
The disk that posts glued membrane is loaded on the scribing machine, with the aligning scribing mark 9 on the cutter 7 aligning lower layer support, as shown in Figure 2, accurate scribing parameter is set, make blade stop downward cutting in depths, 50 μ m position from bottom to top, begin to carry out scribing, as shown in Figure 3 in the lower layer support structure.
After finishing the scribing of lower layer support material, glued membrane is taken off gently water stain on the drying wafer.Utilize aid to be pressed in gently and do not draw on the saturating scribe line,, described disk can be separated into individual chips one by one, as shown in Figure 1 according to naturally cleaved characteristic.Chip internal structure has obtained effective protection, and lead pad is exposed to the chip outside, has made things convenient for further wire bond package, has reached the purpose of wafer level packaging.
After finishing two-sided, depth controlled, the footpath scribing of pinpoint multistep and sliver technology, chip unit independently one by one, it is metal interconnected to utilize lead-in wire bonding mode to adopt thermocompression bonding that chip lead pad and subsequent conditioning circuit are carried out, as shown in Figure 4.
Claims (7)
1, wafer-level package structure is characterized in that comprising superstructure, middle level structure and lower layer support; Wherein the middle level structure is with a bonding ring outward, is distributed with the lead pad of chip structure on the lower layer support, and described lead pad is positioned at the outside of bonding ring; The superstructure of encapsulating structure, middle level structure and lower layer support utilize the bonding ring to be bonded to one by MEMS; Disk is carried out multistep footpath scribing, sliver, the signal lead pad is exposed, utilize wire bonding method chip and subsequent conditioning circuit interconnection.
2, wafer-level package structure according to claim 1, it is characterized in that described superstructure material is a glass, described middle level structural material is a silicon, described lower layer support material is a glass, the scribing correspondence position is made multistep footpath scribing mark on described superstructure material, and the scribing correspondence position is made the scribing mark on described lower layer support material.
3, wafer-level package structure according to claim 1, it is characterized in that described superstructure material is a silicon, described middle level structural material is a silicon, described lower layer support material is a glass, the scribing correspondence position is made multistep footpath scribing mark on described superstructure material, and the scribing correspondence position is made the scribing mark on described lower layer support material.
4, wafer-level package structure according to claim 2, it is characterized in that multistep footpath scribing mark on the described superstructure material is positioned at position directly over the chip bonding ring peripheral leads pad, the scribing mark on the described lower layer support material is positioned in the middle of the adjacent bonding ring.
5, wafer-level package structure according to claim 1, it is characterized in that described bonding ring bottom is etched with a micro groove, signal metal lead-in wire on the described chip lower layer support is by this micro groove and the interconnection of chip middle level inside configuration, described signal metal lead-in wire height≤4 μ m, the height of described micro groove is greater than the height of metal lead wire, and width is greater than the width of metal lead wire.
6, the lead pad electric signal leading process of wafer-level package structure is characterized in that this method comprises the steps:
1) on described disk lower layer support layer, pastes glued membrane;
2) the multistep footpath scribing mark in the superstructure upper edge of described disk chip superstructure carries out multistep footpath scribing and makes blade stop downward cutting in 30-50 μ m place from bottom to top in superstructure, and last remainder is connected;
3) glued membrane on the described disk lower layer support layer is removed, on superstructure, paste glued membrane;
4) the scribing mark on the chip lower layer support material of the lower layer support layer upper edge of described disk carries out scribing, and makes blade stop downward cutting in 30-50 μ m position from bottom to top in the lower layer support structure, and last remainder is connected;
5) glued membrane on the described disk superstructure layer is removed;
Above-mentioned described sequence of process steps also can be:
1) on described disk superstructure, pastes glued membrane;
2) the scribing mark on the chip lower layer support material of the lower layer support layer upper edge of described disk carries out scribing, and makes blade stop downward cutting in 30-50 μ m position from bottom to top in the lower layer support structure, and last remainder is connected;
3) glued membrane on the described disk superstructure is removed, on described disk lower layer support layer, paste glued membrane;
4) the multistep footpath scribing mark in the superstructure upper edge of described disk chip superstructure carries out multistep footpath scribing and makes blade stop downward cutting in 30-50 μ m place from bottom to top in superstructure, and last remainder is connected;
5) glued membrane on the described disk lower layer support layer is removed;
6) described disk sliver is become separate unit, the signal lead pad is exposed;
7) described chip adopts lead-in wire bonding mode and subsequent conditioning circuit to interconnect.
7, the lead pad electric signal leading process of wafer-level package structure according to claim 6, it is characterized in that the resinoid bond cutting blade scribing of selecting for use 300 μ m thick making blade stop downward cutting in 30 μ m-50 μ m places in described superstructure and lower layer support structure respectively from bottom to top.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910028182 CN101477977B (en) | 2009-01-20 | 2009-01-20 | Wafer stage encapsulation structure and lead pad electric signal leading process |
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| CN 200910028182 CN101477977B (en) | 2009-01-20 | 2009-01-20 | Wafer stage encapsulation structure and lead pad electric signal leading process |
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| CN101477977A true CN101477977A (en) | 2009-07-08 |
| CN101477977B CN101477977B (en) | 2011-01-19 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012040873A1 (en) * | 2010-09-29 | 2012-04-05 | Nxp B.V. | Singulation of ic packages |
| CN104332463A (en) * | 2013-07-12 | 2015-02-04 | 英飞凌科技奥地利有限公司 | Multichip device |
| CN104986720A (en) * | 2015-05-27 | 2015-10-21 | 重庆大学 | MEMS wafer level vacuum packaging structure and method |
| CN107814352A (en) * | 2017-11-03 | 2018-03-20 | 苏州希美微纳系统有限公司 | Wet etching packaging structure and its dicing method applied to RF MEMS |
-
2009
- 2009-01-20 CN CN 200910028182 patent/CN101477977B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012040873A1 (en) * | 2010-09-29 | 2012-04-05 | Nxp B.V. | Singulation of ic packages |
| US8809121B2 (en) | 2010-09-29 | 2014-08-19 | Nxp B.V. | Singulation of IC packages |
| CN104332463A (en) * | 2013-07-12 | 2015-02-04 | 英飞凌科技奥地利有限公司 | Multichip device |
| CN104332463B (en) * | 2013-07-12 | 2017-07-18 | 英飞凌科技奥地利有限公司 | Multichip device |
| CN104986720A (en) * | 2015-05-27 | 2015-10-21 | 重庆大学 | MEMS wafer level vacuum packaging structure and method |
| CN104986720B (en) * | 2015-05-27 | 2016-08-17 | 重庆大学 | MEMS wafer-level vacuum package structure and method |
| CN107814352A (en) * | 2017-11-03 | 2018-03-20 | 苏州希美微纳系统有限公司 | Wet etching packaging structure and its dicing method applied to RF MEMS |
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| Publication number | Publication date |
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| CN101477977B (en) | 2011-01-19 |
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