CN101471318A - Lga基板及其制造方法 - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 104
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 100
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 52
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 50
- 239000010931 gold Substances 0.000 claims abstract description 38
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052737 gold Inorganic materials 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910000679 solder Inorganic materials 0.000 claims abstract description 14
- 239000003989 dielectric material Substances 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims description 57
- 238000000034 method Methods 0.000 claims description 45
- 238000007772 electroless plating Methods 0.000 claims description 28
- 238000007654 immersion Methods 0.000 claims description 21
- 238000005516 engineering process Methods 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 230000008901 benefit Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000006479 redox reaction Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- MUJIDPITZJWBSW-UHFFFAOYSA-N palladium(2+) Chemical compound [Pd+2] MUJIDPITZJWBSW-UHFFFAOYSA-N 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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Abstract
一种LGA基板,包括:内核(110),其上形成有内置电介质材料(150)、至少一个金属层(125)和阻焊剂(155);电连接到所述金属层的导电平面栅格阵列焊盘(120);所述导电平面栅格阵列焊盘上的镍层(121);所述镍层上的钯层(122)以及所述钯层上的金层(123)。
Description
技术领域
本发明所公开的实施例总体上涉及用于微电子器件的平面栅格阵列(LGA),更具体而言涉及用于LGA基板的表面终饰(surface finish)材料。
背景技术
很多微电子系统都包括必须与印刷电路板或微电子系统的另一部件电集成的微处理器或其他集成电路器件。这种系统可以利用接收集成电路器件的插座接口并与其形成电连接。存在各种插座类型,包括基于诸如球栅阵列(BGA)、针栅阵列(PGA)和平面栅格阵列(LGA)架构的插座。
BGA和PGA封装分别使用焊球和插针来形成与印刷电路板之间的连接。相反,LGA封装在基板上没有这样的部件;取代插针或焊球的是焊盘,焊盘常常是包括铜的金属堆积体(stackup)上的镀金材料,其接触印刷电路板上安装的插座中的导电部件(即LGA插座插针)。为了降低LGA单元和插座之间的接触电阻,利用包括镍层和厚金层的表面终饰来处理LGA基板。目前,一些LGA基板使用无电镀镍-浸渍金-无电镀金(ENIG+EG)表面终饰,其提供了足以适当降低插座和封装间的接触电阻的金层。然而,ENIG+EG表面终饰的问题在于成本高,并且,根据焊接接缝中的金属堆积情况,在第一级互连(FLI)电迁移边缘测试中可能会遇到平均无故障时间(MTTF)短的问题。
附图说明
结合附图阅读以下详细说明将更好地理解所公开的实施例,在附图中:
图1为根据本发明实施例的LGA基板的侧视图;
图2为示出了根据本发明实施例的制造LGA基板的方法的流程图;以及
图3为示出了根据本发明的不同的实施例的制造LGA基板的方法的流程图。
为了说明的简单清晰,附图例示了构造的一般方式,可以省略对公知特征和技术的描述和细节,以免不必要地使本发明所述的实施例模糊不清。此外,附图中的元件未必是按比例绘制的。例如,图中一些元件的尺度可能被相对于其他元件放大,以帮助改善对本发明的实施例的理解。不同附图中的相同附图标记表示相同的元件。
说明书和权利要求中的术语“第一”、“第二”、“第三”、“第四”等(如果有的话)用于区分类似元件,而未必用于描述特定的顺序或时间上的次序。要理解的是,在适当环境下这样使用的术语是可以互换的,因此,这里所述的本发明的实施例(例如)可以按不同于本文所述或所示的顺序工作。类似地,如果这里所述的方法包括一系列步骤,本文给出的这些步骤的次序未必是可以执行这些步骤的唯一次序,可以省略特定的所述步骤和/或可以向该方法添加这里未描述的一些其他步骤。此外,术语“包括”、“包含”、“具有”及其任何变形意在覆盖非排他性的内涵,因此,包括一系列要素的过程、方法、物品或设备未必受限于那些要素,而是可以包括未明确列出或不固有地属于这种过程、方法、物品或设备的其他要素。
说明书和权利要求中的术语“左”、“右”、“前”、“后”、“顶”、“底”、“上”、“下”等(如果有的话)用于描述性的目的,未必用来描述永久性的相对位置。要理解的是,在适当环境下这样使用的术语是可以互换的,因此,这里所述的本发明的实施例(例如)可以按不同于本文所述或所示的取向工作。如本文所使用的,术语“耦合”被定义为以电气或非电气方式直接或间接地连接。本文描述为彼此“相邻”的物体可以彼此物理接触,彼此靠得很近或位于彼此相同的大致区域,只要适合于使用该短语的语境。本文中出现“在一个实施例中”这一短语未必全部是指同一实施例。
具体实施方式
在本发明的一个实施例中,LGA基板包括:内核,其上形成有内置(build-up)电介质材料、至少一个金属层和阻焊剂;电连接到金属线的导电平面栅格阵列焊盘;导电平面栅格阵列焊盘上的镍(Ni)层;镍层上的钯(Pd)层以及钯层上的金(Au)层。
利用NiPdAu替代当前LGA基板上的ENIG+EG表面终饰增大了基板中某些临界功率传输网的最大电流输运能力(取决于冶金堆积),同时由于从基板制造工艺中消除了厚而昂贵的EG层而实现了单位成本显著降低。根据冶金堆积情况,FLI电迁移MTTF也可能得到显著改善。
现在参考附图,图1为根据本发明实施例的LGA基板100的侧视图。如图1所示,LGA基板100包括:内核110,其上形成有内置电介质材料150、金属层125以及阻焊剂155;电连接到金属层125的导电平面栅格阵列焊盘120(例如铜连接盘等);导电平面栅格阵列焊盘120上的镍层121;镍层121上的钯层122以及钯层122上的金层123。
LGA基板100将具有导电(例如铜)柱171的管芯170连接到具有接触金层123的插针181的插座180。(在未示出的实施例中,由凸点金属化下(UBM)焊料等取代导电柱171。)焊料凸点175将管芯170电连接到可控塌陷芯片连接(C4)焊盘130,该可控塌陷芯片连接(C4)焊盘130电连接到金属层125。内核110包含被铜或其他导电材料的外壳围绕的插塞140,将C4焊盘130连接到平面栅格阵列焊盘120。如平面栅格阵列焊盘120那样,C4焊盘130涂布有镍层121、镍层121上的钯层122以及钯层122上的金层123。这里应当指出,在至少一个实施例中,NiPdAu表面终饰叠层中的每一单个金属层都是同时形成于平面栅格阵列焊盘120和C4焊盘130上的;因此在图1中的LGA基板100的那些部件上对Ni、Pd和Au层使用了相同的附图标记。LGA基板100还包括底填材料160。
在一个实施例中,镍层121具有介于大约5微米和大约10微米之间的厚度。在同一个或另一个实施例中,钯层122具有介于大约0.01微米和大约0.1微米之间的厚度,在同一个或另一个实施例中,金层123具有介于大约0.01微米和大约0.5微米之间的厚度。
图2为示出了根据本发明实施例的制造LGA基板的方法200的流程图。方法200的步骤210是提供其上形成有内置电介质材料、至少一个金属层和阻焊剂的内核。例如,该内核可以类似于图1所示的内核110。作为另一个范例,内置电介质材料、金属层和阻焊剂可以分别类似于内置电介质材料150、金属层125和阻焊剂155,它们都在图1中示出。
方法200的步骤220是将导电平面栅格阵列焊盘电连接到金属层。例如,平面栅格阵列焊盘可以类似于图1所示的平面栅格阵列焊盘120。
方法200的步骤230是在导电平面栅格阵列焊盘上形成镍层。例如,镍层可以类似于图1中示出的镍层121。在一个实施例中,步骤230包括利用无电镀工艺镀覆镍层。
方法200的步骤240是在镍层上形成钯层。例如,钯层可以类似于图1中示出的钯层122。在一个实施例中,步骤240包括利用无电镀工艺镀覆钯层。无电镀钯槽利用氧化还原反应在镍层上沉积一薄层钯,在氧化还原反应中还原剂向来自镀覆溶液的带正电钯离子提供电子。在另一个实施例中,步骤240包括利用浸镀工艺镀覆钯层。在该反应中,在化学置换反应中仅将钯原子沉积到暴露的镍表面上。浸镀是一种置换过程,这意味着利用镀覆金属层取代被镀覆的顶层材料。这限制了所镀覆的层的厚度,因为该浸入过程是受自身限制的,且一旦原始金属表面不再暴露就会停止。
方法200的步骤250是在钯层上形成金层。例如,金层可以类似于图1中示出的金层123。在一个实施例中,步骤250包括利用浸镀工艺镀覆金层。在另一个实施例中,步骤250包括利用无电镀工艺镀覆金层。在另一个实施例中,步骤250包括利用浸镀工艺和无电镀工艺两者来镀覆金层。
镀覆工艺的选择至少可以在一定程度上取决于金层的期望厚度。如果所镀覆的层的期望厚度比用浸镀技术可获得的厚度厚,则必须使用其他方法作为浸镀的替代或补充。应当指出,即使使用了浸镀和无电镀两者,结果仍然是被镀覆的物质(无论是金或另一种材料)的单层;通常无法检测出什么是利用浸入技术镀覆的和什么是利用无电镀技术镀覆的之间的界限。
图3为示出了根据本发明不同实施例的制造LGA基板的方法300的流程图。方法300的步骤310是提供其上形成有内置电介质材料、至少一个金属层以及阻焊剂的内核,并将导电平面栅格阵列焊盘电连接到该金属层。例如,内核、内置电介质材料、金属层、阻焊剂和导电平面栅格阵列焊盘可以分别类似于内核110、内置电介质材料150、金属层125、阻焊剂155和平面栅格阵列焊盘120,所有这些都在图1中示出。
方法300的步骤320是利用无电镀工艺在导电平面栅格阵列焊盘上镀覆镍层。例如,镍层可以类似于图1中示出的镍层121。在一个实施例中,步骤320包括使镍层具有介于大约5微米和大约10微米之间的厚度。
方法300的步骤330是利用无电镀工艺或浸镀工艺在镍层上镀覆钯层。例如,钯层可以类似于图1中示出的钯层122。在一个实施例中,步骤330包括使钯层具有介于大约0.01微米和大约0.1微米之间的厚度。
方法300的步骤340是在钯层上镀覆金层。例如,金层可以类似于图1中示出的金层123。在一个实施例中,步骤340包括利用浸镀工艺。在另一个实施例中,步骤340包括利用无电镀工艺。在另一个实施例中,步骤340包括利用浸镀工艺和无电镀工艺两者。在一个实施例中,步骤340包括使金层具有介于大约0.01微米和大约0.5微米之间的厚度。
带缺陷的LGA单元的比例与时间之间的关系随着所使用的表面终饰的类型而变化。已经发现,根据本发明的实施例的NiPdAu表面终饰在电迁移MTTF方面比特定C4焊料冶金技术的标准ENIG+EG表面终饰所可能实现的效果提供了高达40%的改进。改进量部分取决于用于NiPdAu表面终饰的焊料的类型。
尽管已经参考特定实施例描述了本发明,但本领域的技术人员要理解,可以做出各种改变而不脱离本发明的精神或范围。因此,本发明的实施例的公开内容意在例示本发明的范围,而并非意在限制。本发明的范围应仅限于所附权利要求所请求保护的范围。例如,对于本领域的普通技术人员而言,显而易见的是本文所述的LGA基板和相关方法可以被实现为各种实施例,对这些实施例的上述特定的讨论未必代表对所有可能实施例的完整描述。
此外,已经结合特定实施例描述了益处、其他优点和问题的解决方案。然而,益处、优点、问题的解决方案以及可能产生任何益处、优点或方案或使其更明确的任何要素不应被视为任何或所有权利要求的关键、必需或必要特征或要素。
此外,如果实施例和/或限制:(1)未在权利要求中被明确主张;且(2)在等价原则下是或可能是权利要求中所述要素和/或限制的等价物,则本文公开的实施例和限制并非是在贡献原则下呈献给公众的。
Claims (25)
1、一种LGA基板,包括:
内核,其上形成有内置电介质材料、至少一个金属层和阻焊剂;
电连接到所述金属层的导电平面栅格阵列焊盘;
所述导电平面栅格阵列焊盘上的镍层;
所述镍层上的钯层;以及
所述钯层上的金层。
2、根据权利要求1所述的LGA基板,其中:
所述镍层具有介于大约5微米和大约10微米之间的厚度。
3、根据权利要求1所述的LGA基板,其中:
所述钯层具有介于大约0.01微米和大约0.1微米之间的厚度。
4、根据权利要求1所述的LGA基板,其中:
所述金层具有介于大约0.01微米和大约0.5微米之间的厚度。
5、根据权利要求1所述的LGA基板,其中:
所述导电平面栅格阵列焊盘包括铜连接盘。
6、根据权利要求5所述的LGA基板,其中:
所述镍层具有不大于大约10微米的厚度;
所述钯层具有不大于大约0.1微米的厚度;并且
所述金层具有不大于大约0.5微米的厚度。
7、一种制造LGA基板的方法,所述方法包括:
提供内核,其上形成有内置电介质材料、至少一个金属层和阻焊剂;
将导电平面栅格阵列焊盘电连接到所述金属层;
在所述导电平面栅格阵列焊盘上形成镍层;
在所述镍层上形成钯层;以及
在所述钯层上形成金层。
8、根据权利要求7所述的方法,其中:
形成所述镍层包括利用无电镀工艺镀覆所述镍层。
9、根据权利要求7所述的方法,其中:
形成所述钯层包括利用无电镀工艺镀覆所述钯层。
10、根据权利要求7所述的方法,其中:
形成所述钯层包括利用浸镀工艺镀覆所述钯层。
11、根据权利要求7所述的方法,其中:
形成所述金层包括利用浸镀工艺镀覆所述金层。
12、根据权利要求11所述的方法,其中:
形成所述镍层包括利用无电镀工艺镀覆所述镍层;并且
形成所述钯层包括利用无电镀工艺镀覆所述钯层。
13、根据权利要求11所述的方法,其中:
形成所述镍层包括利用无电镀工艺镀覆所述镍层;并且
形成所述钯层包括利用浸镀工艺镀覆所述钯层。
14、根据权利要求7所述的方法,其中:
形成所述金层包括利用无电镀工艺镀覆所述金层。
15、根据权利要求14所述的方法,其中:
形成所述镍层包括利用无电镀工艺镀覆所述镍层;并且
形成所述钯层包括利用无电镀工艺镀覆所述钯层。
16、根据权利要求14所述的方法,其中:
形成所述镍层包括利用无电镀工艺镀覆所述镍层;并且
形成所述钯层包括利用浸镀工艺镀覆所述钯层。
17、根据权利要求7所述的方法,其中:
形成所述金层包括利用浸镀工艺和无电镀工艺镀覆所述金层。
18、根据权利要求17所述的方法,其中:
形成所述镍层包括利用无电镀工艺镀覆所述镍层;并且
形成所述钯层包括利用无电镀工艺镀覆所述钯层。
19、根据权利要求17所述的方法,其中:
形成所述镍层包括利用无电镀工艺镀覆所述镍层;并且
形成所述钯层包括利用浸镀工艺镀覆所述钯层。
20、一种制造LGA基板的方法,所述方法包括:
提供其上形成有内置电介质材料、至少一个金属层和阻焊剂的内核,并将导电平面栅格阵列焊盘电连接到所述金属层;
利用无电镀工艺在所述导电平面栅格阵列焊盘上镀覆镍层;
利用无电镀工艺或浸镀工艺在所述镍层上镀覆钯层;以及
在所述钯层上镀覆金层。
21、根据权利要求20所述的方法,其中:
镀覆所述金层包括使用浸镀工艺。
22、根据权利要求21所述的方法,其中:
镀覆所述镍层包括使所述镍层具有介于大约5微米和大约10微米之间的厚度;
镀覆所述钯层包括使所述钯层具有介于大约0.01微米和大约0.1微米之间的厚度;并且
镀覆所述金层包括使所述金层具有介于大约0.01微米和大约0.5微米之间的厚度。
23、根据权利要求20所述的方法,其中:
镀覆所述金层包括使用无电镀工艺。
24、根据权利要求23所述的方法,其中:
镀覆所述镍层包括使所述镍层具有介于大约5微米和大约10微米之间的厚度;
镀覆所述钯层包括使所述钯层具有介于大约0.01微米和大约0.1微米之间的厚度;并且
镀覆所述金层包括使所述金层具有介于大约0.01微米和大约0.5微米之间的厚度。
25、根据权利要求20所述的方法,其中:
镀覆所述金层包括使用浸镀工艺和无电镀工艺两种工艺。
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CN103238204A (zh) * | 2010-09-25 | 2013-08-07 | 英特尔公司 | 应用在无芯基板工艺中的电解金或金钯表面终饰 |
WO2023123116A1 (zh) * | 2021-12-29 | 2023-07-06 | 京东方科技集团股份有限公司 | 线路板、功能背板、背光模组、显示面板及显示装置 |
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TW201011878A (en) * | 2008-09-03 | 2010-03-16 | Phoenix Prec Technology Corp | Package structure having substrate and fabrication thereof |
US8127979B1 (en) | 2010-09-25 | 2012-03-06 | Intel Corporation | Electrolytic depositon and via filling in coreless substrate processing |
US20120268928A1 (en) * | 2010-10-26 | 2012-10-25 | Sargent Robert L | Large single chip led device for high intensity packing |
TWI441292B (zh) * | 2011-03-02 | 2014-06-11 | 矽品精密工業股份有限公司 | 半導體結構及其製法 |
KR101251802B1 (ko) * | 2011-07-27 | 2013-04-09 | 엘지이노텍 주식회사 | 메모리카드, 메모리 카드용 인쇄회로기판 및 이의 제조 방법 |
KR102014088B1 (ko) * | 2012-03-20 | 2019-08-26 | 엘지이노텍 주식회사 | 메모리카드, 메모리 카드용 인쇄회로기판 및 이의 제조 방법 |
EP2740818B1 (en) * | 2012-12-05 | 2016-03-30 | ATOTECH Deutschland GmbH | Method for manufacture of wire bondable and solderable surfaces on noble metal electrodes |
US9603247B2 (en) * | 2014-08-11 | 2017-03-21 | Intel Corporation | Electronic package with narrow-factor via including finish layer |
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US20020020898A1 (en) * | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
JP4075306B2 (ja) * | 2000-12-19 | 2008-04-16 | 日立電線株式会社 | 配線基板、lga型半導体装置、及び配線基板の製造方法 |
US6770965B2 (en) * | 2000-12-28 | 2004-08-03 | Ngk Spark Plug Co., Ltd. | Wiring substrate using embedding resin |
US6586043B1 (en) * | 2002-01-09 | 2003-07-01 | Micron Technology, Inc. | Methods of electroless deposition of nickel, methods of forming under bump metallurgy, and constructions comprising solder bumps |
US20050001316A1 (en) * | 2003-07-01 | 2005-01-06 | Motorola, Inc. | Corrosion-resistant bond pad and integrated device |
US7179738B2 (en) * | 2004-06-17 | 2007-02-20 | Texas Instruments Incorporated | Semiconductor assembly having substrate with electroplated contact pads |
US7488896B2 (en) * | 2004-11-04 | 2009-02-10 | Ngk Spark Plug Co., Ltd. | Wiring board with semiconductor component |
US20080188037A1 (en) * | 2007-02-05 | 2008-08-07 | Bridge Semiconductor Corporation | Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier |
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CN103238204A (zh) * | 2010-09-25 | 2013-08-07 | 英特尔公司 | 应用在无芯基板工艺中的电解金或金钯表面终饰 |
CN103238204B (zh) * | 2010-09-25 | 2016-08-10 | 英特尔公司 | 应用在无芯基板工艺中的电解金或金钯表面终饰 |
WO2023123116A1 (zh) * | 2021-12-29 | 2023-07-06 | 京东方科技集团股份有限公司 | 线路板、功能背板、背光模组、显示面板及显示装置 |
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