CN101470458B - Bandgap Reference Voltage Reference Circuit - Google Patents

Abstract

The invention discloses a band gap reference voltage reference circuit, which comprises: a V_BEA voltage generator (11), the V_BEThe voltage generator (11) comprises a self-bias current source (111) for generating a two-branch reference circuit, and a circuit coupled to the self-bias current source (111) for generating two paths V_BEA bias generator (112) of voltage; a reference voltage regulator (12), the reference voltage regulator (12) comprising an operational transconductance amplifier (121) and a reference voltage regulating unit (122) for generating a constant reference voltage. The invention uses the transistor of the sub-threshold working region to replace a resistor to amplify the voltage with positive temperature coefficient, thereby reducing the power consumption and the cost of the band-gap reference voltage reference circuit.

Description

Bandgap Reference Voltage Reference Circuit

technical field

The invention relates to the technical field of analog circuit design, in particular to a low-power consumption bandgap reference voltage reference circuit without any resistance element.

Background technique

In analog circuit design, the reference voltage reference circuit is one of the essential components of many important functional modules. The purpose of a voltage reference is to create a DC voltage source that is independent of temperature, process, and supply voltage variations.

The currently recognized voltage reference technology is a bandgap voltage reference. A bandgap voltage reference uses a circuit proportional to absolute temperature to offset the negative temperature characteristic of the base-emitter voltage of a bipolar transistor, thereby obtaining a constant output reference voltage, which is typically the bandgap voltage of silicon 1.25V or so. Moreover, the bandgap voltage reference can remain stable under different supply voltages and process conditions as well as a wide operating temperature range.

The base-emitter voltage of bipolar transistors has a negative temperature coefficient. Generally, this temperature coefficient is about -1.5mV/°C. When two bipolar transistors are operated at unequal current densities, the difference in their base-emitter voltages is proportional to the absolute temperature. Typically, the temperature coefficient of the difference is one third to one sixth of the temperature coefficient of the base-emitter voltage of a single bipolar transistor.

In traditional bandgap reference circuits, the ratio of two different resistor values is generally used to amplify the difference in the base-emitter voltages of two bipolar transistors so that it is comparable to the base-emitter voltage of a single bipolar transistor. The temperature coefficient of the zone voltage cancels out, thus obtaining a reference voltage with zero temperature coefficient.

In the traditional CMOS process flow, the silicide process is used to reduce the sheet resistance of the polysilicon and the diffusion region, thereby increasing the length and area of the required resistance. Part of the process flow can use the silicide barrier layer to increase the resistance value, and at the same time increase the cost of the process. However, in traditional bandgap reference voltage reference circuits, large resistors are generally used to meet the requirements of low power consumption, which also greatly increases the cost of the circuit.

One factor that must be considered in the design of a voltage reference circuit is the size or chip area required for its circuit. Usually, the size of the reference voltage circuit is determined by the main circuit design of the integrated circuit. Reducing the required area of the reference voltage circuit helps to minimize the chip area of the circuit or increase the area used for the main circuit design, thereby reducing chip cost.

In addition, the resistance provided in the CMOS process has a certain temperature coefficient, which affects the performance of the output reference voltage, and the resistance model provided by the process manufacturer is often of low accuracy, so the performance of the traditional bandgap reference voltage reference circuit is often limited by the resistance. performance and accuracy of the model.

With the rapid development of deep submicron integrated circuit technology and handheld mobile device industry, low-power analog circuit design is becoming a research hotspot. In traditional reference circuits, in order to reduce power consumption, large-area resistors are often used. If a reference circuit without resistive components can be made, its power consumption and cost can be greatly reduced.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a low power consumption bandgap reference voltage reference circuit without any resistance element, so as to reduce the power consumption and cost of the bandgap reference voltage reference circuit.

(2) Technical solution

In order to achieve the above object, the technical solution of the present invention is achieved in that:

A bandgap reference voltage reference circuit, the circuit comprising:

A V _BE voltage generator 11, the V _BE voltage generator 11 includes a self-bias current source 111 for generating two-way reference circuits, and a self-bias current source 111 coupled to the self-bias current source 111 for generating two-way V Bias generator 112 for _BE voltage;

A reference voltage regulator 12, which includes an operational transconductance amplifier 121 and a reference voltage adjustment unit 122 for generating a constant reference voltage; wherein:

The self-bias current source 111 includes PMOS transistors M1, M2 and NMOS transistors M3, M4, wherein the sources of M1 and M2 are connected to the reference power supply, the gate of M1, the gate and drain of M2 and the drain of M4 are directly coupled, and the drain of M1, the gate and drain of M3 and the gate of M4 are directly coupled, and the sources of M3 and M4 are respectively connected to the emitter regions of pnp transistors D1 and D2 in the bias generator 112;

The bias generator 112 includes pnp transistors D1 and D2, the base area and the collector area of D1 and D2 are grounded, and the emitter area is respectively connected to the sources of M3 and M4 in the self-bias current source 111;

The operational transconductance amplifier 121 includes one positive input terminal, one negative input terminal and one output terminal, wherein the positive input terminal is connected to the gate of the transistor M7 in the reference voltage adjustment unit 122, and the negative input terminal is connected to the self-biased The source of M3 in the current source 111 is connected, and the output is connected to the gate of the transistor M5; the transistor M5 is used to provide a DC bias for the reference voltage adjustment unit 122;

The reference voltage adjustment unit 122 includes PMOS transistors M6, M7 and M8, the transistors M6, M7 and M8 are sub-threshold transistors in operation, wherein the gates of the transistors M6 and M7 are connected to the drain, and the gate of M8 is connected to the The source of M4 in the self-bias current source 111 is connected; the substrates of M6, M7 and M8 are connected to their respective sources.

In the above solution, the first bias and the second bias generated by the bias generator 112 are jointly coupled to the self-bias current source 111 to generate two reference voltages.

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

1. Traditional bandgap reference circuits use resistors to convert current into voltage form and provide positive temperature coefficient voltage gain. The gate-source voltage of a MOS transistor operating in the subthreshold region decreases approximately linearly within a certain range as the temperature increases. Based on this characteristic, the resistors in the traditional bandgap reference circuit can be replaced by transistor sleeves operating in the subthreshold region to generate a positive temperature coefficient voltage gain, which is used to offset the negative temperature coefficient of the bipolar transistor base-emitter Voltage, outputting a reference source with a low temperature coefficient, thus avoiding the use of resistors and reducing the power consumption and area of the circuit.

2, the present invention utilizes the transistor of sub-threshold value work area to replace the voltage with positive temperature coefficient of resistance amplification, thereby obtains low power consumption, the bandgap reference voltage reference circuit of high integration degree, has reached and reduced the function of bandgap reference voltage reference circuit consumption and cost purposes.

3. The bandgap reference voltage reference circuit provided by the present invention eliminates the use of resistors, and adopts transistors in the subthreshold region to reduce the operating current and area of the circuit. Compared with traditional bandgap reference voltage reference circuits, it has a lower power consumption and cost.

Description of drawings

Fig. 1 is the circuit diagram of the bandgap reference voltage reference circuit provided by the present invention;

Fig. 2 is a temperature characteristic curve diagram of the output reference voltage of the voltage reference circuit shown in Fig. 1;

FIG. 3 is a graph showing the variation of the output reference voltage of the voltage reference circuit shown in FIG. 1 with the power supply voltage.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in FIG. 1 , FIG. 1 is a circuit diagram of a bandgap reference voltage reference circuit provided by the present invention, and the circuit includes a V _BE voltage generator 11 and a reference voltage regulator 12 . Wherein, the V _BE voltage generator 11 includes a self-bias current source 111 for generating two-branch reference circuits, and a bias generator coupled to the self-bias current source 111 for generating two V _BE voltages device 112. The reference voltage regulator 12 includes an operational transconductance amplifier 121 and a reference voltage adjustment unit 122 for generating a constant reference voltage.

The V _BE voltage generator 11 generates a first V _BE voltage and a second V _BE voltage, the first V _BE voltage is directly coupled to _the reference voltage adjustment unit 122, and the second V BE voltage is directly coupled to the reference voltage adjustment unit 122. The voltage is coupled to the reference voltage adjustment unit 122 through the operational transconductance amplifier 121 .

The self-bias current source 111 includes PMOS transistors M1, M2 and NMOS transistors M3, M4, wherein the sources of M1 and M2 are connected to the reference power supply, the gate of M1, the gate and drain of M2 and the drain of M4 pole is directly coupled, and the drain of M1, the gate and drain of M3 and the gate of M4 are directly coupled, and the sources of M3 and M4 are respectively in phase with the emitter regions of pnp transistors D1 and D2 in the bias generator 112 connect.

The bias generator 112 for generating two-way V _BE voltages includes pnp transistors D1 and D2, the base and collector regions of D1 and D2 are grounded, and the emitter region is connected to M3 and M4 in the self-bias current source 111 The sources are connected separately. The conduction area of the transistor D1 is N times the conduction area of the transistor D2.

The first bias and the second bias generated by the bias generator 112 are jointly coupled to the self-bias current source 111 to generate two reference voltages.

The operational transconductance amplifier 121 includes one positive input terminal, one negative input terminal and one output terminal, wherein the positive input terminal is connected to the gate of the transistor M7 in the reference voltage adjustment unit 122, and the negative input terminal is connected to the gate of the transistor M7 in the reference voltage adjustment unit 122. The source of M3 in the self-bias current source 111 is connected, and the output is connected to the gate of transistor M5. The transistor M5 is used to provide a DC bias for the reference voltage adjustment unit 122 .

The reference voltage adjustment unit 122 includes PMOS transistors M6, M7 and M8, the gates of the transistors M6 and M7 are connected to the drain, and the gate of M8 is connected to the source of M4 in the self-bias current source 111. connection; the substrates of M6, M7 and M8 are connected to their respective sources.

Referring to FIG. 1 again, pnp bipolar transistors D1 and D2 are used to generate two voltages 31 and 32 with negative temperature coefficients, and the temperature coefficient A of the nodes can be expressed as the following formula:

A＝(V _BE -2.5×V _T -E _g /q)/T (1)

In the formula (1), V _BE represents the emitter voltage of the bipolar transistors D1 and D2, E _g is the bandgap energy of silicon, and T is the absolute temperature. Therefore, when V _BE is approximately equal to 750mV and T=300K, the temperature coefficient of V _BE is approximately -1.5mV/°C.

The node 31 is coupled to the node 33 through an operational transconductance amplifier 121, and the output port of the operational transconductance amplifier controls the DC bias of the reference voltage adjustment unit 122, so:

V ₃₁ =V ₃₃ (2)

From the (2) formula, get:

V ₃₃ −V ₃₂ =V _T ×ln(n) (3)

In the formula (3), V _T is the thermal voltage, which is approximately equal to 26mV at normal temperature, and N is the ratio of the conductive areas of the bipolar transistors D2 and D1. Since the direct current flows through the MOS transistors M6, M7 and M8, when the voltage from the drain to the source of the transistor is greater than 4 times V _T , the following three formulas can be obtained:

I _M6 ＝uC _d V _T ² W _M6 /L _M6 exp((V ₃₅ -V ₃₄ -|V _{th, M6} |)/(r×V _T )) (4)

I _M7 ＝uC _d V _T ² W _M7 /L _M7 exp((V ₃₄ −V ₃₃ −|V _{th, M7} |)/(r×V _T )) (5)

I _M8 ＝uC _d V _T ² W _M8 /L _M8 exp((V ₃₃ -V ₃₂ -|V _{th, M8} |)/(r×V _T )) (6)

In the formulas (4)-(6), I is the current flowing through the transistor, u is the mobility of the minority carriers, C _d is the depletion layer capacitance under the gate, W and L are the channel of the MOS transistor respectively The width and length of the track, V _th is the threshold voltage of the MOS transistor, r is the subthreshold slope factor, and formulas (4)-(6) can be transformed into formulas (7)-(8):

r×V _T ×ln(I _M6 /(uC _d V _T ² W _M6 /L _M6 ))＝V ₃₅ -V ₃₄ -|V _th，M6 | (7)

r×V _T ×ln(I _M7 /(uC _d V _T ² W _M7 /L _M7 ))=V ₃₄ -V ₃₃ -|V _{th, M7} | (8)

r×V _T ×ln(I _M8 /(uC _d V _T ² W _M8 /L _M8 ))＝V ₃₃ -V ₃₂ -|V _th，M8 | (9)

Since the substrates of transistors M6, M7, and M8 are connected to their respective sources, the body effect is eliminated, so there are:

|Vth _{, M6} |=|Vth _{, M7} |=|Vth _{, M8} | (10)

Put (9)×2-(7)-(8), and according to (10), there are:

V ₃₅ ＝V ₃₂ +3×(V ₃₃ −V ₃₂ )+r×V _T ×ln((W _M8 /L _M8 ) ² /((W _M6 /L _M6 )×(W _M7 /L _M7 )))

(11)

Bring (3) into (11) to get:

V ₃₅ ＝V ₃₂ +3×V _T ×ln(n)+r×V _T ×ln((W _M8 /L _M8 ) ² /((W _M6 /L _M6 )×(W _M7 /L _M7 )))

(12)

In (12) formula, node 35 is the output reference voltage. The first item on the right side of the equation in the above formula is the negative temperature coefficient voltage, the second item is the positive temperature coefficient voltage, and the third item is the adjustment item of the positive temperature coefficient voltage. The output node 35 can be made to have a zero temperature coefficient by selecting appropriate parameters.

Examples using real numerical values help illustrate the design of voltage reference circuits. Assuming that the temperature coefficient of the emitter of the bipolar transistor is -1.5mV/°C, n is 24, and V _T is equal to 26mV, in order to make the output reference voltage have a zero temperature coefficient, the following formula is given:

ln((W _M8 /L _M8 ) ² /((W _M6 /L _M6 )×(W _M7 /L _M7 )))＝(-V ₃₂ -3×V _T ×ln(n))/(r×V _T )

(13)

Differentiate both sides of the equation (13), and then bring in specific values, you can get:

(W _M8 /L _M8 ) ² /((W _M6 /L _M6 )×(W _M7 /L _M7 ))＝180 (14)

When the output reference voltage is zero temperature coefficient, its value is equal to the bandgap voltage of silicon about 1.2V, so according to the initial conditions:

V ₃₅ | _T ＝T ₀ ＝1.2V (15)

Using the working equations (4)-(6) of the transistors M6, M7 and M8 in the subthreshold working region, it can be determined that the length of the transistors M6, M7 and M8 is 0.4u, and the widths are 40u, 10u and 1u respectively. In this way, a reference voltage reference circuit with zero temperature coefficient is realized.

Since the transistors M6, M7 and M8 work in the sub-threshold region, the current flowing through them can be at the nanoampere level, and the input tube of the operational transconductance amplifier can also work in the sub-threshold region to provide a certain gain, which greatly reduces the power consumption of the reference circuit.

FIG. 2 is a temperature characteristic graph of the output reference voltage of the voltage reference circuit shown in FIG. 1 . The graph shown in Figure 2 is simulated under the 0.18um CMOS mixed-signal process BSIM3V3 SPICE model provided by SMIC with component values similar to the above example. The graph is centered on 40°C and the temperature range is from -40°C to 120°C. In this temperature range, the voltage varies between 1.210V and 1.216V, the variation range is 6mV, the temperature coefficient is 31ppm/℃, ppm means one millionth, and the total current of the circuit is less than 3 microamperes.

FIG. 3 is a graph showing the variation of the output reference voltage of the voltage reference circuit shown in FIG. 1 with the power supply voltage. The process used is the same as that described in Figure 2. This graph shows the response of the output reference voltage as the supply voltage varies from 0V to 5V. When the supply voltage increases from 0V, the output reference voltage also increases; when the supply voltage increases to 1.5V, the output reference voltage rises to 1.2V, and then remains basically constant until the supply voltage rises to 5V. Within the power supply voltage variation range, the voltage varies between 1.211V and 1.233V (at room temperature), the variation range is 22mV, and the power supply voltage suppression coefficient is 6mV/V.

So far, it can be understood that the non-resistor voltage reference circuit provided by the present invention. For MOS transistors, when the leakage current remains constant, the gate-source voltage of the transistor operating in the weak inversion region decreases approximately linearly within a certain range as the temperature increases. Transistors operating in the subthreshold region using multiple sleeve structures can replace resistors to amplify voltages with positive temperature coefficients to cancel out the base-emitter voltages of bipolar transistors with negative temperature coefficients, resulting in Temperature Independent Reference Voltage. Since the use of resistors is eliminated, the power consumption and area of the circuit are reduced.

Based on the bandgap reference voltage reference circuit shown in Figure 1, the present invention also provides a method for applying the bandgap reference voltage reference circuit to generate a reference voltage, the method comprising the following steps:

Generate two reference voltages with negative temperature coefficients;

Subtracting these two generated reference voltages yields a voltage with a positive temperature coefficient;

amplifying the voltage with a positive temperature coefficient;

The reference voltage is obtained by adding two equal voltages with positive and negative temperature coefficients.

The amplification of the voltage with a positive temperature coefficient is accomplished by transistors in the subthreshold operating region; the reference voltage is generated by the sum of a base-emitter voltage drop and the amplified voltage with an equal positive temperature coefficient.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (2)

1. a bandgap voltage reference circuit is characterized in that, this circuit comprises:

One V _BEVoltage generator (11), this V _BEVoltage generator (11) comprises a self-bias current source (111) that is used to produce two branch road reference circuits, and be coupled in this self-bias current source (111) be used to produce two-way V _BEThe bias generator of voltage (112);

One reference voltage regulator (12), this reference voltage regulator (12) comprise operation transconductance amplifier (121) and reference voltage regulon (122), are used to produce a constant reference voltage; Wherein:

Self-bias current source (111) comprises PMOS transistor M1, M2 and nmos pass transistor M3, M4, wherein the source electrode of M1 and M2 is connected with reference power source, the drain electrode of the grid of M1, the grid of M2 and drain electrode and M4 directly is coupled, and the grid of the grid of the drain electrode of M1, M3 and drain electrode and M4 directly is coupled, and the source electrode of M3, M4 is connected with the launch site of middle pnp transistor D1 of described bias generator (112) and D2 respectively;

Bias generator (112) comprises pnp transistor D1 and D2, the base of D1 and D2 and collecting zone ground connection, and the launch site is connected respectively with the source electrode of middle M3 of described self-bias current source (111) and M4;

Operation transconductance amplifier (121) comprises one road positive input terminal, one road negative input end and one road output terminal, wherein the grid of the transistor M7 in positive input terminal and the described reference voltage regulon (122) is connected, negative input end is connected with the source electrode of M3 in the described self-bias current source (111), and output is connected with the grid of transistor M5; Described transistor M5 is used to described reference voltage regulon (122) that direct current biasing is provided;

Reference voltage regulon (122) comprises PMOS transistor M6, M7 and M8, this transistor M6, M7 and M8 are the transistors of subthreshold value in the work, wherein the grid of transistor M6 and M7 is connected with drain electrode, and the grid of M8 is connected with the source electrode of M4 in the described self-bias current source (111); The substrate of described M6, M7 and M8 is connected with source electrode separately.

2. bandgap voltage reference circuit according to claim 1 is characterized in that, the first via biasing that described bias generator (112) produces and the second tunnel biasing coupled in common go up to described self-bias current source (111) and produce the two-way reference voltage.

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