CN101464490A - General-purpose test board and its use method - Google Patents
General-purpose test board and its use method Download PDFInfo
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- CN101464490A CN101464490A CNA2007101724231A CN200710172423A CN101464490A CN 101464490 A CN101464490 A CN 101464490A CN A2007101724231 A CNA2007101724231 A CN A2007101724231A CN 200710172423 A CN200710172423 A CN 200710172423A CN 101464490 A CN101464490 A CN 101464490A
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Abstract
The invention relates to a universal type test board and a testing method thereof. The universal type test board can be used for testing encapsulating chips with base pins distributed differently, comprises a plurality of connectors with two columns of contact pins, a plurality of power connectors with two columns of contact pins and a chip socket, and further comprises a plurality of buffering connectors and a plurality of power buffering connectors. The buffering connectors are connected with the chip socket and the connectors; and the power buffering connectors are connected with the power connectors. When the chips are tested on the test board, the configuration of a power channel or a signal channel is conducted to the connecting channels of the contact pins on the buffering connectors through testing the distribution of the base pins of the chips. By adopting the method, the test board can test the various encapsulating chips with the base pins distributed differently, so that a special test board is not required when the chips with the base pins to be distributed are tested, thus effectively solving the testing economic cost of the chips.
Description
Technical field
The present invention relates to the design and the making field of apparatus for testing chip, relate in particular to a kind of general-purpose test board and using method thereof.
Background technology
At present, all need to encapsulate after chip production completes, for example adopt dual-in-line package (DIP), quad flat formula encapsulation (QFP) or other types encapsulation.Different type of package for chips has different pins and distributes and number of pins.These packaged chips all will carry out functional verification and test.When carrying out this operation, these packaged chips need be placed on the specific test board and test.Conventional test board as shown in Figure 1, comprises two connectors 2 (connector), two power connectors 3 and chip carrier socket 1.Such test board is at the dual-in-line package chip.When testing, chip 4 to be tested is placed on the chip carrier socket 1 of the some pin slots of having of test board, two connectors are all tested by after testing special-purpose winding displacement and test machine linking to each other.Be distributed in the test board of the packaged chip of four sides of packaged chip at pin, according to different number of pins, above-mentioned relatively test board, the connector number that four limits of chip carrier socket distribute has difference.
Encapsulation back pin of chip is roughly divided two classes: signal pins and power pins, when test, this two classes pin needs strict the differentiation.Because power pins need be passed through bigger electric current, and signal pins only need be passed through very little electric current.If do not distinguished, test machine will be supplied with the power supply of needs to chip to be measured, and test can not normally be carried out.Signalling channel on the conventionally test plate is corresponding one by one with signal pins and power pins on the chip with power channel, signalling channel links to each other with test machine by connector 2, power channel links to each other with test machine by power connector 3, at specific chip pin, these passages on the test board just are fixed.Because it is many that chip type to be tested has, static store chip (SRAM) for example, dynamic memory chip (DRAM) can be wiped and programmable ROM (read-only memory) (EEPROM) flash chip (flash) etc.These different chips, their pin difference is very big, and also there is very big difference the position that power pins and signal pins distribute on packaged chip.Conventional test board all is that the chip at specific type designs specially, and signalling channel and power channel are fixed, even the difference of encapsulated type identical chips pin distribution still can cause using identical test board like this.This design of test board has caused the dumb of test board application, also needs to spend the test board that great amount of cost is bought dissimilar chip products at dissimilar chips.
Summary of the invention
The object of the present invention is to provide a kind of general-purpose test board and using method, when testing, need to buy the problem of special-purpose test board to solve the packaged chip that different pins are distributed.
For solving the problems of the technologies described above, general-purpose test board of the present invention, this test board has the connector of two row contact pins except comprising several, several have power connector and the chip carrier socket with some pin slots of two row contact pins, and it comprises that also several buffer couplings with ordered series of numbers contact pin and several have the power supply buffer coupling of two row contact pins.Wherein, the contact pin of buffer coupling links to each other with connector with chip carrier socket, and the contact pin of power supply buffer coupling is connected with the contact pin of power connector.Buffer coupling comprises three row contact pins and a set of connections device, and the row contact pin in the three row contact pins links to each other with chip carrier socket, and the row contact pin on another row contact pin and the connector connects one to one.One row contact pin of the buffer coupling that links to each other with chip carrier socket is connected one by one by the row contact pin of this set of connections device with the buffer coupling that links to each other with connector.
The using method of general-purpose test board of the present invention, this general-purpose test board are used for test and have some pins chip to be measured, and using method may further comprise the steps: step 1: will have some pins chip to be measured and place on the chip carrier socket; Step 2: distribute according to the pin of chip to be measured, the interface channel of the contact pin of described buffer coupling is carried out the power channel configuration.
Further, buffer coupling comprises three row contact pins and a set of connections device, row contact pin in the three row contact pins links to each other with chip carrier socket, and another row contact pin links to each other with connector, and a row contact pin that links to each other with chip carrier socket is connected with a row contact pin that links to each other with connector one by one by a set of connections device.The configuration that the interface channel of the contact pin in the step 2 carries out power channel is to remove described electric wire connecting junction, and the contact pin that will link to each other with chip carrier socket with wire jumper is connected with the contact pin on the described power supply buffer coupling.
Compare with existing test board and method of testing, general-purpose test board of the present invention and using method thereof, by the interface channel of buffer coupling contact pin being carried out the configuration of power supply or signalling channel, make no matter chip to be measured is that power pin or signal pins all can directly link to each other with buffer coupling, the restriction that distributed by chip pin to be measured.Can effectively solve the problem that different chips needs the special test plate to test like this.
Description of drawings
Below in conjunction with the drawings and specific embodiments general-purpose test board of the present invention and using method are described in further detail.
Fig. 1 is the synoptic diagram of conventionally test plate structure.
Fig. 2 is a general-purpose test board structural representation of the present invention.
Fig. 3 is the synoptic diagram of the using method of Fig. 2 general-purpose test board power channel configuration.
Embodiment
DIP encapsulation at present is a kind of encapsulated type commonly used in the Chip Packaging, and the general-purpose test board that encapsulates the chip to be measured of class with test DIP is an example.See also Fig. 2, this general-purpose test board comprises two connectors 2 that all have two row contact pins 11 respectively, two power connectors 3 with two row contact pins 11 have chip carrier socket 1 and two buffer couplings 13 with ordered series of numbers contact pin 11 and two power supply buffer couplings 6 with two row contact pins 11 of some pin slots.Buffer coupling 13 is connected with chip carrier socket 1 with connector 2, and power supply buffer coupling 6 is connected with power connector 3.The contact pin of power supply buffer coupling 6 is connected with the contact pin of power connector 3.
The using method of the general-purpose test board of the foregoing description, the chip to be measured that at first will have some pins places on the chip carrier socket 1 with some pin slots.Distribute according to the pin of chip to be measured then, the interface channel of the contact pin of buffer coupling is carried out power channel or signalling channel configuration.
See also Fig. 3, when testing chip 20 to be measured, this chip 20 places on the chip carrier socket 1.Buffer coupling 13 has the test board of three row contact pins, and wherein a row contact pin 11a links to each other with connector 2, and promptly the row contact pin with connector 2 connects one to one; Another row contact pin 11b with corresponding the connecting of pin slot of chip carrier socket 1.The power pin of supposing chip 20 is connected with 11c27 with the contact pin 11b17 of buffer coupling 13 respectively by chip carrier socket 1, then needs interface channel C17 shown in the dotted line of buffer coupling 13 contact pin 11b17 and 11c27 and interface channel C27 are carried out the power channel configuration.Need remove respectively and connect contact pin 11b17 and the line-connecting machine 12 that is connected contact pin 11c27, will directly be connected with contact pin on the power supply buffer coupling 6 with the contact pin 11b17 by the continuous buffer coupling 13 of the power pin of chip carrier socket 1 and chip 20 and contact pin 11c27 with 19 by wire jumper 18 then.Connection for the ground pin that makes things convenient for chip, row contact pin in the three row contact pins of buffer coupling 13 can be used to ground connection, so only need by the electric wire connecting junction on the buffer coupling 13 12 with the contact pin that links to each other with chip carrier socket 1 on the buffer coupling 13 and on it contact pin of ground connection couple together the ground connection that just can conveniently realize chip pin.
Above embodiment has only provided the test board that is primarily aimed at the dual-in-line package chip, equally to other class encapsulation, under number of pins is not a lot of situation, under the situation of the interface channel abundance of the contact pin of buffer coupling 13 and power supply buffer coupling 6, also can test at this general-purpose test board.When the pin of chip number was more, test board had three to four connectors, also had three to four or more at the buffer coupling of such general-purpose test board.The number of the power connector of same this general-purpose test board also may increase, when guaranteeing test like this, and the contact pin interface channel abundance of power supply impact damper.
Be configured by the interface channel to the buffer coupling contact pin, the restriction that distributed by the packaged chip pin just can adopt this general-purpose test board to test to different test chips.In fact, at present DIP is comparatively common type of package for chips in engineering is used, and DIP encapsulated type converter (Adapter) also has much and appears on the market, adopts it easily other encapsulated type chips to be converted to the DIP formula.Be the chip of the more pin of convenient test, general-purpose test board can guarantee that it has sufficient contact pin interface channel.
Claims (6)
1, a kind of general-purpose test board, described test board comprises that several have the connector of two row contact pins, several have power connector and the chip carrier socket with some pin slots of two row contact pins, it is characterized in that it comprises that also several buffer couplings with ordered series of numbers contact pin and several have the power supply buffer coupling of two row contact pins; The contact pin of described buffer coupling links to each other with connector with chip carrier socket, and the contact pin of described power supply buffer coupling is connected with the contact pin of power connector.
2, general-purpose test board as claimed in claim 1, it is characterized in that, described buffer coupling comprises three row contact pins and a set of connections device, and the row contact pin in the described three row contact pins links to each other with chip carrier socket, and a row contact pin of another row contact pin and described connector connects one to one.
3, general-purpose test board as claimed in claim 2, it is characterized in that, the row contact pin on described and the buffer coupling that chip carrier socket links to each other by a described set of connections device with buffer coupling that described connector links to each other on a row contact pin connect one to one.
4, the using method of general-purpose test board as claimed in claim 1, described general-purpose test board are used to test the chip to be measured with some pins, it is characterized in that, its using method may further comprise the steps:
Step 1: described chip to be measured with some pins is placed on the chip carrier socket with some slots;
Step 2: distribute according to the pin of described chip to be measured, the interface channel of the contact pin of described buffer coupling is carried out the power channel configuration.
5, using method as claimed in claim 4, it is characterized in that, described buffer coupling comprises three row contact pins and a set of connections device, row contact pin in the described three row contact pins links to each other with chip carrier socket, another row contact pin links to each other with connector, and a described row contact pin that links to each other with chip carrier socket connects one to one with a row contact pin that links to each other with described connector by a described set of connections device.
6, using method as claimed in claim 5, it is characterized in that, the configuration that the interface channel of the contact pin in the described step 2 carries out power channel is to remove described electric wire connecting junction, and the contact pin that will link to each other with chip carrier socket with wire jumper is connected with the contact pin on the described power supply buffer coupling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101724231A CN101464490B (en) | 2007-12-17 | 2007-12-17 | General-purpose test board and its use method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101724231A CN101464490B (en) | 2007-12-17 | 2007-12-17 | General-purpose test board and its use method |
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| Publication Number | Publication Date |
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| CN101464490A true CN101464490A (en) | 2009-06-24 |
| CN101464490B CN101464490B (en) | 2010-12-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2007101724231A Expired - Fee Related CN101464490B (en) | 2007-12-17 | 2007-12-17 | General-purpose test board and its use method |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102426333A (en) * | 2011-10-18 | 2012-04-25 | 山东华翼微电子技术有限责任公司 | All-contact signal testing device for contact type IC (Integrated Circuit) card |
| CN102721839A (en) * | 2012-07-09 | 2012-10-10 | 上海华岭集成电路技术股份有限公司 | Test adaptation board |
| CN103278763A (en) * | 2013-04-28 | 2013-09-04 | 上海华力微电子有限公司 | Film transistor (FT) test board system and test method of chip |
| CN103765232A (en) * | 2011-08-29 | 2014-04-30 | 西门子公司 | Wiring test device for electronics cabinets having internal signal wiring |
| CN103869105A (en) * | 2012-12-11 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | General type test board |
| CN104281147A (en) * | 2014-10-24 | 2015-01-14 | 上海自仪泰雷兹交通自动化系统有限公司 | Internal signal fault testing device for rail transit signal equipment |
| CN106249001A (en) * | 2016-05-05 | 2016-12-21 | 苏州能讯高能半导体有限公司 | A kind of test board |
| WO2018068627A1 (en) * | 2016-10-12 | 2018-04-19 | 肖敏 | Apparatus for chip testing and programming, and manufacturing method therefor |
| CN111208323A (en) * | 2018-11-22 | 2020-05-29 | 株式会社Isc | Test socket for testing a device under test |
| CN111579956A (en) * | 2020-04-08 | 2020-08-25 | 上海精密计量测试研究所 | Adjustable surface-mounted packaged semiconductor device clamp and testing method |
| CN113406478A (en) * | 2021-06-23 | 2021-09-17 | 上海电气泰雷兹交通自动化系统有限公司 | Many functional safety hardware test fixture |
| CN114019195A (en) * | 2021-10-29 | 2022-02-08 | 上海华力集成电路制造有限公司 | Chip antistatic performance test board |
| CN116068380A (en) * | 2023-03-01 | 2023-05-05 | 上海聚跃检测技术有限公司 | Chip package testing method and device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW281724B (en) * | 1995-03-06 | 1996-07-21 | Advanced Micro Devices Inc | Apparatus and method to uniquely identify similarly connected electrical devices |
| CN2929733Y (en) * | 2006-06-19 | 2007-08-01 | 纬创资通股份有限公司 | Test board |
-
2007
- 2007-12-17 CN CN2007101724231A patent/CN101464490B/en not_active Expired - Fee Related
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| CN103765232B (en) * | 2011-08-29 | 2016-09-28 | 西门子公司 | For having the wiring test device of the electronic equipment case of the signal wiring of inside |
| US9470736B2 (en) | 2011-08-29 | 2016-10-18 | Siemens Aktiengesellschaft | Wiring test device for electronics cabinets having internal signal wiring |
| CN103765232A (en) * | 2011-08-29 | 2014-04-30 | 西门子公司 | Wiring test device for electronics cabinets having internal signal wiring |
| CN102426333A (en) * | 2011-10-18 | 2012-04-25 | 山东华翼微电子技术有限责任公司 | All-contact signal testing device for contact type IC (Integrated Circuit) card |
| CN102721839A (en) * | 2012-07-09 | 2012-10-10 | 上海华岭集成电路技术股份有限公司 | Test adaptation board |
| CN103869105A (en) * | 2012-12-11 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | General type test board |
| CN103278763B (en) * | 2013-04-28 | 2016-06-22 | 上海华力微电子有限公司 | The FT test board system of chip and method of testing |
| CN103278763A (en) * | 2013-04-28 | 2013-09-04 | 上海华力微电子有限公司 | Film transistor (FT) test board system and test method of chip |
| CN104281147B (en) * | 2014-10-24 | 2016-08-17 | 上海自仪泰雷兹交通自动化系统有限公司 | A kind of internal signal fault testing apparatus of track traffic signal equipment |
| CN104281147A (en) * | 2014-10-24 | 2015-01-14 | 上海自仪泰雷兹交通自动化系统有限公司 | Internal signal fault testing device for rail transit signal equipment |
| CN106249001A (en) * | 2016-05-05 | 2016-12-21 | 苏州能讯高能半导体有限公司 | A kind of test board |
| CN106249001B (en) * | 2016-05-05 | 2019-06-14 | 苏州能讯高能半导体有限公司 | A kind of test board |
| WO2018068627A1 (en) * | 2016-10-12 | 2018-04-19 | 肖敏 | Apparatus for chip testing and programming, and manufacturing method therefor |
| CN111208323A (en) * | 2018-11-22 | 2020-05-29 | 株式会社Isc | Test socket for testing a device under test |
| CN111579956A (en) * | 2020-04-08 | 2020-08-25 | 上海精密计量测试研究所 | Adjustable surface-mounted packaged semiconductor device clamp and testing method |
| CN113406478A (en) * | 2021-06-23 | 2021-09-17 | 上海电气泰雷兹交通自动化系统有限公司 | Many functional safety hardware test fixture |
| CN114019195A (en) * | 2021-10-29 | 2022-02-08 | 上海华力集成电路制造有限公司 | Chip antistatic performance test board |
| CN116068380A (en) * | 2023-03-01 | 2023-05-05 | 上海聚跃检测技术有限公司 | Chip package testing method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101464490B (en) | 2010-12-22 |
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Granted publication date: 20101222 Termination date: 20181217 |