CN101452957A - Concave grid transistor element construction and producing method - Google Patents
Concave grid transistor element construction and producing method Download PDFInfo
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- CN101452957A CN101452957A CNA2007101962259A CN200710196225A CN101452957A CN 101452957 A CN101452957 A CN 101452957A CN A2007101962259 A CNA2007101962259 A CN A2007101962259A CN 200710196225 A CN200710196225 A CN 200710196225A CN 101452957 A CN101452957 A CN 101452957A
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Abstract
The invention provides a concave-grid transistor element structure, which comprises a concave grid, a source doped region, a drain doped region and an asymmetric grid oxide layer, wherein the concave grid is arranged in a grid ditch in a semiconductor substrate; the concave grid is divided into a vertical sidewall part and a U-shaped bottom; the source doped region is arranged in the semiconductor substrate on one side of the grid ditch; the drain doped region is arranged in the semiconductor substrate on the other side of the grid ditch; the asymmetric grid oxide layer is arranged on the grid ditch between the concave grid and the semiconductor substrate; the asymmetric grid oxide layer has a first thickness between the concave grid and the drain doped region, and has a second thickness between the concave grid and the source doped region; and the first thickness is larger than the second thickness.
Description
Technical field
The present invention relates to a kind of semiconductor component structure and manufacture method, relate in particular to concave grid (recessed-gate) transistor element construction and the manufacture method of a kind of deep channel capacitor (deep trench capacitor) dynamic random access memory (dynamic random accessmemory abbreviates DRAM as).
Background technology
Along with the size of element design is constantly dwindled, transistor gate channel length (gate channellength) shortens the short-channel effect (short channel effect abbreviates SCE as) that is caused and has become the obstacle that semiconductor memery device further promotes integrated level and operation usefulness.
Past, existing people proposed to avoid taking place the method for short-channel effect, for example, reduce the thickness of grid oxic horizon or the doping content of increase raceway groove etc., yet, these methods but may cause problems such as the decline of element reliability or data transfer rate be slack-off simultaneously, and are not suitable for practical application.
For addressing these problems, this field has now gradually adopted the MOS transistor element design of concave grid (recessed-gate), or so-called U type extends channel element (extended U-shapedevice, abbreviate EUD as), use promoting as dynamic random access memory integrated circuit integrated level and usefulness such as (DRAM).
Put source electrode, grid and the drain electrode of formula MOS transistor compared to the traditional water horizontal, so-called concave grid MOS transistor is that grid and drain electrode, source electrode are made in the irrigation canals and ditches that are etched in advance at semiconductor-based the end, and the grid groove zone is arranged on the bottom of these irrigation canals and ditches, thereby form a recessed trench (recessed-channel), reduce the horizontal area of MOS transistor thus, to promote the integrated level of semiconductor element.
Yet, aforesaid concave grid MOS transistor element still has many shortcomings, for example, high grid is to drain electrode (or grid is to source electrode) electric capacity and gate induced drain leakage stream (gate induced drainleakage, abbreviate GIDL as), these all are the reasons that causes element operation usefulness to descend, and therefore need further to improve and improve.
Summary of the invention
Main purpose of the present invention is to provide a kind of concave grid MOS transistor element of improvement, and it has asymmetric grid oxic horizon structure, can effectively improve the operation usefulness and the leakage problem of element.
According to a preferred embodiment of the invention, the present invention discloses a kind of concave grid transistor element construction, include a concave grid, be located at one and be formed in the intrabasement gate trenches of semiconductor, wherein this gate trenches is divided into vertical sidewall part and U type bottom; The one source pole doped region was located in this semiconductor-based end of this gate trenches one side; One drain doping region was located in this semiconductor-based end of this gate trenches opposite side; An and asymmetric grid oxic horizon, on this concave grid and this gate trenches between this semiconductor-based end, wherein this asymmetric grid oxic horizon has one first thickness between this concave grid and this drain doping region, between this concave grid and this source doping region, have one second thickness, and this first thickness is greater than this second thickness.
According to another preferred embodiment, the invention provides a kind of method that forms different-thickness grid oxide layer, including provides the semiconductor substrate, is formed with a gate trenches on it, and wherein this gate trenches is divided into vertical sidewall part and U type bottom; Carry out the rake angle ion implantation technology of single, partly inject first dopant at this one-sided vertical sidewall of this gate trenches; Carry out a vertical ion implantation technology, inject second dopant in this U type bottom of this gate trenches; And carry out a thermal oxidation technology, partly grow a first grid oxide layer in this vertical sidewall that is injected with this first dopant, grow a second grid oxide layer in this U type bottom that is injected with this second dopant simultaneously, wherein this first grid thickness of oxide layer is greater than this second grid thickness of oxide layer.
Foundation is another preferred embodiment again, the invention provides a kind of method that forms different-thickness grid oxide layer, and including provides the semiconductor substrate, is formed with a gate trenches on it, and wherein this gate trenches is divided into vertical sidewall part and U type bottom; Carry out the rake angle ion implantation technology of single, only this one-sided vertical sidewall in this gate trenches partly injects a dopant; Carry out first thermal oxidation technology, partly grow a first grid oxide layer in this vertical sidewall that is injected with this dopant, simultaneously grow a second grid oxide layer, and this first grid thickness of oxide layer is greater than this second grid thickness of oxide layer in other position of this gate trenches; Carry out an etch process, remove this second grid oxide layer on this U type bottom that is positioned at this gate trenches, to expose this semiconductor-based end of part; And carry out one second thermal oxidation technology, on this semiconductor-based end that exposes, grow one the 3rd grid oxic horizon.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred implementation cited below particularly, and conjunction with figs. are described in detail below.Yet following preferred implementation and graphic only for reference and explanation usefulness are not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the generalized section according to the concave grid MOS transistor element that the preferred embodiment of the present invention illustrated.
Fig. 2 is the generalized section of the concave grid MOS transistor element that illustrated according to another preferred embodiment of the present invention.
What Fig. 3 to Fig. 6 illustrated is the preferred embodiment of the present invention forms the method with three kinds of different-thickness grid oxide layers in gate trenches generalized section.
What Fig. 7 to Figure 10 illustrated is the ion implantation technology that the present invention only uses single, cooperates synchronous steaming process, forms the schematic diagram of different thickness grid oxide layers in gate trenches.
The main element symbol description
1 deep channel capacitor DRAM array, 10 concave grid MOS transistor elements
10a concave grid MOS transistor element
11 concave grids, 12 gate trenches
12a vertical sidewall part 12b U type bottom
13 source doping region, 14 drain doping region
15 grid oxic horizon 15a grid oxic horizons
15b grid oxic horizon 15c grid oxic horizon
16 U type raceway grooves, 20 deep channel capacitor structures
22 doped polysilicon layers, 23 sidewall capacitance dielectric layers
24 diffusion zones, 26 single-sided buried conductive strips
Cap rock 40 contact plungers on 30 irrigation canals and ditches
The 100 semiconductor-based ends
Embodiment
See also Fig. 1, it is the generalized section according to the concave grid MOS transistor element that the preferred embodiment of the present invention illustrated.As shown in Figure 1, according to a preferred embodiment of the invention, concave grid MOS transistor element 10 is arranged in the deep channel capacitor DRAM array 1, therefore, such element recessed trench array element (recess channel array device that is otherwise known as, be called for short RCAT), and each concave grid MOS transistor element 10 and a deep channel capacitor structure 20 that is arranged on its close position are formed DRAM unit born of the same parents jointly.
According to a preferred embodiment of the invention, concave grid MOS transistor element 10 includes a concave grid 11, one source pole doped region 13, a drain doping region 14 and a grid oxic horizon 15.Wherein, concave grid 11 is to be embedded in the gate trenches (gate trench) 12 that is etched to desired depth of the semiconductor-based ends 100 1, and concave grid 11 can include polysilicon, metal or its combination.Gate trenches 12 can be divided into vertical sidewall part 12a and U type bottom 12b, and the U type raceway groove 16 of concave grid MOS transistor element 10 promptly is positioned at U type bottom 12b.
Being formed on gate trenches 12 lip-deep grid oxic horizons 15 is formed by boiler tube technology, Rapid Thermal reaction (RTP) technology or similar oxide layer growth technology, but wherein do not comprise synchronous steaming process (in-situ steam generation is called for short ISSG).
According to a preferred embodiment of the invention, deep channel capacitor structure 20 includes a doped polycrystalline silicon (doped polysilicon) layer 22 and one sidewall capacitance dielectric (sidewall capacitor dielectric) layer 23, for example, and the ONO dielectric layer.Doped polysilicon layer 22 is intended for the top electrode of deep channel capacitor structure 20.Be simplified illustration, the buried capacitor bottom electrode of channel capacitor structure 20 (buried plate) is not particularly illustrated among the figure, and only briefly shows the superstructure of channel capacitor structure 20.
In addition, on the top of channel capacitor structure 20, utilize so-called " single-sided buried conductive strips (Single-Sided Buried Strap is called SSBS again) " technology to be formed with single-sided buried conductive strips 26, and cap rock (Trench Top Oxide abbreviates TTO as) 30 on the irrigation canals and ditches.Wherein, cap rock 30 can be that silica constitutes on the irrigation canals and ditches, and for example, (high-densityplasma chemical vapor deposition, HDPCVD) method deposits with high density plasma CVD.
Aforesaid " single-sided buried conductive strips " technology generally includes following step: sidewall capacitance dielectric layer 23 and polysilicon layer (Poly-2) 22 are etched back to one first desired depth, insert another polysilicon layer (Poly-3) again, after etch-back Poly-3 to the second desired depth, on Poly-3, form asymmetric clearance wall, the Poly-3 and the Poly-2 that are not covered of etching then by this clearance wall, at last, insert TTO silica insulating barrier, again with CMP (Chemical Mechanical Polishing) process with the planarization of TTO silica insulating barrier.
Concave grid MOS transistor element 10 is by drain doping region 14, is connected with the diffusion zone 24 that single-sided buried conductive strips 26 via channel capacitor structure 20 extend out out.The path that electronics or electric current are promptly constituted via the source doping region 13 of bit line (figure do not show) by contact plunger 40, concave grid MOS transistor element 10, U type raceway groove 16, drain doping region 14, the diffusion zone 24 opened arrives the top electrode of deep channel capacitor 20, the access action of the line data of going forward side by side.
Technical characterictic of the present invention is that the grid oxic horizon 15 of concave grid MOS transistor element 10 has two kinds of different thickness at least, present a kind of dissymmetrical structure of uniqueness, the grid oxic horizon 15a that wherein thickness is thicker is between the concave grid 11 and drain doping region 14 of concave grid MOS transistor element 10, and the grid oxic horizon 15b of thinner thickness then is between concave grid 11 and source doping region 13.
Grid oxic horizon 15b extends downwardly into U type bottom 12b from the vertical sidewall part 12a of gate trenches 12 close source doping region 13 1 sides.According to a preferred embodiment of the invention, the thickness of grid oxic horizon 15a is approximately between 150 dust to 300 dusts, and the thickness of grid oxic horizon 15b is approximately between 20 dust to 60 dusts.
Thicker grid oxic horizon 15a can reduce concave grid MOS transistor element 10 when operation, in the concave grid 11 shown in the circled 50, drain doping region 14 and the semiconductor-based ends 100 three caused gate induced drain leakage stream of high electric field (GIDL) that the place produces that has a common boundary, simultaneously, owing to the asymmetric structure of grid oxic horizon 15, can keep or improve the operation usefulness of concave grid MOS transistor element 10 on the other hand.
See also Fig. 2, it wherein, is still continued to use identical symbol and represents the components identical position for the generalized section of the concave grid MOS transistor element that illustrated according to another preferred embodiment of the present invention.As shown in Figure 2, concave grid MOS transistor element 10a includes a concave grid 11, one source pole doped region 13, a drain doping region 14 and a grid oxic horizon 15 equally.
Wherein, concave grid 11 is to be embedded in the gate trenches 12 that is etched to desired depth of the semiconductor-based ends 100 1.Gate trenches 12 can be divided into vertical sidewall part 12a and U type bottom 12b, and the U type raceway groove 16 of concave grid MOS transistor element 10 is positioned at U type bottom 12b.
Deep channel capacitor structure 20 includes a doped polysilicon layer 22 and a sidewall capacitance dielectric layer 23.Doped polysilicon layer 22 is intended for the top electrode of deep channel capacitor structure 20.Be simplified illustration, the buried capacitor bottom electrode of channel capacitor structure 20 is not particularly illustrated among the figure, and only briefly shows the superstructure of channel capacitor structure 20.Concave grid MOS transistor element 10a and DRAM unit born of the same parents of deep channel capacitor structure 20 common compositions.
Grid oxic horizon 15 has three kinds of different thickness, present asymmetric structure, the grid oxic horizon 15a that wherein thickness is the thickest is between concave grid 11 and drain doping region 14, and thickness time thick grid oxic horizon 15b then is between concave grid 11 and source doping region 13.The thinnest grid oxic horizon 15c is positioned at U type bottom 12b.
According to a preferred embodiment of the invention, the thickness of grid oxic horizon 15a is approximately between 150 dust to 300 dusts, and the thickness of grid oxic horizon 15b is approximately between 80 dust to 120 dusts, and the thickness of grid oxic horizon 15c is approximately between 20 dust to 60 dusts.
See also Fig. 3 to Fig. 6, what it illustrated is the preferred embodiment of the present invention forms the method with three kinds of different-thickness grid oxide layers in gate trenches generalized section, wherein, still continues to use identical symbol and represents the components identical position.At first, as shown in Figure 3, on the semiconductor-based end 100, form a deep channel capacitor structure 20, include a doped polysilicon layer 22 and a sidewall capacitance dielectric layer 23.Then, on the semiconductor-based end 100, form a gate trenches 12, comprise vertical sidewall part 12a and U type bottom 12b.
As shown in Figure 4, carry out the rake angle ion implantation technology of single, on the close vertical sidewall part 12a of deep channel capacitor structure 20, inject the argon ion of predetermined concentration.Then, as shown in Figure 5, carry out the ion implantation technology of single, on the 12b of the U of deep channel capacitor structure 20 type bottom, inject the nitrogen ion of predetermined concentration.Certainly, the ion implantation technology of Fig. 4 and Fig. 5 goes up in proper order and can exchange.
Then, as shown in Figure 6, carry out a thermal oxidation technology, be preferably boiler tube or Rapid Thermal reaction (RTP) technology, in gate trenches 12, grow the grid oxic horizon 15 of different-thickness, wherein, the oxide layer growth speed of vertical sidewall part 12a in thermal oxidation technology that is injected with argon ion is the fastest, and it is the slowest to be injected with the U type bottom oxide layer growth speed of 12b in thermal oxidation technology of nitrogen ion, therefore, finally can obtain three kinds of different thickness, present asymmetric structure.
Wherein, grid oxic horizon 15a thickness is the thickest, and it is the thinnest to be positioned at bottom the U type grid oxic horizon 15c of 12b, and the thickness of grid oxic horizon 15b is then between grid oxic horizon 15a and grid oxic horizon 15c.Because U type bottom 12b is injected with the nitrogen ion, therefore the grid oxic horizon 15c of U type bottom 12b formation the most finally is nitrogen doped silicon oxide (nitrogen-doped silicon oxide).
Herein, be noted that aforesaid thermal oxidation technology does not comprise synchronous steaming process (ISSG), this is because steaming process can be not selective in oxidizing process for the semiconductor-based basal surface that is injected with dopant synchronously, therefore can not produce the difference of oxidation rate.Therefore, at the described technology of Fig. 3 to Fig. 6, synchronous steaming process also is not suitable for.
In addition, utilize ion implantation technology to make equally and inject the principle that dopant causes the alienation of oxide layer growth speed difference in the gate trenches 12, the present invention can also form the grid oxic horizon 15 of different-thickness by injecting the nitrogen ion of variable concentrations.For example, primary ion implantation technology is adopted vertical mode in the higher nitrogen ion of U type bottom 12b implantation concentration, carries out the rake angle ion implantation technology of single subsequently, the lower nitrogen ion of implantation concentration on the monolateral vertical sidewall 12a of gate trenches 12.
Then, carry out oxidation technology.At this moment, the oxide layer growth speed of the U type bottom 12b of the nitrogen ion that implantation concentration is higher is the slowest, therefore grow the thinnest oxide layer, and the oxide layer growth speed of the monolateral vertical sidewall 12a of the lower nitrogen ion of implantation concentration is taken second place, and the oxide layer growth speed of vertical sidewall 12a of not injecting dopant is the fastest, so can obtain the grid oxic horizon 15 of three kinds of different thickness equally, and present asymmetric structure.
See also Fig. 7 to Figure 10, the present invention can also cooperate synchronous steaming process only with the ion implantation technology of single, forms the grid oxic horizon of three kinds of different thickness in gate trenches.At first, as shown in Figure 7, on the semiconductor-based end 100, form a deep channel capacitor structure 20, include a doped polysilicon layer 22 and a sidewall capacitance dielectric layer 23.Then, on the semiconductor-based end 100, form a gate trenches 12, comprise vertical sidewall part 12a and U type bottom 12b.Then, carry out the rake angle ion implantation technology of single, on the close vertical sidewall part 12a of deep channel capacitor structure 20, inject the argon ion of predetermined concentration.
As shown in Figure 8, carry out the thermal oxidation technology first time, for example boiler tube or Rapid Thermal reaction process, in gate trenches 12, grow the grid oxic horizon 15a and the 15b of different-thickness, wherein, the oxide layer growth speed of vertical sidewall part 12a in thermal oxidation technology that is injected with argon ion is the fastest, form thicker grid oxic horizon 15a, and the vertical sidewall part 12a of the U type that is not injected into bottom 12b and opposite side, oxide layer growth speed in thermal oxidation technology is relatively slow, so can obtain the grid oxic horizon 15a and the 15b of two kinds of different-thickness, and be similarly dissymmetrical structure.
As shown in Figure 9, then carry out an anisotropic dry etch technology, the grid oxic horizon 15b on the 12b of U type bottom is removed, expose the semiconductor-based end 100 of part.At last, as shown in figure 10, carry out the thermal oxidation technology second time,, grow a grid oxic horizon 15c at the semiconductor-based end 100 that in gate trenches 12, is exposed as synchronous steaming process.So only use the ion implantation technology of single, just can in gate trenches 12, obtain the grid oxic horizon 15 of three kinds of different thickness equally, and present asymmetric structure.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (17)
1. concave grid transistor element construction includes:
Concave grid is located at and is formed in the intrabasement gate trenches of semiconductor, and wherein this gate trenches comprises sidewall sections, and the U type bottom that is linking this sidewall sections;
Source doping region was located in this semiconductor-based end of this gate trenches one side;
Drain doping region is located at this gate trenches in this semiconductor-based end with respect to this source doping region opposite side; And
Asymmetric grid oxic horizon is on this concave grid and this gate trenches between this semiconductor-based end.
2. concave grid transistor element construction as claimed in claim 1, wherein this asymmetric grid oxic horizon has first thickness between this concave grid and this drain doping region, has second thickness between this concave grid and this source doping region.
3. concave grid transistor element construction as claimed in claim 2, wherein this first thickness is greater than this second thickness.
4. concave grid transistor element construction as claimed in claim 2, wherein between this U type bottom of this concave grid bottom surface and gate trenches, this asymmetric grid oxic horizon has the 3rd thickness.
5. method that forms oxide layer in irrigation canals and ditches includes:
The semiconductor-based end is provided, is formed with irrigation canals and ditches on it, wherein these irrigation canals and ditches are divided into sidewall sections and U type bottom;
Inject the part of first dopant in this sidewall; And
Generate first oxide layer in this sidewall sections that is injected with this first dopant, and, generate second oxide layer in the opposing sidewalls place of this sidewall sections.
6. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 5, wherein this first oxidated layer thickness is greater than this second oxidated layer thickness.
7. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 5, wherein, the method for injecting this first dopant comprises the rake angle ion implantation technology.
8 methods that form oxide layer in irrigation canals and ditches as claimed in claim 7, wherein this first dopant includes argon ion.
9. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 5 wherein also comprises after generating this second oxide layer:
Remove this second oxide layer that is generated on this U type bottom; And
Go up generation the 3rd oxide layer in this U type bottom.
10. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 9, wherein the 3rd oxidated layer thickness is less than this second oxidated layer thickness.
11. a method that forms oxide layer in irrigation canals and ditches includes:
The semiconductor-based end is provided, is formed with irrigation canals and ditches on it, wherein these irrigation canals and ditches are divided into sidewall sections and U type bottom;
Inject first dopant in the part of this sidewall;
Inject second dopant in this U type bottom; And
Carry out thermal oxidation technology, generate first oxide layer, generate second oxide layer, and inject U type bottom generation the 3rd oxide layer of this second dopant in this sidewall sections that does not inject this first dopant in this sidewall sections that is injected with this first dopant.
12. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 11, wherein the 3rd thickness of oxide layer is less than this second thickness of oxide layer.
13. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 12, wherein this second thickness of oxide layer is less than this first thickness of oxide layer.
14. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 11 wherein comprises the rake angle ion implantation technology in the method that the part of this sidewall is injected this first dopant.
15. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 14, wherein this first dopant includes argon ion.
16. the method that forms oxide layer in irrigation canals and ditches as claimed in claim 14, wherein this second dopant includes the nitrogen ion.
17. a concave grid oxide layer structure comprises:
Gate trenches is arranged at at semiconductor-based the end, and this gate trenches has sidewall sections and U type bottom; And
Grid oxic horizon is covered in this semiconductor irrigation canals and ditches surface, and this grid oxic horizon that wherein is covered in this sidewall sections has uneven gauge.
18. concave grid oxide layer structure as claimed in claim 17, wherein this grid oxic horizon thickness of being covered in this U type bottom is different from the thickness that covers this sidewall sections.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102903748A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Lateral double-diffused metal oxide semiconductor (DMOS) and manufacturing method thereof |
| CN108475679A (en) * | 2015-12-22 | 2018-08-31 | 瓦里安半导体设备公司 | The non-homogeneous gate-oxide thicknesses of DRAM elements |
| CN109216359A (en) * | 2017-07-04 | 2019-01-15 | 华邦电子股份有限公司 | Memory device and its manufacturing method |
| CN112635545A (en) * | 2020-12-18 | 2021-04-09 | 华南师范大学 | Enhanced GaN-based MIS-HEMT with asymmetric gate dielectric layer and preparation method thereof |
| CN114743880A (en) * | 2022-04-12 | 2022-07-12 | 上海晶岳电子有限公司 | Power semiconductor groove size control method and power semiconductor structure |
| CN118173505A (en) * | 2024-05-14 | 2024-06-11 | 杭州积海半导体有限公司 | Method for preparing semiconductor structure and semiconductor structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6437386B1 (en) * | 2000-08-16 | 2002-08-20 | Fairchild Semiconductor Corporation | Method for creating thick oxide on the bottom surface of a trench structure in silicon |
| TW591756B (en) * | 2003-06-05 | 2004-06-11 | Nanya Technology Corp | Method of fabricating a memory cell with a single sided buried strap |
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- 2007-11-30 CN CN2007101962259A patent/CN101452957B/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102903748A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Lateral double-diffused metal oxide semiconductor (DMOS) and manufacturing method thereof |
| CN102903748B (en) * | 2011-07-25 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of lateral double diffusion metal oxide semiconductor and manufacture method thereof |
| CN108475679A (en) * | 2015-12-22 | 2018-08-31 | 瓦里安半导体设备公司 | The non-homogeneous gate-oxide thicknesses of DRAM elements |
| CN109216359A (en) * | 2017-07-04 | 2019-01-15 | 华邦电子股份有限公司 | Memory device and its manufacturing method |
| CN112635545A (en) * | 2020-12-18 | 2021-04-09 | 华南师范大学 | Enhanced GaN-based MIS-HEMT with asymmetric gate dielectric layer and preparation method thereof |
| CN112635545B (en) * | 2020-12-18 | 2022-05-31 | 华南师范大学 | Enhanced GaN-based MIS-HEMT with asymmetric gate dielectric layer and preparation method thereof |
| CN114743880A (en) * | 2022-04-12 | 2022-07-12 | 上海晶岳电子有限公司 | Power semiconductor groove size control method and power semiconductor structure |
| CN114743880B (en) * | 2022-04-12 | 2023-06-06 | 上海晶岳电子有限公司 | Power semiconductor groove size control method and power semiconductor structure |
| CN118173505A (en) * | 2024-05-14 | 2024-06-11 | 杭州积海半导体有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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