CN101452957B - Concave grid transistor element construction and producing method - Google Patents

Concave grid transistor element construction and producing method Download PDF

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Publication number
CN101452957B
CN101452957B CN 200710196225 CN200710196225A CN101452957B CN 101452957 B CN101452957 B CN 101452957B CN 200710196225 CN200710196225 CN 200710196225 CN 200710196225 A CN200710196225 A CN 200710196225A CN 101452957 B CN101452957 B CN 101452957B
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oxide layer
trench
gate
thickness
dopant
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CN101452957A (en
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吴铁将
李中元
林正平
王哲麒
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南亚科技股份有限公司
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Abstract

The invention provides a concave-grid transistor element structure, which comprises a concave grid, a source doped region, a drain doped region and an asymmetric grid oxide layer, wherein the concave grid is arranged in a grid ditch in a semiconductor substrate, the grid ditch is divided into a vertical sidewall part and a U-shaped bottom; the source doped region is arranged in the semiconductor substrate on one side of the grid ditch; the drain doped region is arranged in the semiconductor substrate on the other side of the grid ditch; the asymmetric grid oxide layer is arranged on the grid ditch between the concave grid and the semiconductor substrate; the asymmetric grid oxide layer has a first thickness between the concave grid and the drain doped region, a second thickness between the concave grid and the source doped region, and a third thickness between the bottom surface of the concave grid and the U-shaped bottom of the grid ditch, and the first thickness is larger than the second thickness, the second thickness is larger than the third thickness.

Description

凹入式栅极晶体管元件结构及制作方法 Recessed gate structure and a method of manufacturing a transistor device

技术领域 FIELD

[0001] 本发明涉及一种半导体元件结构及制作方法,尤其涉及一种深沟渠电容(de印trench capacitor)动态随机存取存储器(dynamic random accessmemory,简称为DRAM) 的凹入式栅极(recessed-gate)晶体管元件结构及制作方法。 [0001] The present invention relates to a structure and method for manufacturing a semiconductor device, particularly to a deep trench capacitor (de printed trench capacitor) dynamic random access memory (dynamic random accessmemory, simply referred to as DRAM) is recessed gate (recessed -Gate) structure and manufacturing method of the transistor element.

背景技术 Background technique

[0002] 随着元件设计的尺寸不断缩小,晶体管栅极沟道长度(gate channel length)缩短所引发的短沟道效应(short channel effect,简称为SCE)已成为半导体存储器元件进一步提升集成度及操作效能的障碍。 [0002] With the design element the dimensions shrink, the gate of the transistor channel length (gate channel length) shortening effect caused by the short channel (short channel effect, referred to as SCE) has been further enhanced degree of integration of the semiconductor memory device, and obstacles to the effectiveness of the operation.

[0003] 过去已有人提出避免发生短沟道效应的方法,例如,减少栅极氧化层的厚度或是增加沟道的掺杂浓度等,然而,这些方法却可能同时造成元件可靠度的下降或是数据传送速度变慢等问题,并不适合实际应用。 [0003] Past methods have been proposed to avoid the occurrence of the short channel effect, e.g., to reduce the thickness of the gate oxide layer to increase the doping concentration of the channel or the like, however, these methods but may also cause decreased reliability or element data transfer rate is slow and other issues, not suitable for practical applications.

[0004] 为解决这些问题,该领域现已逐渐采用凹入式栅极(recessed-gate)的MOS晶体管元件设计,或所谓的U型延伸沟道元件(extended U-shapedevice,简称为EUD),藉以提升如动态随机存取存储器(DRAM)等集成电路集成度以及效能。 [0004] To solve these problems, the art has been gradually adopted recessed gate (recessed-gate) MOS transistor element design, or a so-called U-shaped channel extending member (extended U-shapedevice, referred to as the EUD), in order to enhance dynamic random access memory (DRAM) integrated circuits such integration and performance.

[0005] 相较于传统水平置放式MOS晶体管的源极、栅极与漏极,所谓的凹入式栅极MOS晶体管是将栅极与漏极、源极制作于预先蚀刻在半导体基底中的沟渠中,并且将栅极沟道区域设置在该沟渠的底部,从而形成一凹入式沟道(recessed-charmel),由此降低MOS晶体管的横向面积,以提升半导体元件的集成度。 [0005] Compared to the conventional horizontal placement of the source type MOS transistor, a gate and a drain, a so-called gate of the MOS transistor is a recessed gate and the drain, a source previously fabricated in a semiconductor substrate etching the trenches, and the gate channel region is disposed at the bottom of the trench, thereby forming a recessed channel (recessed-charmel), thereby reducing the lateral area of ​​the MOS transistor, to improve integration of the semiconductor element.

[0006] 然而,前述的凹入式栅极MOS晶体管元件仍有诸多缺点,例如,高栅极对漏极(或栅极对源极)电容及栅极引发漏极漏电流(gate induced drainleakage,简称为GIDL),这些都是导致元件操作效能下降的原因,因此需要进一步改善及改进。 [0006] However, the above-described recessed gate MOS transistor element are still many shortcomings, for example, a high gate-to-drain (or a gate-to-source) capacitance and the gate-induced drain leakage (gate induced drainleakage, referred to as the GIDL), these are the causes of performance degradation of the operating element, and thus further improvement improvement.

发明内容 SUMMARY

[0007] 本发明的主要目的在于提供一种改良的凹入式栅极MOS晶体管元件,其具有不对称的栅极氧化层结构,可以有效改善元件的操作效能以及漏电流问题。 [0007] The main object of the present invention to provide an improved recessed gate MOS transistor element, a gate oxide layer has an asymmetrical structure can effectively improve the operating performance and the leakage current of the element.

[0008] 根据本发明的优选实施例,本发明披露一种凹入式栅极晶体管元件结构,包括有一凹入式栅极,设于一形成在一半导体基底内的栅极沟渠中,其中该栅极沟渠分为一垂直侧壁部分以及一U型底部;一源极掺杂区,设于该栅极沟渠一侧的该半导体基底内;一漏极掺杂区,设于该栅极沟渠另一侧的该半导体基底内;及一不对称的栅极氧化层,介于该凹入式栅极与该半导体基底之间的该栅极沟渠上,其中该不对称的栅极氧化层于该凹入式栅极与该漏极掺杂区之间具有一第一厚度,于该凹入式栅极与该源极掺杂区之间具有一第二厚度,于该凹入式栅极底面和栅极沟渠的该U型底部之间具有第三厚度,且该第一厚度大于该第二厚度,该第二厚度大于该第三厚度。 [0008] According to a preferred embodiment of the present invention, the present invention discloses a recessed gate transistor device structure including a recessed gate electrode, provided in a trench formed on the gate in a semiconductor substrate, wherein the a vertical sidewall of the gate trench is divided into a bottom portion and a U-shaped; in the semiconductor substrate a dopant source region, provided on the side of the gate trench; a doped drain region provided to the gate trench the other side of the semiconductor substrate; and an asymmetric gate oxide layer, the gate trench interposed between the recessed gate and the semiconductor substrate, wherein the gate oxide layer in asymmetric the recessed gate between the drain doped region having a first thickness at the recessed gate region having a second thickness between the doped source and gate to the concave having a third thickness between the bottom and the bottom of the U-shaped trench of the gate, and the first thickness is greater than the second thickness, the second thickness is greater than the third thickness.

[0009] 依据另一优选实施例,本发明提供一种形成不同厚度栅极氧化层的方法,包括有提供一半导体基底,其上形成有一栅极沟渠,其中该栅极沟渠分为一垂直侧壁部分以及一U型底部;进行单次的斜角度离子注入工艺,在该栅极沟渠的单侧的该垂直侧壁部分注入第一掺杂剂;进行一垂直的离子注入工艺,在该栅极沟渠的该U型底部注入第二掺杂剂;及进行一热氧化工艺,于注入有该第一掺杂剂的该垂直侧壁部分长出一第一栅极氧化层,同时于注入有该第二掺杂剂的该U型底部长出一第二栅极氧化层,其中该第一栅极氧化层的厚度大于该第二栅极氧化层的厚度。 [0009] According to a further preferred embodiment, the present invention provides a method of forming different thicknesses of the gate oxide layer, comprising providing a semiconductor substrate, on which a gate trench, wherein the gate trench is divided into a vertical side U-shaped wall portion, and a bottom portion; for miter single ion implantation process, dopant is implanted in a first portion of one side of the vertical sidewall of the gate trench; performing a vertical ion implantation process, on the gate a second dopant of the bottom of the U-shaped trench electrode implantation; and performing a thermal oxidation process, there is the injection of the vertical sidewall portion of the first dopant is grown a first gate oxide layer, while the injection has the U-shaped bottom of the second dopant to grow a second gate oxide layer, wherein the thickness of the first gate oxide layer is greater than a thickness of the second gate oxide layer.

[0010] 依据又另一优选实施例,本发明提供一种形成不同厚度栅极氧化层的方法,包括有提供一半导体基底,其上形成有一栅极沟渠,其中该栅极沟渠分为一垂直侧壁部分以及一U型底部;进行单次的斜角度离子注入工艺,仅于该栅极沟渠的单侧的该垂直侧壁部分注入一掺杂剂;进行第一热氧化工艺,于注入有该掺杂剂的该垂直侧壁部分长出一第一栅极氧化层,同时于该栅极沟渠的其它部位长出一第二栅极氧化层,且该第一栅极氧化层的厚度大于该第二栅极氧化层的厚度;进行一蚀刻工艺,去除位于该栅极沟渠的该U型底部上的该第二栅极氧化层,以暴露出部分的该半导体基底;及进行一第二热氧化工艺,于暴露出的该半导体基底上长出一第三栅极氧化层。 [0010] In accordance with yet another preferred embodiment, the present invention provides a method different thickness of gate oxide layer is formed, comprising providing a semiconductor substrate, on which a gate trench, wherein the gate trench is divided into a vertical side wall portions and a U-shaped bottom; for miter single ion implantation process, only one side of the vertical sidewall portion of the gate trench a dopant implantation; a first thermal oxidation process, there is the injection the vertical sidewall portion of the first dopant to grow a gate oxide layer, while other portions of the gate trench grow a second gate oxide layer and the thickness of the gate oxide layer is greater than the first the thickness of the second gate oxide layer; and performing an etching process, removing the second gate oxide layer on the bottom of the U-shaped trench of the gate, in order to expose a portion of the semiconductor substrate; and performing a second a thermal oxidation process, a third gate oxide layer is grown on the exposed semiconductor substrate.

[0011] 为让本发明的上述目的、特征、和优点能更明显易懂,下文特举优选实施方式,并配合附图,作详细说明如下。 [0011] In order to make the above-described object of the present invention, features, and advantages can be more fully understood by reading the following preferred embodiment accompanied with figures are described in detail below. 然而如下的优选实施方式与图式仅供参考与说明用,并非用来对本发明加以限制。 However, the following preferred embodiment and the drawings and described with reference only, not intended to limit the present invention.

附图说明 BRIEF DESCRIPTION

[0012] 图1为依据本发明优选实施例所绘示的凹入式栅极MOS晶体管元件的剖面示意图。 [0012] FIG. 1 is a schematic cross-sectional view of the embodiment depicted recessed gate of the MOS transistor device according to a preferred embodiment of the present invention.

[0013] 图2为依据本发明另一优选实施例所绘示的凹入式栅极MOS晶体管元件的剖面示意图。 [0013] FIG. 2 is a schematic cross-sectional view according to the recessed gate MOS transistor element illustrated according to another preferred embodiment of the present invention.

[0014] 图3至图6绘示的是本发明优选实施例在栅极沟渠中形成具有三种不同厚度栅极氧化层的方法的剖面示意图。 [0014] Figures 3 to 6 are schematic cross-sectional schematic diagram of a method having three different thicknesses of the gate oxide layer is formed in the gate trench preferred embodiments of the present invention.

[0015] 图7至图10绘示的是本发明仅用单次的离子注入工艺,配合同步蒸汽法,在栅极沟渠内形成不同的厚度栅极氧化层的示意图。 [0015] FIG. 7 to FIG. 10 is a schematic diagram of the present invention with only a single ion implantation process, steam with the synchronization method, a schematic view of the different thickness of gate oxide layer formed within the gate trench.

[0016] 主要元件符号说明 [0016] Main reference numerals DESCRIPTION

[0017] 1深沟渠电容DRAM阵列 10凹入式栅极MOS晶体管元件 [0017] The deep trench capacitor DRAM array 1 10 recessed gate MOS transistor element

[0018] IOa凹入式栅极MOS晶体管元件 [0018] IOa recessed gate MOS transistor element

[0019] 11凹入式栅极 12栅极沟渠 [0019] 11 recessed gate 12 of the gate trench

[0020] 12a垂直侧壁部分 12bU型底部 [0020] 12a sidewall portion of the bottom of the vertical type 12bU

[0021] 13源极掺杂区 14漏极掺杂区 [0021] 13 doped source region 14 doped drain region

[0022] 15栅极氧化层 15a栅极氧化层 [0022] gate oxide layer 15 gate oxide layer 15a

[0023] 15b栅极氧化层 15c栅极氧化层 [0023] 15b of the gate oxide layer 15c gate oxide layer

[0024] 16U型沟道 20深沟渠电容结构 [0024] 16U-channel deep trench capacitor structure 20

[0025] 22掺杂多晶硅层 23侧壁电容介电层 [0025] 22 side wall 23 of the doped polysilicon layer capacitor dielectric layer

[0026] 24扩散区域 26单边埋入导电带 [0026] diffusion region 24 is embedded unilaterally conductive tape 26

[0027] 30沟渠上盖层 40接触插塞 [0027] The trench 30 on the cap layer 40 contact plug

[0028] 100半导体基底具体实施方式 [0028] The semiconductor substrate 100 DETAILED DESCRIPTION

[0029] 请参阅图1,其为依据本发明优选实施例所绘示的凹入式栅极MOS晶体管元件的剖面示意图。 [0029] Referring to FIG. 1, which is a schematic cross-sectional view of the embodiment depicted recessed gate MOS transistor device according to a preferred embodiment of the present invention. 如图1所示,根据本发明的优选实施例,凹入式栅极MOS晶体管元件10是设置在一深沟渠电容DRAM阵列1中,因此,这样的元件又被称为凹入式沟道阵列元件(recess channel array device,简称RCAT),而每一个凹入式栅极MOS晶体管元件10与一个设置在其邻近位置的深沟渠电容结构20,共同组成一个DRAM单元胞。 1, according to a preferred embodiment of the present invention, the recessed gate MOS transistor element 10 is provided in a deep trench capacitor DRAM array 1, and therefore, such an element is also known as an array of recessed channel element (recess channel array device, referred to as the RCAT), and each gate of the MOS transistor is a recessed member 10 and the deep trench capacitor structure is disposed adjacent a position 20, together constitute a DRAM unit cells.

[0030] 根据本发明的优选实施例,凹入式栅极MOS晶体管元件10包括有一凹入式栅极11、一源极掺杂区13、一漏极掺杂区14以及一栅极氧化层15。 [0030] According to a preferred embodiment of the present invention, the recessed gate MOS transistor element 10 includes a recessed gate 11, a source region 13 doping, a doped drain region 14 and a gate oxide layer 15. 其中,凹入式栅极11是嵌入于蚀刻至半导体基底100 —预定深度的栅极沟渠(gate trench) 12内,且凹入式栅极11 可以包括有多晶硅、金属或者其组合。 Wherein the recessed gate 11 is embedded in the semiconductor substrate is etched to 100-- predetermined depth of the gate trench (gate trench) 12, and a recessed gate 11 may include polysilicon, metal or combinations thereof. 栅极沟渠12可分为垂直侧壁部分12a以及U型底部12b,而凹入式栅极MOS晶体管元件10的U型沟道16即位于U型底部12b。 The gate trench 12 may be divided into a vertical side wall 12a and the U-shaped bottom portion 12b, and the gate of the MOS transistor recessed element 16 of the U-shaped channel 10 that is U-shaped at the bottom 12b.

[0031] 形成在栅极沟渠12表面上的栅极氧化层15可以是由炉管技术、快速热反应(RTP)工艺或类似的氧化层生长技术所形成,但其中不包括同步蒸汽法(in-situ steam generation,简禾尔ISSG)。 Gate oxide layer [0031] formed on the surface 15 of the gate trench 12 may be formed by a tube, rapid thermal reactor (RTP) process or the like of oxide layer growth technique, but does not include a synchronization process steam (in -situ steam generation, Jane Wo Seoul ISSG).

[0032] 根据本发明的优选实施例,深沟渠电容结构20包括有一掺杂多晶硅(doped polysilicon)层22 以及一侧壁电容介电(sidewall capacitor dielectric)层23,例如, 0N0介电层。 [0032] According to a preferred embodiment of the present invention, deep trench capacitor structure 20 includes a doped polysilicon (doped polysilicon) layer 22, and a capacitor dielectric sidewall (sidewall capacitor dielectric) layer 23, e.g., a dielectric layer 0n0. 掺杂多晶硅层22是用来作为深沟渠电容结构20的上电极。 Doped polysilicon upper electrode layer 22 is used as a deep trench capacitor structure 20. 为简化说明,沟渠电容结构20的埋入式电容下电极(buried plate)并未特别显示在图中,而仅简要显示沟渠电容结构20的上部构造。 To simplify the description, the trench capacitor structure 20 embedded capacitor electrode (buried plate) is not particularly shown in the figures, briefly showing only the upper structure 20 of the trench capacitor structure.

[0033] 此外,在沟渠电容结构20的上部,利用所谓的“单边埋入导电带(Single-Sided Buried Strap,又称为SSBS)”工艺形成有单边埋入导电带26,以及沟渠上盖层(Trench Top Oxide,简称为TT0) 30。 [0033] Further, the upper portion 20 of the trench capacitor structure, a so-called "buried-sided conductive tape (Single-Sided Buried Strap, also known as SSBS)" with a process of forming a buried conductive sided tape 26, and the trench caprock (Trench Top Oxide, referred to as TT0) 30. 其中,沟渠上盖层30可以是氧化硅所构成,例如,以高密度等离子体化学气相沉积(high-densityplasma chemical vapor d印osition,HDPCVD)法所沉积。 Wherein the trench cap layer 30 may be formed of silicon oxide, e.g., a high density plasma chemical vapor deposition (high-densityplasma chemical vapor d printing osition, HDPCVD) method deposited.

[0034] 前述的“单边埋入导电带”工艺通常包括有以下的步骤:将侧壁电容介电层23以及多晶硅层(Poly_2)22回蚀刻至一第一预定深度,再填入另一多晶硅层(Poly_3),回蚀刻Poly-3至第二预定深度后,在Poly-3上形成不对称的间隙壁,然后蚀刻未被该间隙壁覆盖的Poly-3以及Poly-2,最后,填入TTO硅氧绝缘层,再以化学机械抛光工艺将TTO硅氧绝缘层平坦化。 [0034] The above-described "unilateral buried conductive tape" process generally comprises the steps of: the sidewall capacitance of the dielectric layer 23 and a polysilicon layer (Poly_2) 22 is etched back to a first predetermined depth, then fill the other polysilicon layer (Poly_3), poly-3 after etch-back to a second predetermined depth, forming spacers on asymmetric poly-3, and then etching the spacer not covered by the poly-3 and poly-2, and finally, to fill TTO silicone into the insulating layer, and then a chemical mechanical polishing process TTO silicone insulating layer is planarized.

[0035] 凹入式栅极MOS晶体管元件10是通过漏极掺杂区14,与经由沟渠电容结构20的单边埋入导电带26外扩出来的扩散区域24相连接。 Diffusion region [0035] The gate of the MOS transistor recessed element 10 is 14, and the buried conductive via sided trench capacitor structure 20 through the outer band 26 out of the doped drain region 24 is connected to expansion. 电子或者电流即经由位线(图未示) 通过接触插塞40、凹入式栅极MOS晶体管元件10的源极掺杂区13、开启的U型沟道16、漏极掺杂区14、扩散区域24所构成的路径到达深沟渠电容20的上电极,并进行数据的存取动作。 I.e. electrons or current through the bit line (not shown) through a contact plug 40, the gate of the MOS transistor source recessed element 10 doping region 13, the open U-shaped channel 16, the drain region 14 doped, diffusion region 24 constituting the path reaches the deep trench capacitor upper electrode 20, and the data access operation.

[0036] 本发明的技术特征在于凹入式栅极MOS晶体管元件10的栅极氧化层15至少具有两种不同的厚度,呈现出一种独特的不对称结构,其中厚度较厚的栅极氧化层15a位于凹入式栅极MOS晶体管元件10的凹入式栅极11与漏极掺杂区14之间,而厚度较薄的栅极氧化层15b则是位于凹入式栅极11与源极掺杂区13之间。 [0036] The technical features of the present invention is that the gate oxide layer is recessed gate of the MOS transistor 15 of the element 10 having at least two different thicknesses, it presents a unique asymmetric, wherein the gate oxide is thicker layer 15a is located in the recessed gate recessed gate of the MOS transistor 11 and the element 10 between the doped drain region 14, and a thin gate oxide layer 15b is located in the recessed gate 11 and the source 13 between the doping region.

[0037] 栅极氧化层15b从栅极沟渠12靠近源极掺杂区13 —侧的垂直侧壁部分12a向下延伸到U型底部12b。 [0037] gate oxide layer 15b from the gate trench 12 near the source region 13 doping - Vertical side wall portion 12a extends down to the bottom side of the U-12b. 根据本发明的优选实施例,栅极氧化层15a的厚度约介于150埃至300埃之间,而栅极氧化层15b的厚度约介于20埃至60埃之间。 According to a preferred embodiment of the present invention, the thickness of the gate oxide layer 15a is between about 150 angstroms to 300 angstroms, and the thickness of the gate oxide layer 15b is between about 20 angstroms to 60 angstroms.

[0038] 较厚的栅极氧化层15a可以降低凹入式栅极MOS晶体管元件10在操作时,于圆圈处50所示的凹入式栅极11、漏极掺杂区14与半导体基底100三者交界处所产生的高电场所引起的栅极引发漏极漏电流(GIDL),同时,由于栅极氧化层15的不对称的结构,另一方面可以维持或改善凹入式栅极MOS晶体管元件10的操作效能。 [0038] The thicker gate oxide layer 15a can be reduced recessed gate MOS transistor element 10 is in operation, the recessed gate shown in a circle at 5011, the drain doped regions 14 and the semiconductor substrate 100 three gate high electric field generated at the junction due to induced drain leakage (the GIDL), at the same time, due to the asymmetrical structure of the gate oxide layer 15, on the other hand can be maintained or improved recessed gate MOS transistor Efficiency of operation of device 10.

[0039] 请参阅图2,其为依据本发明另一优选实施例所绘示的凹入式栅极MOS晶体管元件的剖面示意图,其中,仍沿用相同的符号来表示相同的元件部位。 [0039] Please refer to FIG. 2, which is a cross-sectional view of the embodiment depicted recessed gate of the MOS transistor device according to another preferred embodiment of the present invention, a schematic diagram, which is still in use by the same reference numerals denote the same elements site. 如图2所示,凹入式栅极MOS晶体管元件IOa同样包括有一凹入式栅极11、一源极掺杂区13、一漏极掺杂区14以及一栅极氧化层15。 As shown in FIG. 2, the recessed gate MOS transistor also comprises a member IOa recessed gate 11, a source region 13 doping, a doped drain region 14 and a gate oxide layer 15.

[0040] 其中,凹入式栅极11是嵌入于蚀刻至半导体基底100 —预定深度的栅极沟渠12 内。 [0040] wherein the recessed gate 11 is embedded in the semiconductor substrate 100 is etched to a - 12 a predetermined depth of the gate trench. 栅极沟渠12可分为垂直侧壁部分12a以及U型底部12b,而凹入式栅极MOS晶体管元件10的U型沟道16位于U型底部12b。 The gate trench 12 may be divided into a vertical side wall 12a and the U-shaped bottom portion 12b, and the gate of the MOS transistor recessed element 16 of the U-shaped channel 10 at the bottom of the U-shaped 12b.

[0041] 深沟渠电容结构20包括有一掺杂多晶硅层22以及一侧壁电容介电层23。 [0041] The deep trench capacitor structure 20 includes a doped polysilicon layer 22, and a capacitor dielectric layer 23 sidewalls. 掺杂多晶硅层22是用来作为深沟渠电容结构20的上电极。 Doped polysilicon upper electrode layer 22 is used as a deep trench capacitor structure 20. 为简化说明,沟渠电容结构20的埋入式电容下电极并未特别显示在图中,而仅简要显示沟渠电容结构20的上部构造。 To simplify the description, the trench capacitor structure embedded capacitor electrode 20 is not particularly shown in the figures, briefly showing only the upper structure 20 of the trench capacitor structure. 凹入式栅极MOS晶体管元件IOa与深沟渠电容结构20共同组成一个DRAM单元胞。 Recessed gate MOS transistor element IOa and deep trench capacitor structure 20 together form a DRAM unit cells.

[0042] 栅极氧化层15具有三种不同的厚度,呈现出不对称的结构,其中厚度最厚的栅极氧化层15a位于凹入式栅极11与漏极掺杂区14之间,而厚度次厚的栅极氧化层15b则是位于凹入式栅极11与源极掺杂区13之间。 [0042] The gate oxide layer 15 having three different thicknesses, exhibits an asymmetric structure, wherein the thickness of the thick gate oxide layer 15a is positioned between the recessed gate 14 and drain 11 doped region, and times the thickness of thick gate oxide layer 15b is located in the recessed gate 11 and the source doped region 13 between. 最薄的栅极氧化层15c位于U型底部12b。 Thinnest gate oxide layer 15c of the U-shaped bottom 12b.

[0043] 根据本发明的优选实施例,栅极氧化层15a的厚度约介于150埃至300埃之间,栅极氧化层15b的厚度约介于80埃至120埃之间,而栅极氧化层15c的厚度约介于20埃至60埃之间。 [0043] According to a preferred embodiment of the present invention, the thickness of the gate oxide layer 15a is between about 150 angstroms to 300 angstroms, the thickness of the gate oxide layer 15b is between about 80 angstroms to 120 angstroms, and the gate the thickness of the oxide layer 15c is between about 20 angstroms to 60 angstroms.

[0044] 请参阅图3至图6,其绘示的是本发明优选实施例在栅极沟渠中形成具有三种不同厚度栅极氧化层的方法的剖面示意图,其中,仍沿用相同的符号来表示相同的元件部位。 [0044] Please refer to FIG. 3 to FIG. 6, which illustrates a cross-sectional schematic view of the method have three different thicknesses of the gate oxide layer is formed in the gate trench preferred embodiment of the present invention, wherein the same symbols are still in use refer to the same elements site. 首先,如图3所示,于半导体基底100上形成一深沟渠电容结构20,包括有一掺杂多晶硅层22以及一侧壁电容介电层23。 First, as shown, a deep trench capacitor structure 20 is formed on the semiconductor substrate 1003, a doped polysilicon layer includes a sidewall 22 and a capacitor dielectric layer 23. 接着,在半导体基底100上形成一栅极沟渠12,包括垂直侧壁部分12a以及U型底部12b。 Next, a gate trench 12 is formed, including a vertical sidewall portions 12a and 12b in the U-shaped bottom portion 100 on the semiconductor substrate.

[0045] 如图4所示,进行单次的斜角度离子注入工艺,在较靠近深沟渠电容结构20的垂直侧壁部分12a上注入预定浓度的氩离子。 [0045] As shown in FIG. 4, a single miter ion implantation process, the predetermined concentration of argon ions implanted in the vertical side wall portion 12a closer to the deep trench capacitor structure 20. 接着,如图5所示,进行单次的离子注入工艺, 在深沟渠电容结构20的U型底部12b上注入预定浓度的氮离子。 Subsequently, as shown in FIG 5, a single ion implantation process, the predetermined concentration of nitrogen ions implanted in the deep trench capacitor structure of the U-shaped bottom 12b 20. 当然,图4以及图5的离子注入工艺顺序上可以对调。 Of course, FIGS. 4 and 5 the ion implantation process, can be switched on sequentially.

[0046] 然后,如图6所示,进行一热氧化工艺,优选为炉管或快速热反应(RTP)工艺,在栅极沟渠12内长出不同厚度的栅极氧化层15,其中,注入有氩离子的垂直侧壁部分12a在热氧化工艺中的氧化层成长速率最快,而注入有氮离子的U型底部12b在热氧化工艺中的氧化层成长速率最慢,因此,最终可以得到三种不同的厚度,呈现出不对称的结构。 [0046] Then, as shown in FIG. 6, a thermal oxidation process, preferably a thermal reaction tube or rapid (RTP) process, grown gate oxide layers of different thicknesses of the gate electrode 15 in trench 12, wherein the injection a vertical sidewall portion of the argon ions growth rate of the oxide layer 12a in a thermal oxidation process is the fastest, while the grown oxide layer 12b implanted with nitrogen ions rate U-shaped bottom in a thermal oxidation process is the slowest, thus eventually obtained Three different thickness, exhibits an asymmetric structure.

[0047] 其中,栅极氧化层15a厚度最厚,而位于U型底部12b的栅极氧化层15c最薄,栅极氧化层15b的厚度则介于栅极氧化层15a与栅极氧化层15c之间。 [0047] wherein the thickness of the gate oxide layer 15a is thickest, and the gate oxide layer at the bottom of the U-shaped 12b 15c thinnest thickness of the gate oxide layer 15b is interposed between the gate oxide layer 15a and the gate oxide layer 15c between. 由于U型底部12b注入有氮离子,因此最终于U型底部12b形成的栅极氧化层15c为氮掺杂氧化硅(nitrogen-dopedsilicon oxide)0 Since the U-shaped bottom portion 12b implanted with nitrogen ions, so the final gate oxide layer 12b is formed on the bottom of the U-shaped 15c is a nitrogen-doped silicon oxide (nitrogen-dopedsilicon oxide) 0

[0048] 此处,要注意的是前述的热氧化工艺并不包括同步蒸汽法(ISSG),这是因为同步蒸汽法对于注入有掺杂剂的半导体基底表面在氧化过程中不会有选择性,因此不会产生氧化速率的差异。 [0048] Here, it is noted that the foregoing thermal oxidation process steam does not include a synchronization method (the ISSG), because there are synchronization steaming method for implanting a dopant in the semiconductor substrate surface not selective oxidation process , so that no difference in oxidation rate. 因此,针对图3至图6所描述的工艺,同步蒸汽法并不适合。 Thus, for the process described in FIG. 6 to FIG. 3, the synchronization process is not suitable for steam.

[0049] 此外,同样利用离子注入工艺使栅极沟渠12内注入掺杂剂导致氧化层成长速率差异化的原理,本发明亦可以通过注入不同浓度的氮离子,来形成不同厚度的栅极氧化层15。 [0049] In addition, the same ion implantation process using the gate trench 12 is injected into the lead oxide dopant layer grown differentiated rate principles, the present invention also may be formed with different thicknesses of gate oxide by implantation of nitrogen ions at different concentrations layer 15. 例如,第一次的离子注入工艺采垂直方式于U型底部12b注入浓度较高的氮离子,随后进行单次的斜角度离子注入工艺,在栅极沟渠12的单边垂直侧壁12a上注入浓度较低的氮罔子。 For example, an ion implantation process first embodiment taken perpendicular to the bottom of the U-type high concentration 12b nitrogen ion implantation, followed by a single oblique angle ion implantation process, unilateral injection on the vertical sidewalls of the gate trench 12a 12 of lower concentrations of nitrogen sub indiscriminately.

[0050] 接着,进行氧化工艺。 [0050] Next, an oxidation process. 此时,注入浓度较高的氮离子的U型底部12b的氧化层成长速率最慢,因此长出最薄的氧化层,而注入浓度较低的氮离子的单边垂直侧壁12a的氧化层成长速率次之,而未注入掺杂剂的垂直侧壁12a的氧化层成长速率最快,如此同样可以得到三种不同的厚度的栅极氧化层15,而呈现出不对称的结构。 At this time, the growth rate of the oxide layer of the U-shaped bottom portion 12b of the high concentration of implanted nitrogen ions slowest, and therefore grow thinnest oxide layer and a lower concentration of implanted nitrogen ions unilateral vertical sidewall oxide layer 12a growth rate, followed by dopant implantation without vertical sidewall oxide layer 12a fastest growth rate, thus obtained may also be three different gate oxide thickness of 15, while showing an asymmetric structure.

[0051] 请参阅图7至图10,本发明亦可以仅用单次的离子注入工艺,配合同步蒸汽法,在栅极沟渠内形成三种不同的厚度的栅极氧化层。 [0051] Please refer to FIG. 7 to FIG. 10, the present invention can also be only a single ion implantation process, steam with the synchronization method, three kinds of gate oxide layer is formed of a different thickness in the gate trench. 首先,如图7所示,于半导体基底100上形成一深沟渠电容结构20,包括有一掺杂多晶硅层22以及一侧壁电容介电层23。 First, as shown in FIG 7, a deep trench capacitor structure 20 is formed on the semiconductor substrate 100, a doped polysilicon layer includes a sidewall 22 and a capacitor dielectric layer 23. 接着,在半导体基底100上形成一栅极沟渠12,包括垂直侧壁部分12a以及U型底部12b。 Next, a gate trench 12 is formed, including a vertical sidewall portions 12a and 12b in the U-shaped bottom portion 100 on the semiconductor substrate. 然后,进行单次的斜角度离子注入工艺,在较靠近深沟渠电容结构20的垂直侧壁部分12a上注入预定浓度的氩离子。 Then, a single miter ion implantation process, the predetermined concentration of argon ions implanted in the vertical side wall portion 12a closer to the deep trench capacitor structure 20.

[0052] 如图8所示,进行第一次热氧化工艺,例如炉管或快速热反应工艺,在栅极沟渠12 内长出不同厚度的栅极氧化层15a及15b,其中,注入有氩离子的垂直侧壁部分12a在热氧化工艺中的氧化层成长速率最快,形成较厚的栅极氧化层15a,而未被注入的U型底部12b 以及另一侧的垂直侧壁部分12a,在热氧化工艺中的氧化层成长速率相对较慢,如此可以得到两种不同厚度的栅极氧化层15a及15b,且同样为不对称结构。 [0052] As shown in FIG. 8, a first thermal oxidation process, such as furnace or rapid thermal reaction process tube, grown gate oxide layers of different thicknesses 15a and 15b in the gate trench 12, wherein the argon is injected vertical sidewall portion 12a of ion oxide layer grown at the rate of the fastest thermal oxidation process, forming a thick gate oxide layer 15a, but not the vertical sidewalls of the U-shaped bottom portion 12b of the injection and the other side portion 12a, oxide layer is grown at the rate of the thermal oxidation process is relatively slow, thus obtained two different gate oxide layer thicknesses 15a and 15b, and likewise asymmetrical structure.

[0053] 如图9所示,接着进行一各向异性干蚀刻工艺,将U型底部12b上的栅极氧化层15b去除,暴露出部分的半导体基底100。 [0053] As shown in FIG. 9, followed by an anisotropic dry etching process, the gate oxide layer on the bottom of the U-shaped 12b 15b is removed, exposing a portion of the semiconductor substrate 100. 最后,如图10所示,进行第二次热氧化工艺,如同步蒸汽法,在栅极沟渠12内被暴露出来的半导体基底100上长出一栅极氧化层15c。 Finally, as shown in FIG. 10, a second thermal oxidation process, such as synchronization steaming method, a gate oxide layer 15c grown on the semiconductor substrate 100 is exposed within the gate trench 12. 如此仅使用单次的离子注入工艺,便同样可以在栅极沟渠12内得到三种不同的厚度的栅极氧化层15,而呈现出不对称的结构。 Thus the use of only a single ion implantation process, they can also obtain three different thicknesses of the gate oxide layer 15 in the gate trench 12, while showing an asymmetric structure.

[0054] 以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。 [0054] The above are only preferred embodiments of the present invention, all modifications and alterations made under this invention as claimed in claim, also belong to the scope of the present invention.

Claims (11)

1. 一种凹入式栅极晶体管元件结构,包括有:凹入式栅极,设于形成在半导体基底内的栅极沟渠中,其中该栅极沟渠包括侧壁部分, 以及连结着该侧壁部分的U型底部;源极掺杂区,设于该栅极沟渠一侧的该半导体基底内;漏极掺杂区,设于该栅极沟渠相对于该源极掺杂区另一侧的该半导体基底内;及不对称的栅极氧化层,介于该凹入式栅极与该半导体基底之间的该栅极沟渠上, 其中该不对称的栅极氧化层于该凹入式栅极与该漏极掺杂区之间具有第一厚度,于该凹入式栅极与该源极掺杂区之间具有第二厚度,于该凹入式栅极底面和栅极沟渠的该U型底部之间具有第三厚度,且该第一厚度大于该第二厚度,该第二厚度大于该第三厚度。 A recessed gate transistor device structure, comprising: a recessed gate electrode, a gate disposed in the trench formed in the semiconductor substrate, wherein the trench gate includes a side wall portion, and the side connected to the within the semiconductor substrate doped source region, provided on one side of the gate trench;; the bottom wall portion of the U-type doped drain region, provided on the other side of the gate trench with respect to the source region doping within the semiconductor substrate; a gate oxide layer and the asymmetric, between the gate trench between the recessed gate and the semiconductor substrate, wherein the asymmetric gate oxide layer on the concave a first gate electrode having a thickness between the drain and the doping region, having a second thickness between the recessed gate electrode and the source region dopant at the bottom surface of the recessed gate and the gate trench having a third thickness between the bottom of the U-shaped, and the first thickness is greater than the second thickness, the second thickness is greater than the third thickness.
2. 一种在沟渠内形成氧化层的方法,包括有:提供半导体基底,其上形成有沟渠,其中该沟渠分为侧壁部分以及U型底部; 注入第一掺杂剂于该侧壁的一部分;生成第一氧化层于注入有该第一掺杂剂的该侧壁部分,以及于该侧壁部分的相对侧壁处和U型底部上,生成第二氧化层,其中该第一氧化层厚度大于该第二氧化层厚度; 移除该U型底部上所生成的该第二氧化层;以及于该U型底部上生成第三氧化层。 2. A method for forming an oxide layer within the trench, comprising: providing a semiconductor substrate with a trench formed thereon, wherein the trench is divided into a bottom portion and a U-shaped side wall; a first dopant is implanted in the side wall portion; generating a first oxide layer on the sidewall portion of the injection with a first dopant, and on the opposite side walls and a bottom of the U-shaped sidewall portion, generating a second oxide layer, wherein the first oxide the layer thickness is greater than the thickness of the second oxide layer; removing the second oxide layer on the bottom of the U-shaped generated; and generating a third oxide layer on the U-shaped bottom.
3.如权利要求2所述的在沟渠内形成氧化层的方法,其中,注入该第一掺杂剂的方法包括斜角度离子注入工艺。 The method of forming an oxide layer within the trench as claimed in claim 2, wherein the first implanted dopant comprising miter ion implantation process.
4.如权利要求3所述的在沟渠内形成氧化层的方法,其中该第一掺杂剂包括有氩离子。 4. The method of forming an oxide layer within the trench as claimed in claim 3, wherein the first dopant comprises argon ions.
5.如权利要求2所述的在沟渠内形成氧化层的方法,其中该第三氧化层厚度小于该第二氧化层厚度。 5. The method of forming an oxide layer within the trench as claimed in claim 2, wherein the third oxide layer is less than the thickness of the second oxide layer.
6. 一种在沟渠内形成氧化层的方法,包括有:提供半导体基底,其上形成有沟渠,其中该沟渠分为侧壁部分以及U型底部; 于该侧壁的一部分注入第一掺杂剂; 于该U型底部注入第二掺杂剂;以及进行热氧化工艺,于注入有该第一掺杂剂的该侧壁部分生成第一氧化层,于未注入该第一掺杂剂的该侧壁部分生成第二氧化层,而注入该第二掺杂剂的U型底部生成第三氧化层。 A method for forming an oxide layer in a trench, comprising: providing a semiconductor substrate, on which the trench, wherein the trench is divided into a bottom portion and a U-shaped sidewall; a portion of the sidewall of the first dopant implantation agent; in the bottom of the U-shaped implanting a second dopant; and performing a thermal oxidation process, in the sidewall portion of the injected first dopant generating a first oxide layer on the first non-implanted dopant generating a second portion of the sidewall oxide layer, the third oxide layer is injected to generate the U-shaped bottom of the second dopant.
7.如权利要求6所述的在沟渠内形成氧化层的方法,其中该第三氧化层的厚度小于该第二氧化层的厚度。 7. The method of forming an oxide layer within the trench as claimed in claim 6, wherein the thickness of the third oxide layer is less than the thickness of the second oxide layer.
8.如权利要求7所述的在沟渠内形成氧化层的方法,其中该第二氧化层的厚度小于该第一氧化层的厚度。 8. A method of forming an oxide layer within the trench claimed in claim 7, wherein the thickness of the second oxide layer is smaller than the thickness of the first oxide layer.
9.如权利要求6所述的在沟渠内形成氧化层的方法,其中于该侧壁的一部分注入该第一掺杂剂的方法包括斜角度离子注入工艺。 9. The method of forming an oxide layer within the trench to claim 6, wherein a portion of the sidewall of the implanted first dopant comprising miter ion implantation process.
10.如权利要求9所述的在沟渠内形成氧化层的方法,其中该第一掺杂剂包括有氩离子。 10. The method of forming an oxide layer within the trench as claimed in claim 9, wherein the first dopant comprises argon ions.
11.如权利要求9所述的在沟渠内形成氧化层的方法,其中该第二掺杂剂包括有氮离子。 11. The method of forming an oxide layer within the trench as claimed in claim 9, wherein the second dopant comprises nitrogen ions.
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