CN101452058A - Semiconductor integrated circuit device and battery pack - Google Patents

Semiconductor integrated circuit device and battery pack Download PDF

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Publication number
CN101452058A
CN101452058A CNA2008101830273A CN200810183027A CN101452058A CN 101452058 A CN101452058 A CN 101452058A CN A2008101830273 A CNA2008101830273 A CN A2008101830273A CN 200810183027 A CN200810183027 A CN 200810183027A CN 101452058 A CN101452058 A CN 101452058A
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clock
battery
integrated circuit
circuit device
pattern
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CNA2008101830273A
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CN101452058B (en
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板垣孝俊
阿部真喜男
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Mitsumi Electric Co Ltd
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Mitsumi Electric Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/392—Determining battery ageing or deterioration, e.g. state of health
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/396—Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/05—Accumulators with non-aqueous electrolyte
    • H01M10/052—Li-accumulators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Electrochemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Sources (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Tests Of Electric Status Of Batteries (AREA)
  • Secondary Cells (AREA)

Abstract

The invention aims to provide a semiconductor integrated circuit device and battery set, which can set various action patterns with difference current sinking, can decrease current sinking corresponding to the connection state or action state of battery-using devices and can determine the battery surplus. The semiconductor integrated circuit device uses batteries as an electric power source, and has the function of determining the battery surplus and then transmitting to the battery-using devices using the batteries as and electric power source. The semiconductor integrated circuit device has: clocking generating units (21, 23) generating a first clock and a second clock having a frequency greater than that of the first clock; a selecting unit (24) selecting one of the first clock and the second clock outputted by the clock generating units to output; an arithmetic unit (12) for arithmetic according to the clock performing action outputted by the selecting unit for the battery surplus; and a communication unit (16) for transmitting the battery surplus calculated by the arithmetic unit to the battery-using devices according to the clock performing action outputted by the selecting unit.

Description

Conductor integrated circuit device and electric battery
Technical field
The present invention relates to conductor integrated circuit device and electric battery, relate to possessing to have and obtain conductor integrated circuit device and the electric battery that residual capacity of battery sends to the function of battery use equipment then.
Background technology
Lithium ion battery has been provided in the portable battery use equipment such as mobile phone, digital camera in recent years.Lithium ion battery generally is difficult to according to its voltage detecting residual capacity of battery.Therefore, take the charging and discharging currents of battery is added up, measure the method for residual capacity of battery.
At present, developed and be used to use above-mentioned method to measure the fuel quantity ga(u)ge IC of residual capacity of battery, the built-in CPU of this fuel quantity ga(u)ge IC, storer etc., convert detected charging and discharging currents to numerical data and add up computing, counting cell surplus thus, and the residual capacity of battery that calculates is sent to batteries such as mobile phone, digital camera by telecommunication circuit and use equipment.
Though fuel quantity ga(u)ge IC is used to measure residual capacity of battery, fuel quantity ga(u)ge IC itself provides action power by lithium ion battery, therefore need reduce the current sinking of fuel quantity ga(u)ge IC as far as possible.
In patent documentation 1, put down in writing the mode determination that residual capacity of battery is set in the control model of data processing unit, in mode determination, carried out the supplying electric current from battery is restricted to minimum control, realized power saving.
[patent documentation 1] spy opens the 2005-12960 communique
Summary of the invention
Existing fuel quantity ga(u)ge IC is except normal mode, only has the " shut " mode" that when long-term the placement, clock is stopped or cutting off the electricity supply, existence can't be used the connection status of equipment or the operating state reduction current sinking that battery uses equipment by corresponding battery, also can't obtain do not connecting the problem that battery uses the electric current surplus under the long-term laying state of equipment.
The present invention proposes in view of the above problems, its purpose is to provide can set the different exercises pattern of current sinking, can use the connection status of equipment or operating state to reduce current sinking by corresponding battery, and can obtain the conductor integrated circuit device and the electric battery of residual capacity of battery.
The conductor integrated circuit device of an embodiment of the present invention, with battery as power supply, and have and obtain residual capacity of battery and send to the function of using equipment with described battery as the battery of power supply then, it has: clock generation unit (21,23), and it generates first clock and the frequency second clock greater than described first clock; Selected cell (24), it selects first clock of described clock generation unit output and some output the in the second clock; Arithmetic element (12), its clock according to described selected cell output moves described residual capacity of battery is carried out computing; And communication unit (16), its clock according to described selected cell output moves, the residual capacity of battery that described arithmetic element is calculated sends to described battery use equipment, thus, can set the different pattern of current sinking, can use the connection status of equipment or operating state to reduce current sinking by corresponding battery, and can obtain residual capacity of battery.
In described conductor integrated circuit device, can have setup unit (12,22,25, S1～S6), this setup unit is set first pattern that makes described arithmetic element (12) action and second pattern that described arithmetic element (12) is stopped.
In described conductor integrated circuit device, described clock generation unit (21,23) can have second oscillator (23) of the second clock of first oscillator (21) that generates first clock and generation and described first clock synchronization.
In described conductor integrated circuit device, described clock generation unit (21,23) can have first oscillator (21) of generation first clock and second oscillator (23) of generation and the asynchronous second clock of described first clock.
In described conductor integrated circuit device, can have the timing unit (15) that the clock according to the output of described selected cell moves, carries out timing under described second pattern.
In described conductor integrated circuit device, described setup unit (S1～S6), can use the connection status and the operating state of equipment to carry out the switching of described first pattern and described second pattern according to described battery.
The electric battery of an embodiment of the present invention, the conductor integrated circuit device and the described battery that possess above-mentioned a certain mode, can set the different exercises pattern of current sinking thus, can use the connection status of equipment or operating state to reduce current sinking according to battery, and can obtain residual capacity of battery.
In described conductor integrated circuit device, can have setup unit (12,22,25, S11～S16), the four-mode that the timing unit (15) that its setting makes the three-mode of described arithmetic element (12) action and makes described arithmetic element (12) stop only to use the clock of described selected cell output to carry out timing moves
Described clock generation unit has first oscillator (41) that generates first clock and second oscillator (23) that generates second clock,
Described first oscillator (41) with respect to the frequency of first clock that generates, is reduced in the frequency of first clock that generates under the described four-mode under described three-mode.
In described conductor integrated circuit device, described timing unit (15) can make described setup unit move to described three-mode using described first clock to carry out timing through the stipulated time time under the described four-mode.
In described conductor integrated circuit device, described timing unit (15) can freely change the described stipulated time.
In addition, the reference marks in the above-mentioned bracket is added in order to understand easily, and only an example is not limited to illustrated state.
Description of drawings
Fig. 1 is the frame assumption diagram of an embodiment of conductor integrated circuit device of the present invention.
Fig. 2 is the state transition diagram of conductor integrated circuit device.
Fig. 3 is the process flow diagram of an embodiment of pattern hand-off process.
Fig. 4 is the key diagram of mode switch.
Fig. 5 has been to use the stereographic map of an embodiment of the electric battery of conductor integrated circuit device of the present invention.
Fig. 6 is the frame assumption diagram of other embodiments of conductor integrated circuit device of the present invention.
Fig. 7 is the circuit structure diagram of an embodiment of variable oscillation circuit.
Fig. 8 is the state transition diagram of conductor integrated circuit device shown in Figure 6.
Fig. 9 is the process flow diagram of other embodiments of pattern hand-off process.
Figure 10 is the key diagram of mode switch.
Symbol description
10, fuel quantity ga(u)ge functional module; 11 mimic channel portions; 12 CPU; 13 ROM; 14 RAM; 15 timing portions; 16 Department of Communication Forces; 21,23,41 oscillatory circuits; 22 pattern registers; 24 clock selectors; 25 modules stop register; 30 electric battery; 31 batteries; 32 SIC (semiconductor integrated circuit)
Embodiment
(structure of conductor integrated circuit device)
Fig. 1 represents the frame assumption diagram of an embodiment of conductor integrated circuit device of the present invention.In the figure, be provided with mimic channel portion 11, CPU12, ROM13, RAM14, timing portion 15, Department of Communication Force 16 in fuel quantity ga(u)ge functional module 10, they do not interconnect by there being illustrated internal bus.
Be provided with mimic channels such as voltage sensor, temperature sensor, current sensor, AD converter in mimic channel portion 11, the detected value of each sensor carries out digitizing by AD converter, offers CPU12 via internal bus.
CPU12 carries out the various softwares store in ROM13, the charging and discharging currents of the lithium ion battery that current sensor senses is gone out adds up computing, comes the residual capacity of battery of computing lithium ion battery thus.In addition, the detected value of voltage sensor and temperature sensor is used to carry out various corrections, and the operating area when RAM14 carries out processing as CPU12 also comprises the EEPROM as nonvolatile memory in ROM13.
Timing portion 15 has to comprise interrupts using timer at interior various timer with timer and timing, and the signal that these timers generate for example is provided for CPU12 as look-at-me, Measuring Time.Department of Communication Force 16, the corresponding requirement of using equipment to provide from batteries such as mobile phone, digital cameras via communication terminal 17, the residual capacity of battery that CPU12 is calculated via communication terminal 17 sends to battery use equipment.
Oscillatory circuit 21 is indicated the vibration corresponding with pattern by pattern register 22 or is stopped, and for example produces the low-speed clock that frequency is 38.4kHz according to the indication of vibrating, and offers oscillatory circuit 23 and clock selector 24 then.
Oscillatory circuit 23, for example be built-in with PLL, by the pattern register 22 indications frequency corresponding with pattern, producing with coming for example frequency of the clock synchronization of self-oscillating circuit 21 is some high speed clocks of 5MHz/2.5MHz/1.25MHz, offers clock selector 24 then.
In addition, also the clock that can oscillatory circuit 21 not exported offers oscillatory circuit 23, and oscillatory circuit 21,23 is moved asynchronously.
Clock selector 24 is by 22 indications and the corresponding clock selecting of pattern of pattern register, select some in low-speed clock and a plurality of high speed clock, offer mimic channel portion 11, CPU12, ROM13, RAM14, timing portion 15, Department of Communication Force 16 in the fuel quantity ga(u)ge module 10 respectively.
Above-mentioned pattern register 22 is set pattern by CPU12, serves as to trigger the change action pattern with CPU12 fill order (sleep commands).In addition, CPU12 stops in the register 25 setting the permission that mimic channel portion 11, timing portion 15, Department of Communication Force 16 clock separately accepts or forbids in module, the signal that the clock that module stops register 25 and provides indication to set to mimic channel portion 11, timing portion 15, Department of Communication Force 16 is respectively accepted permission or forbidden.Thus, mimic channel portion 11, timing portion 15, Department of Communication Force 16 only when being instructed to clock acceptance permission, are just accepted the clock that provides from clock selector 24.
(state transition)
Fig. 2 represents the state transition of SIC (semiconductor integrated circuit) shown in Figure 1.In the figure, become aggressive mode (at a high speed) ACH by resetting apparatus.Afterwards, by the setting of pattern register 22 and the execution of sleep commands, for aggressive mode (middling speed) ACM, carry out reciprocal migration by the setting of pattern register 22 and the execution of sleep commands from aggressive mode (at a high speed) ACH migration.And,, for sub-aggressive mode SAC, in addition, carry out reciprocal migration by the setting of pattern register 22 and the execution of sleep commands from aggressive mode (middling speed) ACM migration by the setting of pattern register 22 and the execution of sleep commands.
Aggressive mode (at a high speed) ACH is the clock of CPU12 according to frequency 5MHz, pattern with high-speed execution, the clock of the frequency 5MHz that clock selector 24 is selected offers each one of fuel quantity ga(u)ge functional module 10, and the instruction simulation circuit part 11, timing portion 15, the Department of Communication Force 16 that stop register 25 according to module are accepted clock to move at a high speed.
Aggressive mode (middling speed) ACM is the clock of CPU12 according to frequency 2.5MHz or 1.25MHz, pattern with the middling speed executive routine, frequency 2.5MHz that clock selector 24 is selected or the clock of 1.25MHz offer each one of fuel quantity ga(u)ge functional module 10, and the instruction simulation circuit part 11, timing portion 15, the Department of Communication Force 16 that stop register 25 according to module are accepted clock and moved with middling speed.
Sub-aggressive mode SAC is the clock of CPU12 according to frequency 38.4kMHz, pattern with the low speed executive routine, the clock of the frequency 38.4kHz that clock selector 24 is selected offers each one of fuel quantity ga(u)ge functional module 10, and the instruction simulation circuit part 11, timing portion 15, the Department of Communication Force 16 that stop register 25 according to module are accepted clock and moved with low speed.
In addition, respectively from aggressive mode (at a high speed) ACH, aggressive mode (middling speed) ACM, sub-aggressive mode SAC, by the setting of pattern register 22 and the execution of sleep commands, migration is sleep pattern (at a high speed) SLH, sleep pattern (middling speed) SLM, sub-sleep pattern SSL, carries out reciprocal migration by the generation that program interrupt or timer interrupt.
Sleep pattern (at a high speed) SLH is that CPU12 stops action, stops the indication of register 25 according to module, and mimic channel portion 11, timing portion 15, Department of Communication Force 16 are accepted the pattern that the clock of the frequency 5MHz that selected by clock selector 24 moves.
Sleep pattern (middling speed) SLM is that CPU12 stops action, stop the indication of register 25 according to module, mimic channel portion 11, timing portion 15, Department of Communication Force 16 are accepted the pattern that the clock of the frequency 2.5MHz that selected by clock selector 24 or 1.25MHz moves.
Sub-sleep pattern SSL is that CPU12 stops action, stops the indication of register 25 according to module, and mimic channel portion 11, timing portion 15, Department of Communication Force 16 are accepted the pattern that the clock of the frequency 38.4kHz that selected by clock selector 24 moves.
In addition, from aggressive mode (at a high speed) ACH, aggressive mode (middling speed) ACM, sub-aggressive mode SAC, by the setting of pattern register 22 and the execution of sleep commands, migration is monitoring mode WTC, software standby mode SSB respectively, carries out reciprocal migration by the generation that program interrupt or timer interrupt.
Monitoring mode WTC is that CPU12 stops action, stops the indication of register 25 according to module, and only timing portion 15 accepts the pattern that the clock of the frequency 38.4kHz that selected by clock selector 24 moves.
Software standby mode SSB is that CPU12 stops, and stops instruction simulation circuit part 11, timing portion 15, Department of Communication Force 16 whole patterns that stop of moving of register 25 according to module.
In addition, in monitoring mode WTC, software standby mode SSB, mimic channel portion 11, RAM14 pattern register 22, module stop register 25 etc. and keep separately internal state under the situation about stopping moving.
Therefore, can in timing portion 15, carry out timing under the monitoring mode WTC to the time of keeping monitoring mode WTC, revert to aggressive mode (at a high speed) ACH, aggressive mode (middling speed) ACM, sub-aggressive mode SAC from monitoring mode WTC after, can hold time according to monitoring mode by CPU12 and infer the charging and discharging currents of lithium ion battery.
(pattern switching)
Fig. 3 represents the process flow diagram of an embodiment of the pattern hand-off process that CPU12 carries out.In addition, when this handles beginning, aggressive mode (at a high speed) ACH or aggressive mode (middling speed) ACM have been preestablished.
In the figure, CPU12 in step S1 according to the frequency of kind, state or the request of the request of using equipment that Department of Communication Force 16 is provided from battery, judge that battery uses equipment whether to be connected with the electric battery that possesses self device (conductor integrated circuit device), battery uses equipment whether to be in operating state, and battery uses equipment whether to be in the function stop state.
For example, if battery uses equipment to be connected with electric battery, then the voltage of communication terminal 17 is the regulation grade, use the connection of equipment so can judge battery, if battery uses equipment as operating state then the frequency of asking is higher than setting, the frequency of asking if battery use equipment is in the function stop state is lower than setting, so can acts of determination state/function stop state.
In step S2, judge according to result of determination battery uses equipment whether to be in operating state, when battery use equipment is in operating state, in step S3, pattern is set at initiatively (at a high speed) ACH or aggressive mode (middling speed) ACM.
On the other hand, when in step S2, using equipment to be not operating state according to the result of determination battery, judge in step S4 battery uses equipment whether to be the function stop state, when battery use equipment is in the function stop state, pattern is switched to sleep pattern (at a high speed) SLH or sleep pattern (middling speed) SLM at step S5.After switching, this, for example interrupts reverting to original aggressive mode (at a high speed) ACH or aggressive mode (middling speed) ACM or sub-aggressive mode SAC according to timer when through after the stipulated time.
And, in step S4, when battery uses equipment not to be the function stop state, i.e. when battery use equipment is not connected with electric battery, in step S6, pattern switched to sub-aggressive mode SAC or sub-sleep pattern SSL or monitoring mode WTC.After this sub-sleep pattern SSL or monitoring mode WTC switching, when through the stipulated time, for example interrupt reverting to original aggressive mode (at a high speed) ACH or aggressive mode (middling speed) ACM or sub-aggressive mode SAC according to timer.
Will in above-mentioned steps S3, set among aggressive mode (at a high speed) ACH or aggressive mode (middling speed) ACM which? will in step S5, switch among sleep pattern (at a high speed) SLH or sleep pattern (middling speed) SLM which? will and in step S6, switch among sub-aggressive mode SAC or sub-sleep pattern SSL or the monitoring mode WTC which? by the user be predetermined and EEPROM in ROM13 in configure.
But, use equipment to be connected at battery with electric battery, when battery uses equipment to be not operating state, shown in Fig. 4 (A), can make aggressive mode (at a high speed) ACH (or aggressive mode (middling speed) ACM) is stipulated time T1, making sleep pattern (at a high speed) SLH (or sleep pattern (middling speed) SLM) is stipulated time T2, repeats such setting.
In addition, when battery use equipment was not connected with electric battery, shown in Fig. 4 (B), can make aggressive mode (at a high speed) ACH (or aggressive mode (middling speed) ACM or sub-aggressive mode SAC) was stipulated time T1, making monitoring mode WTC is stipulated time T3, repeats such setting.As mentioned above, corresponding battery uses the state of equipment to use which pattern, and the user can freely set.
So, corresponding battery uses the connection status and the operating state of equipment, if battery uses equipment as operating state then for example set aggressive mode, if battery use equipment is not operating state then for example is made as sleep pattern, if not connecting battery uses equipment then for example is made as monitoring mode, thus, just current sinking can be reduced, the residual capacity of battery that does not connect under the long-term laying state of battery use equipment can be obtained.
(electric battery)
Fig. 5 represents to use the stereographic map of an embodiment of the electric battery of conductor integrated circuit device of the present invention.In the figure, the structure of electric battery 30 is for having held battery 31 and conductor integrated circuit device 32 in housing 33.Battery 31 is lithium ion batteries, is connected with conductor integrated circuit device 32 shown in Figure 1 by splicing ear 34a, 34b.
In addition, the outside terminal 35a, the 35b that are provided with on housing 33 are connected with negative pole with the positive pole of battery 31, and outside terminal 35c is connected with the communication terminal 17 of conductor integrated circuit device 32.
In addition, in the above-described embodiment, used aggressive mode, used sleep pattern or monitoring mode as an example of second pattern as an example of first pattern.
(other embodiments)
Fig. 6 represents the frame assumption diagram of other embodiments of conductor integrated circuit device of the present invention.In the figure, give identical symbol for the part identical with Fig. 1.Be provided with mimic channel portion 11, CPU12, ROM13, RAM14, timing portion 15, Department of Communication Force 16 in fuel quantity ga(u)ge functional module 10, they interconnect by not shown internal bus.
Be provided with mimic channels such as voltage sensor, temperature sensor, current sensor, AD converter in mimic channel portion 11, the detected value of each sensor carries out digitizing by AD converter, offers CPU12 via internal bus.
CPU12 carries out the various softwares store in ROM13, the charging and discharging currents of the lithium ion battery that current sensor senses is gone out adds up computing, comes the residual capacity of battery of computing lithium ion battery thus.In addition, the detected value of voltage sensor and temperature sensor is used to carry out various corrections, and the operating area when RAM14 carries out processing as CPU12 also comprises the EEPROM as nonvolatile memory in ROM13.
Timing portion 15 has to comprise interrupts using timer at interior various timer with timer and timing, and the signal that these timers generate for example is provided for CPU12 as look-at-me, Measuring Time.The requirement that Department of Communication Force 16 correspondences use equipment to provide via communication terminal 17 from batteries such as mobile phone, digital cameras, the residual capacity of battery that CPU12 is calculated via communication terminal 17 sends to battery use equipment.
Variable oscillation circuit 41 is indicated the vibration of the frequency corresponding with pattern by pattern register 22 or is stopped, for example produce the low-speed clock that frequency is 38.4kHz according to vibration indication 1 (aggressive mode, sub-aggressive mode, sleep pattern, sub-sleep pattern), for example producing frequency according to vibration indication 2 (monitoring modes) is 9.6kHz or its following Ultra-Low Speed clock, offers oscillatory circuit 23 and clock selector 24 then.
At this, sometimes as the AD converter in the mimic channel portion 11 Sigma-De Erta modulator is set, by Sigma-De Erta modulator simulating signal is carried out PDM (pulse number modulation (PNM)) promptly, the modulation of 1 bit digital, offer CPU12 then, is the digital value of multidigit by CPU12 with the PDM conversion of signals, i.e. PCM (pulse code modulation (PCM)) data.At this moment, if CPU12 is provided the clock that frequency is the low speed of 38.4kHz, can be the PCM data then with the PDM conversion of signals, but if the Ultra-Low Speed clock of frequency 9.6kHz can't carry out from the conversion of above-mentioned PDM signal to the PCM data.That is, frequency is that the clock of the Ultra-Low Speed of 9.6kHz is the Ultra-Low Speed of the degree that CPU12 can't regular event.
Fig. 7 represents the circuit structure diagram of an embodiment of variable oscillation circuit 41.In the figure, the MOS-FET of p raceway groove (burning film semiconductor-field effect transistor: below become " MOS transistor ") M1～M4 is connected source electrode, grid is connected with terminal 42a～42d, and drain electrode is linked together with power Vcc.In the drain electrode of MOS transistor M1～M4, be connected with the source electrode of p channel MOS transistor M5, M6.Drain current when making MOS transistor M1～M4 conducting is identical.
The drain electrode of MOS transistor M5 is connected with non-inverting input of comparer 43, the drain electrode of n channel MOS transistor M7 and the end of capacitor C1, and with the other end ground connection of source electrode and the capacitor C1 of MOS transistor M7.The grid of MOS transistor M5, M7 is connected with the terminal d of logical circuit 45.Reverse input terminal at comparer 43 applies reference voltage V 1 from constant pressure source 46, and the lead-out terminal of comparer 43 is connected with the terminal a of logical circuit 45.
The drain electrode of MOS transistor M6 is connected with non-inverting input of comparer 44, the drain electrode of n channel MOS transistor M8 and the end of capacitor C2 (for example C1=C2), and with the other end ground connection of source electrode and the capacitor C2 of MOS transistor M8.The grid of MOS transistor M6, M8 is connected with the terminal e of logical circuit 45.Reversed input terminal at comparer 44 applies reference voltage V 1 from constant pressure source 46, and the lead-out terminal of comparer 44 is connected with the terminal b of logical circuit 45.
At this, terminal e at logical circuit 45 is output as high level, when terminal d output becomes low level, MOS transistor M6 conducting, MOS transistor M8 ends to come the charging to capacitor C2, and the voltage of non-inverting input of comparer 44 slowly rises, when having surpassed reference voltage V 1, the output of comparer 44 (that is the input of the terminal b of logical circuit 45) switches to high level from low level.Thus, the output of terminal c becomes low level, and the output of terminal e becomes high level, and MOS transistor M6 ends, MOS transistor M8 conducting, and capacitor C2 discharges hastily.So, the output of the terminal c of logical circuit 45 is exported from terminal 47 as oscillator signal.
At the indication generated frequency is that the vibration of the low-speed clock of 38.4kHz was indicated 1 o'clock, whole terminal 42a～42d are provided low level signal, MOS transistor M1～M4 conducting, the additive value of the drain current of MOS transistor M1～M4 becomes the drain current of MOS transistor M5 or MOS transistor M6, i.e. the charging current of capacitor C1, C2.
At the indication generated frequency is that the vibration of the Ultra-Low Speed clock of 9.6kHz was indicated 2 o'clock, only terminal 42a is a low level, the signal of high level is provided for terminal 42b～42d, only MOS transistor M1 conducting, the drain current of MOS transistor M1 becomes the drain current of MOS transistor M5 or MOS transistor M6, i.e. the charging current of capacitor C1, C2.
So, in vibration indication 2, become 1/4 of vibration indication 1, and make oscillation frequency become about 1/4 by the charging current that makes capacitor C1, C2.
In addition, as variable oscillation circuit 41, the oscillator that can prepare to generate the oscillator of low-speed clock and generate the Ultra-Low Speed clock switches to a certain side wherein.
Oscillatory circuit 23 for example is built-in with PLL, and by the pattern register 22 indications frequency corresponding with pattern, producing with coming for example frequency of the clock synchronization of self-oscillating circuit 41 is 5MHz/2.5
Some high speed clocks of MHz/1.25MHz offer clock selector 24 then.
In addition, also the clock that can oscillatory circuit 41 not exported offers oscillatory circuit 23, and oscillatory circuit 41,23 is moved asynchronously.
Clock selector 24 is by 22 indications and the corresponding clock selecting of pattern of pattern register, select some in low-speed clock and a plurality of high speed clock, offer mimic channel portion 11, CPU12, ROM13, RAM14, timing portion 15, Department of Communication Force 16 in the fuel quantity ga(u)ge module 10 respectively.
Above-mentioned pattern register 22 is set pattern by CPU12, serves as to trigger the change action pattern with CPU12 fill order (sleep commands).In addition, CPU12 stops in the register 25 setting the permission that mimic channel portion 11, timing portion 15, Department of Communication Force 16 clock separately accepts or forbids in module, the signal that the clock that module stops register 25 and provides indication to set to mimic channel portion 11, timing portion 15, Department of Communication Force 16 is respectively accepted permission or forbidden.Thus, mimic channel portion 11, timing portion 15, Department of Communication Force 16 only when being instructed to clock acceptance permission, are just accepted the clock that provides from clock selector 24.
(state transition)
Fig. 8 represents the state transition of SIC (semiconductor integrated circuit) shown in Figure 6.In addition, longitudinal direction is represented clock frequency in Fig. 8.In the figure, become aggressive mode (at a high speed) ACH by resetting apparatus.Afterwards, by the setting of pattern register 22 and the execution of sleep commands, for sub-aggressive mode SAC, in addition, carry out reciprocal migration by the setting of pattern register 22 and the execution of sleep commands from aggressive mode (at a high speed) ACH migration.
Aggressive mode (at a high speed) ACH is the clock of CPU12 according to frequency 5MHz, pattern with high-speed execution, the clock of the frequency 5MHz that clock selector 24 is selected offers each one of fuel quantity ga(u)ge functional module 10, and the instruction simulation circuit part 11, timing portion 15, the Department of Communication Force 16 that stop register 25 according to module are accepted clock to move at a high speed.
Sub-aggressive mode SAC is the clock of CPU12 according to frequency 38.4kMHz, pattern with the low speed executive routine, the clock of the frequency 38.4kHz that clock selector 24 is selected offers each one of fuel quantity ga(u)ge functional module 10, and the instruction simulation circuit part 11, timing portion 15, the Department of Communication Force 16 that stop register 25 according to module are accepted clock and moved with low speed.
In addition,,, move and be sleep pattern (middling speed) SLM, carry out reciprocal migration by the generation that program interrupt or timer interrupt by the setting of pattern register 22 and the execution of sleep commands from aggressive mode (at a high speed) ACH.
Sleep pattern (middling speed) SLM is that CPU12 stops action, stop the indication of register 25 according to module, mimic channel portion 11, timing portion 15, Department of Communication Force 16 are accepted the pattern that the clock of the frequency 2.5MHz that selected by clock selector 24 or 1.25MHz moves.
In addition,,, move and be sub-sleep pattern SSL, carry out reciprocal migration by the generation that program interrupt or timer interrupt by the setting of pattern register 22 and the execution of sleep commands from sub-aggressive mode SAC.
Sub-sleep pattern SSL is that CPU12 stops action, stops the indication of register 25 according to module, and mimic channel portion 11, timing portion 15, Department of Communication Force 16 are accepted the pattern that the clock of the frequency 38.4kHz that selected by clock selector 24 moves.
In addition, by the setting of pattern register 22 and the execution of sleep commands, migration is monitoring mode WTC, software standby mode SSB respectively, carries out reciprocal migration by the generation that program interrupt or timer interrupt from aggressive mode (at a high speed) ACH.
Monitoring mode WTC is that CPU12 stops action, stops the indication of register 25 according to module, and only timing portion 15 accepts the pattern that the clock of the frequency 9.6kHz that selected by clock selector 24 moves.
Software standby mode SSB is that CPU12 stops, and stops instruction simulation circuit part 11, timing portion 15, Department of Communication Force 16 whole patterns that stop of moving of register 25 according to module.
In addition, in monitoring mode WTC, software standby mode SSB, mimic channel portion 11, RAM14 pattern register 22, module stop register 25 etc. and keep separately internal state under the situation about stopping moving.
Therefore, can in timing portion 15, carry out timing under the monitoring mode WTC to the time of keeping monitoring mode WTC, after reverting to sub-aggressive mode SAC, can hold time according to monitoring mode by CPU12 and infer the charging and discharging currents of lithium ion battery from monitoring mode WTC.
(pattern switching)
Fig. 9 represents the process flow diagram of another embodiment of the pattern hand-off process that CPU12 carries out.In addition, when this handles beginning, aggressive mode (at a high speed) ACH or aggressive mode (middling speed) ACM have been preestablished.
In the figure, CPU12 in step S11 according to the frequency of kind, state or the request of the request of using equipment that Department of Communication Force 16 is provided from battery, judge that battery uses equipment whether to be connected with the electric battery that possesses self device (conductor integrated circuit device), battery uses equipment whether to be in operating state, and battery uses equipment whether to be in the function stop state.
For example, if battery uses equipment to be connected with electric battery, then the voltage of communication terminal 17 is the regulation grade, use the connection of equipment so can judge battery, if battery uses equipment as operating state then the frequency of asking is higher than setting, the frequency of asking if battery use equipment is in the function stop state is lower than setting, so can acts of determination state/function stop state.
In step S12, judge according to result of determination battery uses equipment whether to be in operating state, when battery use equipment is in operating state, in step S13, pattern is set at initiatively (at a high speed) ACH.
On the other hand, when in step S12, using equipment to be not operating state according to the result of determination battery, judge in step S14 battery uses equipment whether to be the function stop state, when battery use equipment is in the function stop state, pattern is switched to sleep pattern (middling speed) SLM at step S15.After switching, this, for example interrupts reverting to original aggressive mode (at a high speed) ACH according to timer when through after the stipulated time.
And, in step S14, when battery uses equipment not to be the function stop state, i.e. when battery use equipment is not connected with electric battery, in step S16, pattern switched to monitoring mode WTC.The Ultra-Low Speed clock that is 9.6kHz by 15 pairs of frequencies of timing portion after switching to this monitoring mode WTC is counted, when through the stipulated time, interrupt reverting to original aggressive mode (at a high speed) ACH or sub-aggressive mode SAC according to the timer that comes self clock portion 15.
In addition, in step S16, can also switch to monitoring mode WTC aggressive mode SAC or sub-sleep pattern SSL in addition.
In this embodiment, when battery use equipment was not connected with electric battery, as shown in figure 10, can make sub-aggressive mode SAC was stipulated time T1, and making monitoring mode WTC is stipulated time N * T1 (N is a real number), repeats such setting.
At this moment,, can in advance default value be set in during fabrication among the EEPROM in the ROM13, afterwards, when battery uses equipment to be connected with electric battery, use equipment that variable N is set change by battery about variable N.Thus, can be corresponding battery duration of using the state of equipment freely to change monitoring mode WTC.
So, in another embodiment, by under monitoring mode, for example using 9.6kHz or the Ultra-Low Speed clock below it, can reduce current sinking, even for example under the state that battery use equipment does not have with electric battery is connected, also can become sub-aggressive mode termly and come the computing residual capacity of battery, can further prolong the life-span of electric battery by cutting down current sinking.
In addition, in another embodiment, aggressive mode or sub-aggressive mode can be used, monitoring mode can be used as an example of four-mode as an example of three-mode.

Claims (10)

1. conductor integrated circuit device, it as power supply, and has battery to obtain residual capacity of battery and send to then with described battery and use the function of equipment as the battery of power supply, it is characterized in that,
Have following unit:
The clock generation unit, it generates first clock and the frequency second clock greater than described first clock;
Selected cell, it selects first clock of described clock generation unit output and some output the in the second clock;
Arithmetic element, its clock according to described selected cell output moves, and described residual capacity of battery is carried out computing; And
Communication unit, its clock according to described selected cell output moves, and will be sent to described battery by the residual capacity of battery that described arithmetic element calculates and use equipment.
2. conductor integrated circuit device according to claim 1 is characterized in that,
Have setup unit, this setup unit is set first pattern that makes described arithmetic element action and second pattern that described arithmetic element is stopped.
3. conductor integrated circuit device according to claim 1 and 2 is characterized in that,
Described clock generation unit has second oscillator of the second clock of first oscillator that generates first clock and generation and described first clock synchronization.
4. conductor integrated circuit device according to claim 1 and 2 is characterized in that,
Described clock generation unit has first oscillator of described first clock of generation and second oscillator of generation and the asynchronous second clock of described first clock.
5. according to any described conductor integrated circuit device of claim 2 to 4, it is characterized in that,
The clock that has according to described selected cell output moves the timing unit that carries out timing under described second pattern.
6. according to any described conductor integrated circuit device of claim 2 to 5, it is characterized in that,
Described setup unit uses the connection status and the operating state of equipment to carry out the switching of described first pattern and described second pattern according to described battery.
7. an electric battery is characterized in that,
Any described conductor integrated circuit device and the described battery that possess claim 1 to 6.
8. conductor integrated circuit device according to claim 1 is characterized in that,
Have setup unit, the four-mode that the clock that this setup unit is set the three-mode that makes described arithmetic element action and made described arithmetic element stop the described selected cell output of only use carries out the timing unit action of timing,
Described clock generation unit has first oscillator that generates first clock and second oscillator that generates second clock,
Described first oscillator with respect to the frequency of first clock that generates under described three-mode, makes the frequency of first clock that generates under described four-mode low.
9. conductor integrated circuit device according to claim 8 is characterized in that,
Described timing unit allows described setup unit move to described three-mode using described first clock to carry out timing through the stipulated time time under the described four-mode.
10. conductor integrated circuit device according to claim 9 is characterized in that,
Described timing unit has been made the described stipulated time can freely to change.
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