KR101508677B1 - semiconductor integrated circuit device and battery pack - Google Patents

Abstract

The present invention provides a semiconductor integrated circuit device and a battery pack capable of setting various operation modes in which current consumption is different, reducing current consumption according to the connection state and operation state of the battery using device, .

A semiconductor integrated circuit device having a function of obtaining a remaining battery level by using a battery as a power source and transmitting the remaining battery level to a battery using device that uses the battery as a power source, the semiconductor integrated circuit device comprising: a clock generating unit that generates a first clock and a second clock having a frequency higher than that of the first clock A selecting means (24) for selecting one of a first clock and a second clock outputted by the clock generating means, and a selecting means (24) for selecting one of the first clock and the second clock outputted by the selecting means And a communication means (16) which is operated by a clock outputted by the selection means and which transmits the remaining battery level calculated by the calculation means to the battery using device.

Battery, battery use device, semiconductor integrated circuit device, clock generating means, selecting means, calculating means, communication means

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor integrated circuit device,

The present invention relates to a semiconductor integrated circuit device and a battery pack, and more particularly, to a semiconductor integrated circuit device and a battery pack having a function of obtaining a remaining battery level and transmitting it to a battery-powered device.

BACKGROUND ART [0002] In recent years, lithium ion batteries have been mounted on portable battery-powered devices such as mobile phones and digital cameras. It is generally known that the lithium ion battery is difficult to detect the remaining battery level by the voltage. For this reason, a method of measuring the residual amount of the battery by integrating the charging / discharging current of the battery is taken.

Conventionally, a fuel gauge (IC) has been developed for measuring the remaining amount of a battery using the above-described method. The fuel gauge (IC) has a built-in CPU, memory, etc. and converts the detected charge / discharge current into digital data The battery remaining amount is calculated, and the calculated remaining battery amount is transmitted to a battery using device such as a cellular phone or a digital camera by a communication circuit.

Although the Fuel Gauge (IC) is intended to measure the battery level, it is necessary to reduce the consumption current of the Fuel Gauge (IC) as much as possible because the Fuel Gauge (IC) supplies operating power from the lithium ion battery.

Patent Document 1 discloses that a battery residual amount measurement mode is provided in the control mode of the data processing means and control is performed to minimize the supply current from the battery during the measurement mode to achieve power saving.

Patent Document 1: JP-A-2005-12960

The conventional fuel gauge (IC) has only a shutdown mode for stopping the clock or shutting off the power supply for a long period of time in addition to the normal mode. Therefore, it is possible to reduce the current consumption according to the connection state of the battery- There is a problem that the remaining amount of the battery can not be obtained in a long-term neglected state in which the battery using device is not connected.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to provide a battery charger that can set various operation modes with different current consumption and can reduce consumption current according to the connection state and operation state of the battery- An object of the present invention is to provide a semiconductor integrated circuit device and a battery pack.

A semiconductor integrated circuit device according to an embodiment of the present invention is a semiconductor integrated circuit device having a function of obtaining the remaining amount of a battery using a battery as a power source and transmitting the remaining amount of the battery to a battery using device that uses the battery as a power source,

Clock generating means (21, 23) for generating a first clock and a second clock having a frequency higher than that of the first clock,

Selecting means (24) for selecting and outputting either the first clock or the second clock outputted by the clock generating means,

Calculating means (12) operated by a clock outputted by said selecting means and calculating the battery remaining amount,

And a communication means (16) which is operated by a clock outputted by the selection means and transmits the battery remaining amount calculated by the calculation means to the battery using device, whereby various operation modes having different current consumption can be set, The consumption current can be reduced according to the connection state and the operation state of the apparatus, and the battery remaining amount can also be obtained.

In the semiconductor integrated circuit device,

(12, 22, 25, S1 to S6) for setting a first mode for operating the calculation means (12) and a second mode for stopping the calculation means (12).

In the semiconductor integrated circuit device,

The clock generating means (21, 23) includes a first oscillator (21) for generating a first clock,

And a second oscillator (23) for generating a second clock synchronized with the first clock.

In the semiconductor integrated circuit device,

The clock generating means (21, 23) includes a first oscillator (21) for generating the first clock,

And a second oscillator (23) for generating a second clock asynchronous with the first clock.

In the semiconductor integrated circuit device,

And a time measuring means (15) operated by a clock outputted by the selecting means and performing time measurement in the second mode.

In the semiconductor integrated circuit device,

The setting means (S1 to S6) may be configured to switch between the first mode and the second mode according to the connection state and the operation state of the battery using device.

The battery pack according to the embodiment of the present invention can set various operation modes with different current consumption by including the semiconductor integrated circuit device according to any one of claims 1 to 6 and the battery, The consumption current can be reduced according to the state or operation state, and the remaining battery capacity can be obtained.

In the semiconductor integrated circuit device,

A fourth mode for operating only the time measuring means (15) for stopping the calculation means (12) and performing the time measurement using the clock outputted by the selection means (12, 22, 25, S11 to S16)

The clock generating means has a first oscillator (41) for generating a first clock and a second oscillator (23) for generating a second clock,

The first oscillator 41 may be configured to decrease the frequency of the first clock generated in the fourth mode with respect to the frequency of the first clock generated in the third mode.

In the semiconductor integrated circuit device,

The time measuring means 15 measures the time using the first clock in the fourth mode and makes the setting means transit to the third mode when a predetermined time has elapsed.

In the semiconductor integrated circuit device,

The time measuring means 15 can be configured so that the predetermined time can be changed freely.

The reference numerals in the above parentheses are added for ease of understanding and are merely one example, and the present invention is not limited to the illustrated embodiment.

According to the present invention, the start-up of the signal processing means can be optimized according to the selected oscillation source.

(Best Mode for Carrying Out the Invention)

≪ Configuration of Semiconductor Integrated Circuit Device >

1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, the analog circuit portion 11, the CPU 12, the ROM 13, the RAM 14, the timer portion 15, and the communication portion 16 are provided in the fuel gauge function module 10, These are connected to each other by an internal bus (not shown).

Analog circuits such as a voltage sensor, a temperature sensor, a current sensor, and an AD converter are provided in the analog circuit unit 11, and the detection values of the respective sensors are digitized in the AD converter and supplied to the CPU 12 via the internal bus.

The CPU 12 executes various kinds of software stored in the ROM 13, and calculates the battery remaining amount of the lithium ion battery by integrating the charging / discharging current of the lithium ion battery detected by the current sensor. The detected values of the voltage sensor and the temperature sensor are used for various kinds of correction. The RAM 14 is used as a work area when the CPU 12 executes the processing, and the ROM 13 is also provided with an EEPROM .

The timer unit 15 has various timers including an interruption timer and a timer for time measurement. The signal generated by these timers is supplied to the CPU 12 as an interrupt signal and measurement time, for example. The communication unit 16 communicates the remaining amount of the battery calculated by the CPU 12 to the battery using device via the communication terminal 17 in accordance with a request supplied from the battery use device such as a cellular phone or a digital camera through the communication terminal 17 .

The oscillation circuit 21 is instructed to oscillate or stop according to the operation mode from the operation mode register 22 and generates a low speed clock of, for example, a frequency of 38.4 kHz in response to the instruction of the oscillation and outputs it to the oscillation circuit 23 and the clock selector 24.

The oscillation circuit 23 incorporates, for example, a PLL. The oscillation circuit 23 is supplied with the operation mode register 22 with a multiplication factor according to the operation mode, High-speed clock of the frequency 5 MHz / 2.5 MHz / 1.25 MHz and supplies it to the clock selector 24.

The oscillation circuits 21 and 23 may be operated asynchronously without supplying the clock output from the oscillation circuit 21 to the oscillation circuit 23.

The clock selector 24 instructs clock selection in accordance with the operation mode from the operation mode register 22 and selects one of the low clock and the plurality of middle and high speed clocks, To the CPU 11, the CPU 12, the ROM 13, the RAM 14, the timer 15, and the communication unit 16, respectively.

The operation mode register 22 sets the operation mode from the CPU 12 and triggers the instruction (sleep instruction) by the CPU 12 to switch the operation mode. The CPU 12 sets permission or inhibition of clock acceptance of each of the analog circuit unit 11, the timer unit 15 and the communication unit 16 to the module stop register 25 and the module stop register 25 sets A timer unit 15, and a communication unit 16, each of which instructs to permit or prohibit the reception of the clocks, to the analog circuit unit 11, the timer unit 15, and the communication unit 16, respectively. Thereby, the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive clocks supplied from the clock selector 24 only to those for which clock acceptance is instructed.

<State transition>

Fig. 2 shows a state transition diagram of the semiconductor integrated circuit device shown in Fig. In the figure, by reset, the device is in the active mode (high speed) (ACH). (High speed) ACH to the active mode (middle speed) ACM by the setting of the operation mode register 22 and the execution of the sleep instruction and the setting of the operation mode register 22 and the sleep command In the reverse direction. It is also possible to change from the active mode (middle speed) ACM to the subactive mode SAC by setting of the operation mode register 22 and execution of the sleep instruction and also to set the operation mode register 22 and execute the sleep instruction In the opposite direction.

The active mode (high-speed) ACH is a mode in which the CPU 12 executes a program at a high speed by a clock having a frequency of 5 MHz and a clock with a frequency of 5 MHz selected by the clock selector 24 is input to the respective And the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive the clock and operate at a high speed in response to an instruction from the module stop register 25. [

The active mode (medium speed) ACM is a mode in which the CPU 12 executes a program at an intermediate speed by a clock of a frequency of 2.5 MHz or 1.25 MHz and a clock of 2.5 MHz or 1.25 MHz selected by the clock selector 24 is a clock Gauge function module 10 and the analog circuit unit 11, the timer unit 15 and the communication unit 16 receive the clock and operate at a medium speed under the direction of the module stop register 25. [

The subactive mode SAC is a mode in which the CPU 12 executes a program at a low speed by a clock of a frequency of 38.4 kHz and a clock of a frequency of 38.4 kHz selected by the clock selector 24 is applied to the respective phases of the fuel gauge function module 10 And the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive the clock and operate at a low speed in response to an instruction from the module stop register 25. [

It is also possible to set the operation mode register 22 and the sleep command from the active mode (high speed) ACH, the active mode (middle speed) ACM and the subactive mode SAC, SLH), a sleep mode (medium speed) SLM, and a sub sleep mode (SSL), and a transition is made in the reverse direction by the occurrence of a program interrupt or a timer interrupt.

In the sleep mode (high speed) SLH, the CPU 12 stops operating, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 are controlled by the clock selector And receives a clock having a frequency of 5 MHz selected by the user.

In the sleep mode (middle speed) SLM, the CPU 12 stops operating, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 are controlled by the clock selector 24 ), And operates by receiving a clock of 2.5 MHz or 1.25 MHz.

In the sub sleep mode (SSL), the CPU 12 stops operating, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 are controlled by the clock selector 24 It operates by receiving clock of 38.4kHz selected frequency.

The setting of the operation mode register 22 and the execution of the sleep instruction from the active mode (high speed) ACH, the active mode (middle speed) ACM and the subactive mode SAC, Standby mode (SSB), and a transition is made in the reverse direction by occurrence of a program interrupt or a timer interrupt.

The watch mode WTC is a mode in which the CPU 12 stops operating and only the timer unit 15 receives clocks of the frequency 38.4 kHz selected by the clock selector 24 under the direction of the module stop register 25 to be.

The software standby mode SSB is a mode in which the CPU 12 stops operating and both the analog circuit unit 11, the timer unit 15 and the communication unit 16 stop operating in response to an instruction from the module stop register 25 .

When the analog circuit unit 11, the RAM 14, the operation mode register 22, the module stop register 25, and the like are stopped in the watch mode (WTC) and the software standby mode (SSB) Lt; / RTI &gt;

Therefore, in the watch mode (WTC), it is possible to measure the time in which the watch mode (WTC) is held in the timer section 15 and the active mode (high speed) ACH, (ACM) and the subactive mode (SAC), the CPU 12 can estimate the charging / discharging current of the lithium ion battery from the watch mode holding time.

<Switching operation mode>

Fig. 3 shows a flowchart of an embodiment of the operation mode switching process executed by the CPU 12. Fig. Further, active mode (high speed) (ACH) or active mode (medium speed) (ACM) is set in advance when this processing starts.

In step S1, the CPU 12 determines whether or not a battery (battery) having its own device (semiconductor integrated circuit device) is selected from the type of the request supplied from the battery using device to the communication unit 16, It is determined whether the battery-used device is connected to the pack, whether the battery-used device is in the operating state or the battery-used device is in the function stop state.

For example, when the battery-powered device is connected to the battery pack, the connection of the battery-operated device can be determined because the voltage of the communication terminal 17 is at the predetermined level. If the battery-powered device is in the operating state, And the frequency of the request is lower than the predetermined value when the battery-operated device is in the function stop state, the operation state / function stop state can be determined.

(High-speed) ACH or active mode (medium speed) ACM in step S3 if the battery-operated device is in the operating state, Set to the operation mode.

On the other hand, if the battery-operated device is not in the operating state from the determination result in step S2, it is determined in step S4 whether or not the battery-powered device is in the function stop state. If the battery- Switches the operation mode to sleep mode (high speed) (SLH) or sleep mode (medium speed) (SLM). (High speed) ACH, active mode (medium speed) ACM, or subactive mode SAC, for example, by a timer interruption when a predetermined time elapses after the switching.

If it is determined in step S4 that the battery-operated device is not in the function stop state, that is, if the battery-powered device is not connected to the battery pack, the sub-active mode (SAC) (WTC). (ACH) or an active mode (medium speed) (ACM) or the like in response to a predetermined time after the switching to the sub sleep mode (SSL) or the watch mode (WTC) And returns to the subactive mode SAC.

(High speed) ACH or active mode (medium speed) ACM is set in step S3 and whether any one of the sleep mode (high speed) SLH or the sleep mode (medium speed) SLM (SAC), the sub-sleep mode (SSL), or the watch mode (WTC) in step S6 is set in advance in the EEPROM of the ROM 13 by the user.

When the battery-powered device is connected to the battery pack and the battery-powered device is not in the operating state, the active mode (high-speed) ACH (or active) (High speed) SLH (or sleep mode (medium speed) SLM) by a predetermined time T2, and repeats this operation.

When the battery pack is not connected to the battery pack, the active mode (high-speed) ACH (or active mode (medium speed) ACM or ACM Active mode (SAC)], the watch mode (WTC) is set for the predetermined time T3, and this is repeated. As described above, the user can freely set which mode to use according to the state of the battery using device.

Thus, for example, if the battery use device is in the active state, the active mode is set according to the connection state and operation state of the battery use device, and if the battery use device is not in the operation state, for example, If the battery using device is not connected, for example, by setting the watch mode, the current consumption can be reduced, and the battery remaining amount in a long-term left-off state in which the battery using device is not connected can be obtained.

<Battery Pack>

5 is a perspective view of an embodiment of a battery pack to which the semiconductor integrated circuit device of the present invention is applied. In the figure, the battery pack 30 has a structure in which the battery 31 and the semiconductor integrated circuit device 32 are housed in a case 33. The battery 31 is a lithium ion battery and is connected to the semiconductor integrated circuit device 32 having the configuration shown in Fig. 1 by connection terminals 34a and 34b.

The external terminals 35a and 35b provided in the case 33 are connected to the positive and negative electrodes of the battery 31 and the external terminal 35c is connected to the communication terminal 17 of the semiconductor integrated circuit device 32 have.

In the above embodiment, the active mode is used as an example of the first mode, and the sleep mode or the watch mode is used as an example of the second mode.

<Other Embodiments>

6 shows a block diagram of another embodiment of the semiconductor integrated circuit device of the present invention. In the figure, the same parts as those in Fig. 1 are denoted by the same reference numerals. The analog circuit section 11, the CPU 12, the ROM 13, the RAM 14, the timer section 15, and the communication section 16 are provided in the fuel gauge function module 10, And are connected to each other by an internal bus.

An analog circuit such as a voltage sensor, a temperature sensor, a current sensor, and an AD converter is provided in the analog circuit unit 11. The detection values of the respective sensors are digitized in the AD converter and supplied to the CPU 12 via the internal bus.

The CPU 12 executes various kinds of software stored in the ROM 13, and calculates the battery remaining amount of the lithium ion battery by integrating the charging / discharging current of the lithium ion battery detected by the current sensor. The detected values of the voltage sensor and the temperature sensor are used for various kinds of correction. The RAM 14 is used as a work area when the CPU 12 executes the processing, and the ROM 13 is also provided with an EEPROM .

The timer unit 15 has various timers including an interruption timer and a timer for time measurement. The signal generated by these timers is supplied to the CPU 12 as an interrupt signal and measurement time, for example. The communication unit 16 communicates the remaining amount of the battery calculated by the CPU 12 to the battery using device via the communication terminal 17 in accordance with a request supplied from the battery use device such as a cellular phone or a digital camera through the communication terminal 17 .

The variable oscillation circuit 41 receives an instruction from the operation mode register 22 to oscillate or stop the frequency in accordance with the operation mode and outputs the oscillation instruction 1 (active mode, subactive mode, sleep mode, Generates a low speed clock of 38.4 kHz and generates an ultra low speed clock of, for example, a frequency of 9.6 kHz or less in the oscillation instruction 2 (watch mode) and supplies it to the oscillation circuit 23 and the clock selector 24.

Here, a sigma-delta modulator is provided as an AD converter in the analog circuit unit 11, a sigma-delta modulator supplies the CPU 12 with the analog signal by PDM (Pulse Density Modulation) or 1-bit digital modulation, 12 may be configured to convert the PDM signal into a digital value of David, that is, PCM (pulse code modulation) data. In this case, the CPU 12 can convert the PDM signal into the PCM data when the low-speed clock of the frequency of 38.4 kHz is supplied, but can not convert the PDM signal into the PCM data at the ultra-low-speed clock of the frequency 9.6 kHz . That is, the ultra-low speed clock having the frequency of 9.6 kHz is very low speed that the CPU 12 can not operate normally.

7 shows a circuit diagram of a variable oscillation circuit 41 according to an embodiment of the present invention. In the figure, the source of the p-channel MOS-FET (metal oxide semiconductor-field effect transistor: hereinafter referred to as "MOS transistor") M1 to M4 is connected to the power source (Vcc), the gate is connected to the terminals 42a to 42d, And the drains are connected in common. The sources of the p-channel MOS transistors M5 and M6 are connected to the drains of the MOS transistors M1 to M4. And the drain currents when the MOS transistors M1 to M4 are on are the same.

The drain of the MOS transistor M5 is connected to the non-inverting input terminal of the comparator 43, the drain of the n-channel MOS transistor M7 and one end of the capacitor C1, and the source of the MOS transistor M7 and the capacitor C1 Is grounded. The gates of the MOS transistors M5 and M7 are connected to the terminal d of the logic circuit 45. [ The reference voltage V1 is applied to the inverting input terminal of the comparator 43 from the constant voltage source 46 and the output terminal of the comparator 43 is connected to the terminal a of the logic circuit 45.

The drain of the MOS transistor M6 is connected to the non-inverting input terminal of the comparator 44 and one end of the drain of the n-channel MOS transistor M8 and the capacitor C2 (for example, C1 = C2) M8 and the other end of the capacitor C2 are grounded. The gates of the MOS transistors M6 and M8 are connected to the terminal e of the logic circuit 45. [ The reference voltage V1 is applied from the constant voltage source 46 to the inverting input terminal of the comparator 44 and the output terminal of the comparator 44 is connected to the terminal b of the logic circuit 45.

Here, when the output of the terminal e of the logic circuit 45 is at the high level and the output of the terminal d is at the low level, the MOS transistor M5 is turned on, the MOS transistor M7 is turned off, When the voltage of the non-inverting input terminal of the comparator 43 gradually rises and exceeds the reference voltage V1, the output of the comparator 43 (that is, the input of the terminal (a) of the logic circuit 45) Level to high level. As a result, the output of the terminal c becomes a high level and the output of the terminal d becomes a high level so that the MOS transistor M5 is turned off and the MOS transistor M7 is turned on so that the capacitor C1 rapidly Is discharged.

When the output of the terminal d of the logic circuit 45 is at the high level and the output of the terminal e is at the low level, the MOS transistor M6 is turned on, the MOS transistor M8 is turned off to charge the capacitor C2, When the voltage of the non-inverting input terminal of the comparator 44 gradually rises and exceeds the reference voltage V1, the output of the comparator 44 (that is, the input of the terminal b of the logic circuit 45) Level. As a result, the output of the terminal c becomes the low level, the output of the terminal e becomes the high level, the MOS transistor M6 is turned off, the MOS transistor M8 is turned on, and the capacitor C2 is rapidly discharged . Thus, the output of the terminal c of the logic circuit 45 is outputted from the terminal 47 as an oscillation signal.

Level signal is supplied to all of the terminals 42a to 42d and the MOS transistors M1 to M4 are turned on to turn on the MOS transistors M1 to M4 ) Becomes the drain current of the MOS transistor M5 or M6, that is, the charge current of the capacitors C1 and C2.

In the case of the oscillation instruction 2 for instructing the generation of the ultra-low speed clock of 9.6 kHz, only the terminal 42a supplies a high level signal to the level terminal terminals 42b to 42d so that only the MOS transistor M1 is turned on, The drain current of the transistor M1 becomes the drain current of the MOS transistor M5 or M6, that is, the charging current of the capacitors C1 and C2.

As described above, in the oscillation instruction 2, the oscillation frequency is reduced to about 1/4 by setting the charge current of the capacitors C1 and C2 to 1/4 of the oscillation instruction 1.

As the variable oscillation circuit 41, an oscillator for generating a low-speed clock and an oscillator for generating an ultra-low-speed clock may be provided and switched to either one.

The oscillation circuit 23 incorporates, for example, a PLL, receives an instruction from the operation mode register 22 for a multiplier according to the operation mode, and generates an oscillation signal in synchronization with the clock from the oscillation circuit 41, for example, / 2.5 MHz / 1.25 MHz and supplies it to the clock selector 24.

The oscillation circuits 41 and 23 may be operated asynchronously without supplying the clock output from the oscillation circuit 41 to the oscillation circuit 23.

The clock selector 24 is instructed to select a clock in accordance with the operation mode from the operation mode register 22 and selects one of the low clock and the plurality of middle and high speed clocks, 11, the CPU 12, the ROM 13, the RAM 14, the timer 15, and the communication unit 16, respectively.

The operation mode register 22 switches the operation mode by triggering that the operation mode is set from the CPU 12 and the CPU 12 executes the instruction (sleep instruction). The CPU 12 sets permission or inhibition of clock acceptance of each of the analog circuit unit 11, the timer unit 15 and the communication unit 16 to the module stop register 25. The module stop register 25 sets the clock enable The timer section 15, and the communication section 16, respectively, to the analog circuit section 11, the timer section 15, and the communication section 16, respectively. Thereby, the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive clocks supplied from the clock selector 24 only to those for which clock acceptance is instructed.

<State transition>

Fig. 8 shows a state transition diagram of the semiconductor integrated circuit device shown in Fig. 8 shows the clock frequency in the longitudinal direction. In the figure, by reset, the device is in the active mode (high speed) (ACH). (SAC) FH transits from the active mode (high speed) ACH to the subactive mode SAC FH by the setting of the operation mode register 22 and the execution of the sleep instruction, And performs a reverse transition by execution.

The active mode (high-speed) ACH is a mode in which the CPU 12 executes a program at a high speed by a clock having a frequency of 5 MHz and a clock with a frequency of 5 MHz selected by the clock selector 24 is input to the respective And the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive the clock and operate at a high speed according to an instruction from the module stop register 25. [

The subactive mode SAC is a mode in which the CPU 12 executes a program at a low speed by a clock of a frequency of 38.4 kHz and a clock of a frequency of 38.4 kHz selected by the clock selector 24 is applied to the respective phases of the fuel gauge function module 10 And the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive the clock and operate at a low speed in response to an instruction from the module stop register 25. [

(SLM) by the setting of the operation mode register 22 and the execution of the sleep instruction from the active mode (high-speed) ACH and the occurrence of the program interrupt or the timer interrupt Transition is performed.

In the sleep mode (middle speed) SLM, the CPU 12 stops operating, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 are controlled by the clock selector 24), and operates by receiving a clock of 2.5 MHz or 1.25 MHz.

In addition, transition is made from the subactive mode SAC to the sub-sleep mode (SSL) by the setting of the operation mode register 22 and the execution of the sleep instruction, and a transition is made in the reverse direction by the occurrence of a program interrupt or a timer interrupt.

In the sub sleep mode (SSL), the CPU 12 stops operating, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 are controlled by the clock selector 24 It operates by receiving clock of 38.4kHz selected frequency.

It is also possible to make a transition from the active mode (high speed) ACH to the watch mode WTC and the software standby mode SSB by the setting of the operation mode register 22 and the execution of the sleep instruction, And makes a reverse transition by occurrence.

The watch mode WTC is a mode in which the CPU 12 stops operating and only the timer unit 15 receives clocks of the frequency 9.6 kHz selected by the clock selector 24 under the direction of the module stop register 25 to be.

The software standby mode SSB is a mode in which the CPU 12 stops operating and the operation of all of the analog circuit unit 11, the timer unit 15, and the communication unit 16 is stopped by an instruction from the module stop register 25 to be.

When the analog circuit portion 11, the RAM 14, the operation mode register 22, the module stop register 25, and the like are stopped in the watch mode (WTC) and the software standby mode (SSB) Lt; / RTI &gt;

Therefore, in the watch mode (WTC), the time in which the watch mode (WTC) is held in the timer section (15) can be measured and after returning from the watch mode (WTC) to the subactive mode ), The charge / discharge current of the lithium ion battery can be estimated from the watch mode holding time.

<Switching operation mode>

Fig. 9 shows a flowchart of another embodiment of the operation mode switching process executed by the CPU 12. Fig. Further, active mode (high speed) (ACH) or active mode (medium speed) (ACM) is set in advance when this processing starts.

In step S11, the CPU 12 determines whether or not a battery pack having a self-device (semiconductor integrated circuit device) is connected to the communication unit 16, based on the type of the request, the status, It is determined whether or not the battery using apparatus is connected, the battery using apparatus is in the operating state, and the battery using apparatus is in the function stop state.

For example, when the battery-powered device is connected to the battery pack, the connection of the battery-operated device can be determined because the voltage of the communication terminal 17 is at the predetermined level. If the battery-powered device is in the operating state, And the frequency of the request is lower than the predetermined value when the battery-operated device is in the function stop state, the operation state / function stop state can be determined.

In step S12, it is determined whether or not the battery-powered device is in the operating state. If the battery-powered device is in the operating state, the active mode is set to the active mode (high speed) ACH in step S13.

On the other hand, if the battery use device is not in the operating state from the determination result in step S12, it is determined in step S14 whether or not the battery using device is in the function stop state. If the battery use device is in the function stop state, Switches the operation mode to sleep mode (medium speed) (SLM). When a predetermined time elapses after the switching, the timer returns to the original active mode (high-speed) ACH, for example, by a timer interrupt.

If the battery-operated device is not in the function stop state in step S14, that is, if the battery-powered device is not connected to the battery pack, the operation mode is switched to the watch mode (WTC) in step S16. After switching to the watch mode (WTC), the timer section 15 counts the ultra-low speed clock of frequency 9.6 kHz, and when the predetermined time elapses, the timer interruption from the timer section 15 causes the original active mode ACH) or the subactive mode (SAC).

In addition, in step S16, it may be configured to switch to the subactive mode (SAC) or the sub-sleep mode (SSL) other than the watch mode (WTC).

In this embodiment, when the battery-powered device is not connected to the battery pack, as shown in Fig. 10, the subactive mode SAC is set for the predetermined time T1, N is a real number) is set as the watch mode (WTC), and this is repeated.

In this case, the variable N is set to a default value in the EEPROM in the ROM 13 at the time of manufacture, and when the battery-powered device is connected to the battery pack thereafter, the variable N can be changed from the battery- . This makes it possible to freely change the duration of the watch mode (WTC) according to the state of the battery-powered device.

As described above, in another embodiment, the consumption current can be reduced by using, for example, an ultra low-speed clock having a frequency of 9.6 kHz or less in the watch mode. For example, when the battery- Active mode, so that the remaining battery life can be further extended by reducing the consumption current.

In another embodiment, an active mode or a subactive mode is used as an example of the third mode, and a watch mode is used as an example of the fourth mode.

1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

2 is a state transition diagram of the semiconductor integrated circuit device.

3 is a flow chart of one embodiment of the operation mode switching process.

4 is an explanatory diagram of mode switching.

5 is a perspective view of one embodiment of a battery pack to which the semiconductor integrated circuit device of the present invention is applied.

6 is a block diagram of another embodiment of the semiconductor integrated circuit device of the present invention.

7 is a circuit configuration diagram of one embodiment of the variable oscillation circuit.

8 is a state transition diagram of the semiconductor integrated circuit device shown in Fig.

9 is a flowchart of another embodiment of the operation mode switching process.

10 is an explanatory diagram of mode switching.

(Explanation of Symbols)

10 Fuel Gauge Function Module 11 Analog Circuitry

12 CPU 13 ROM

14 RAM 15 Timer part

16 communication unit 21, 23, 41 oscillation circuit

22 Operation mode register 24 Clock selector

25 Module Stop Registers 30 Battery Packs

31 Battery 32 Semiconductor Integrated Circuit Device

Claims (10)

A semiconductor integrated circuit device having a function of obtaining a remaining amount of a battery by using a battery as a power source and transmitting the remaining amount of the battery to a battery using device which is a power source, Clock generating means for generating a first clock and a second clock having a frequency higher than that of the first clock, Selecting means for selecting and outputting either the first clock or the second clock outputted by the clock generating means; Calculating means for operating on the basis of a clock outputted by the selecting means and calculating the remaining battery charge; A communication unit operable by a clock outputted by said selection unit and transmitting the battery remaining amount calculated by said calculation unit to said battery use device; And setting means for setting a first mode for operating said calculating means and a second mode for stopping said calculating means, Wherein said setting means switches between said first mode and said second mode in accordance with a connection state and an operation state of said battery use device. delete 2. The semiconductor integrated circuit device according to claim 1, wherein said clock generating means comprises a first oscillator for generating a first clock and a second oscillator for generating a second clock synchronized with said first clock. The semiconductor integrated circuit device according to claim 1, wherein said clock generating means has a first oscillator for generating said first clock and a second oscillator for generating a second clock which is asynchronous with said first clock. The semiconductor integrated circuit device according to claim 1, further comprising a time measuring means for operating with a clock outputted by said selecting means and performing time measurement in said second mode. delete As a battery pack, A battery, And a semiconductor integrated circuit device having a function of obtaining the remaining amount of the battery by using the battery as a power source and transmitting the remaining amount of the battery to a battery using device which is used as a power source, The semiconductor integrated circuit device includes: Clock generating means for generating a first clock and a second clock having a frequency higher than that of the first clock, Selecting means for selecting and outputting either the first clock or the second clock outputted by the clock generating means; Calculating means for operating on the basis of a clock outputted by the selecting means and calculating the remaining battery charge; A communication unit operable by a clock outputted by said selection unit and transmitting the battery remaining amount calculated by said calculation unit to said battery use device; And setting means for setting a first mode for operating said calculating means and a second mode for stopping said calculating means, Wherein the setting means switches between the first mode and the second mode according to a connection state and an operation state of the battery using device. The apparatus according to claim 1, further comprising: a third mode for operating said calculating means; a setting for setting a fourth mode for operating only time measuring means for stopping said calculating means and performing time measurement using a clock outputted by said selecting means With the means, The clock generating means has a first oscillator for generating a first clock and a second oscillator for generating a second clock, Wherein the first oscillator lowers the frequency of the first clock generated in the fourth mode with respect to the frequency of the first clock generated in the third mode. The apparatus according to claim 8, wherein the time measuring means measures the time using the first clock in the fourth mode, and causes the setting means to transit to the third mode when a predetermined time elapses Semiconductor integrated circuit device. 10. The semiconductor integrated circuit device according to claim 9, wherein the time measuring means changes the predetermined time.

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