CN101442318B - Low time delay IRA code encoder based on near lower triangular structure check matrix - Google Patents

Abstract

The invention provides a low time delay IRA code coder for an approximate lower triangular structure based check matrix, which belongs to the technical field of wireless communication, wherein the row exchange treatment of an H1 part of the check matrix is performed by a pretreatment module of the check matrix, so that the H1 part of the check matrix meets the approximate lower triangular structure; an information bit buffer memory module receives information bit of the code ready for coding and temporarily stores the information bit, and immediately controls a signal channel coding module to start coding after receiving partial information bit; and according to the check matrix after pretreatment, the signal channel coding module starts coding after the information buffer memory module receives the partial information bit. The coder has the advantages of advancing the start time of signal channel coding, reducing transmission time delay, and continuing to receive and temporarily store the information bit while coding; and because the coding and the receiving and temporary store of the information bit are performed at the same time, the working efficiency of the coder is improved, and the coding time delay is reduced.

Description

Low time delay IRA code encoder based near lower triangular structure check matrix

Technical field

The present invention relates to a kind of encoder of wireless communication technology field, specifically is a kind of low time delay IRA code encoder based near lower triangular structure check matrix.

Background technology

Along with to the going deep into of Turbo code and LDPC sign indicating number research, the researcher of chnnel coding begins to pay close attention to, and for given channel, how to find a kind of so good sign indicating number: one, linear time code; Two, arbitrarily near the code check of channel capacity the time, linear session decoding.For Turbo code, no matter parallel or serial can both linear time code, yet for the LDPC sign indicating number, its encryption algorithm and code length are secondary and concern.

1998, Divsalar, Jin and McEliece proposed regular RA (Repeat Accumulate) sign indicating number, promptly repeated the accumulation sign indicating number.The structure of RA encoder is very simple, is formed by duplication code, interleaver and accumulator serially concatenated.2000; They further receive the inspiration of abnormal LDPC code; IRA (Irregular Repeat Accumulate) sign indicating number has been proposed; Be the irregular accumulation sign indicating number of repeating, and proved that binary system IRA sign indicating number can obtain the same superior performance of abnormal LDPC code, but the complexity of encryption algorithm is well below the LDPC sign indicating number.

Literature search through to prior art finds that H.Jin, A.Khandekar and R.EcEliece are in Proc.2nd Int.Symp.Turbo Codes, 2000; (Turbo code international conference in 2000 that pp.1-8 is last have been delivered " IrregularRepeat Accumulate Codes "; The 1-8 page or leaf, non-rule repeats accumulated code), provided the implementation method of a kind of encoder of IRA sign indicating number in the literary composition; Realize linear time code, greatly reduced encoder complexity.Yet this method must could begin to generate check bit after receiving the full detail bit, and the coding time started is later, and propagation delay time is bigger, and moreover, because coding can not carry out with the buffer memory information bit simultaneously, the time delay of therefore encoding is also bigger.

Summary of the invention

The objective of the invention is deficiency to above-mentioned prior art; A kind of low time delay IRA code encoder based near lower triangular structure check matrix has been proposed; Effectively reduce propagation delay time and coding time delay,, have important use and be worth for the chnnel coding environment that real-time is had relatively high expectations.

The present invention realizes through following technical scheme, the present invention includes: check matrix pretreatment module, information bit cache module, channel coding module, wherein:

The check matrix pretreatment module partly is listed as exchange to IRA code check matrix left side random configuration and handles; IRA code check matrix left side random configuration partly is the H1 part of check matrix; Make the H1 of check matrix partly satisfy near lower triangular structure; And will exchange and handle the back check matrix and offer channel coding module, the maximum column of 1 element in the every row of check matrix H 1 part number is offered the information bit cache module;

The information bit cache module receives information bit to be encoded; And with its buffer memory; Receive row exchange processing back check matrix H 1 part that the check matrix pretreatment module transmits simultaneously; Whenever the maximum column number that receives 1 element in every row is about to information bit and is transferred to channel coding module, and the control channel coding module is encoded;

Channel coding module receives the information bit that the information bit cache module sends over, and based on the check matrix after the row exchange processing information bit is encoded.

Said check matrix pretreatment module; It makes the H1 of check matrix partly become near lower triangular structure through the row exchange; Specific as follows: row of 1 element number in the every row of scanned for checkout matrix H 1 part successively; If the row of certain 1 element number are greater than " maximum column of lastrow 1 element number add 1 ", then exchange this row and " maximum column of lastrow 1 element number add 1 " that be listed as, if be less than or equal to then do not do any exchange.

Said information bit cache module; It is responsible for receiving the information bit row cache of going forward side by side from information source; And encode according to the maximum column control channel coding module of 1 element in the every row of 1 part of check matrix H after the preliminary treatment; Because check matrix has passed through row exchange preliminary treatment; The maximum column of handling 1 element in the every row of back check matrix H 1 part number has been offered the information bit cache module, and the information bit cache module need not wait the whole buffer memorys of information bit, and promptly beginning ahead of time provides information bit to encode to channel coding module.

Among the present invention, adopt through the pretreated check matrix of row exchange and encode, because check matrix H 1 part is a near lower triangular structure; Therefore, channel coding module just can begin coding behind information bit cache module receiving unit information bit, after promptly the information bit cache module receives the maximum column number pairing information bit of 1 element in check matrix H 1 part first row; Coding can begin; Since handle the maximum column monotone increasing of 1 element in the every row of back check matrix H 1 part, therefore, in receiving the information bit process; When the information bit number equaled the maximum column of 1 element in certain row, this row corresponding check bit just can generate.

Compared with prior art; The present invention has following beneficial effect: the present invention has generated a part of check bit when receiving the full detail bit, has significantly reduced propagation delay time and coding time delay; And after common IRA code coder must receive the full detail bit, could begin coding.In addition; Because it is a preliminary treatment job that check matrix is listed as exchange; And row exchanges does not change codeword performance fully, so the present invention's encoder complexity and not losing under the situation of any codeword performance when not increasing work in fact, has improved IRA sign indicating number coding real-time.

Description of drawings

Fig. 1 is a system architecture diagram of the present invention;

Fig. 2 partly is the check matrix sketch map of near lower triangular structure for H1 in the IRA code check matrix among the present invention;

Fig. 3 is listed as the pretreated workflow diagram of exchange for the check matrix pretreatment module among the present invention;

Fig. 4 partly is listed as the dot chart that exchanges the near lower triangular matrix that obtains after the preliminary treatment for the H1 to certain website check matrix in the embodiments of the invention;

Fig. 5 is the amplification of Fig. 4 near lower triangular matrix square frame part.

Embodiment

Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment being to implement under the prerequisite with technical scheme of the present invention.

IRA code check matrix general type is specific as follows:

IRA code check matrix in the present embodiment is: $\left(\begin{array}{cccccc}1& 0& 1& 0& 1& 0\\ 0& 1& 1& 0& 0& 1\\ 0& 0& 0& 1& 1& 1\\ 1& 1& 0& 0& 0& 1\\ 0& 1& 1& 1& 0& 0\\ 1& 0& 0& 1& 1& 0\end{array}\right|\left.\begin{array}{cccccc}1& 0& 0& 0& 0& 0\\ 1& 1& 0& 0& 0& 0\\ 0& 1& 1& 0& 0& 0\\ 0& 0& 1& 1& 0& 0\\ 0& 0& 0& 1& 1& 0\\ 0& 0& 0& 0& 1& 1\end{array}\right).$

As shown in Figure 1, present embodiment comprises: check matrix pretreatment module, information bit cache module, channel coding module, wherein:

The check matrix pretreatment module partly is listed as exchange to IRA code check matrix left side random configuration and handles; IRA code check matrix left side random configuration partly is the H1 part of check matrix; Make the H1 of check matrix partly satisfy near lower triangular structure; And will exchange and handle the back check matrix and offer channel coding module, the maximum column of 1 element in the every row of check matrix H 1 part number is offered the information bit cache module;

The information bit cache module receives information bit to be encoded; And with its buffer memory; Receive row exchange processing back check matrix H 1 part that the check matrix pretreatment module transmits simultaneously; Whenever the maximum column number that receives 1 element in every row is about to information bit and is transferred to channel coding module, and the control channel coding module is encoded;

Channel coding module receives the information bit that the information bit cache module sends over, and based on the check matrix after the row exchange processing information bit is encoded.

As shown in Figure 3, said check matrix pretreatment module makes the H1 of check matrix partly become near lower triangular structure through the row switching method, at first, and initialization check matrix, row i=1, row j=1,1 element maximum column x=1; Each row of scanned for checkout matrix H 1 part successively if the element of the capable j of i row equals 1, then exchanges j and is listed as the x row then, and 1 element maximum column x++; Then j++, if j=M+1, j=x then, i++, otherwise got back to for second step; At last, if i=N-M+1 then finishes, otherwise got back to for second step.

In the present embodiment, check matrix H 1 part of random configuration has been carried out preliminary treatment, reached the effect of low time delay, check matrix H 2 parts are consistent with common IRA sign indicating number, kept the IRA sign indicating number simple characteristic of encoding, and whole check matrix sketch map is shown in accompanying drawing 2.

As shown in Figure 4; Be in the present embodiment; To in MacKay website (http://www.inference.phy.cam.ac.uk/mackay/codes/data.html#166) (1018; 2048) check matrix carries out the dot chart of H1 part after the preliminary treatment, and Fig. 5 be the amplification partly of Fig. 4 near lower triangular matrix square frame.

In the present embodiment, be through the IRA code check matrix after the check matrix pretreatment module row exchange preliminary treatment: $\left(\begin{array}{cccccc}1& 1& 1& 0& 0& 0\\ 0& 1& 0& 1& 1& 0\\ 0& 0& 1& 0& 1& 1\\ 1& 0& 0& 1& 1& 0\\ 0& 1& 0& 1& 0& 1\\ 1& 0& 1& 0& 0& 1\end{array}\right|\left.\begin{array}{cccccc}1& 0& 0& 0& 0& 0\\ 1& 1& 0& 0& 0& 0\\ 0& 1& 1& 0& 0& 0\\ 0& 0& 1& 1& 0& 0\\ 0& 0& 0& 1& 1& 0\\ 0& 0& 0& 0& 1& 1\end{array}\right).$

Said information bit cache module, it receives and the cache information bit, and information bit is followed successively by 0,1 in the present embodiment, and 1,0,1,0.

Said channel coding module, its coding generates check bit, receives 0,1 at the information bit cache module, after 1, generates first check bit 0, receives 0; After 1,1,0,1, generate second check bit 0, receive 0; After 1,1,0,1,0, generate the 3rd check bit 0; After full detail bit buffer memory finishes, continue to accomplish cataloged procedure, generate remaining check bit 1,0,1, coding is accomplished.

In the present embodiment, owing to adopted the check matrix preconditioning technique, therefore, after receiving first three information bit 0,1,1, can get into coding stage, propagation delay time shortens to 3, continues simultaneously to receive information bit, promptly receives information bit and carries out with coding is parallel; Under common coding, need wait these six information bits all to receive to finish and just can encode, the propagation delay time that is input to first check bit output from first information bit is 6.

In the present embodiment, the encoding time delay that is input to the output of last check bit from first information bit is 9, and if to adopt general coding method, encoding time delay be 12.

In sum, the encoder that adopts the present embodiment method to propose is encoded and is made transmission delay reduce by 50%, and encoding time delay reduces by 25%.

Claims (3)

1. the low time delay IRA code encoder based near lower triangular structure check matrix is characterized in that, comprising: check matrix pretreatment module, information bit cache module, channel coding module, wherein:

The check matrix pretreatment module partly is listed as exchange to IRA code check matrix left side random configuration and handles; IRA code check matrix left side random configuration partly is the H1 part of check matrix; Make the H1 of check matrix partly satisfy near lower triangular structure; And will exchange and handle the back check matrix and offer channel coding module, the maximum column of 1 element in the every row of check matrix H 1 part number is offered the information bit cache module;

The information bit cache module receives information bit to be encoded; And with its buffer memory; Receive row exchange processing back check matrix H 1 part that the check matrix pretreatment module transmits simultaneously; Whenever the maximum column number that receives 1 element in every row is about to information bit and is transferred to channel coding module, and the control channel coding module is encoded;

Channel coding module receives the information bit that the information bit cache module sends over, and based on the check matrix after the row exchange processing information bit is encoded;

Check matrix H=(H1|H2).

2. the low time delay IRA code encoder based near lower triangular structure check matrix according to claim 1; It is characterized in that; Said check matrix pretreatment module; It makes the H1 of check matrix partly become near lower triangular structure through row exchanges, and is specific as follows: row of 1 element number in the every row of scanned for checkout matrix H 1 part successively, if the row of certain 1 element number are greater than " maximum column of lastrow 1 element number add 1 "; Then exchange this row and " maximum column of lastrow 1 element number add 1 " that be listed as, if be less than or equal to then do not do any exchange.

3. the low time delay IRA code encoder based near lower triangular structure check matrix according to claim 1; It is characterized in that; Said information bit cache module, it is responsible for receiving the information bit row cache of going forward side by side from information source, and according to row in the every row of check matrix H 1 part after exchange is handled the maximum column control channel coding module of 1 element encode; Because check matrix has passed through row exchange preliminary treatment; The maximum column of handling 1 element in the every row of back check matrix H 1 part number has been offered the information bit cache module, and the information bit cache module need not wait the whole buffer memorys of information bit, and promptly beginning ahead of time provides information bit to encode to channel coding module.

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