CN101442302B - Gate drive circuit and drive method thereof - Google Patents
Gate drive circuit and drive method thereof Download PDFInfo
- Publication number
- CN101442302B CN101442302B CN2007101877152A CN200710187715A CN101442302B CN 101442302 B CN101442302 B CN 101442302B CN 2007101877152 A CN2007101877152 A CN 2007101877152A CN 200710187715 A CN200710187715 A CN 200710187715A CN 101442302 B CN101442302 B CN 101442302B
- Authority
- CN
- China
- Prior art keywords
- low
- output
- pressure side
- voltage
- driving stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000005669 field effect Effects 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 17
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 230000008676 import Effects 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 3
- 230000009471 action Effects 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 claims 1
- 230000009466 transformation Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 239000011159 matrix material Substances 0.000 abstract description 8
- 230000008570 general process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a gate drive circuit and a drive method thereof. A voltage-level converter converts the voltage operation level range of an input end signal so as to reduce use of circuit components and lower cost; and a driver stage output component on the high voltage end adopts a P type metal-oxide semiconductor field effect transistor, which is connected in series, to be used as a diverter switch, thereby preventing the matrix effect generating in the general process of manufacturing at a high voltage.
Description
Technical field
The present invention relates to a kind of driver, particularly relate to a kind of gate driver circuit and driving method thereof.
Background technology
Because some specific application circuit needs the assembly of huge driving force, this assembly is power transistor normally, and promote these application circuits for the power controlling transistor, must import a gate terminal that controls signal to power transistor, therefore, can dispose a gate driver circuit in the prime of power transistor.For example the drive principle of motor is controlled high-pressure side power transistor and low-pressure end power transistor according to specific connected mode exactly, allows revolution to make its conducting in order with closing.And will make the power transistor conducting or close, must import the control signal of a high state or low state in its gate terminal, but because the control signal of importing in the gate terminal of high-pressure side and low-pressure end power transistor, the voltage level of its high state and low state is also inequality.For this reason, a gate driver circuit must be disposed, in order to the signal that general control signal is converted to the conducting of may command power transistor or closes before power transistor.
As shown in Figure 1, it is the schematic diagram of the gate driver circuit of known technology.Gate driver circuit 10 comprises an input logic circuit 110, a pulse generator 120, a high tension voltage position quasi converter 130, a pulsed filter 140, a latch circuit 150, a high-pressure side driving stage 160, a low-pressure end driving stage 170 and a low voltage detector 180.And input logic circuit 110 utilizes signal input part HIN, LIN to come receiving inputted signal.
The output signal AT of high-pressure side does the voltage level conversion through pulse generator 120 and high tension voltage position quasi converter 130, and produce via the processing of pulsed filter 140 and latch circuit 150, wherein the voltage-operated scope of the circuit (comprising pulsed filter 140, latch circuit 150 and high-pressure side driving stage 160) after the high tension voltage position quasi converter 130 is the VB to VS with high voltage.The output signal AB of low-pressure end then directly is controlled by input logic circuit 110, and voltage level is relatively low, and its voltage-operated scope is VM to VSS.The difference of VB and VS can equal the difference of VM and VSS in addition.The switch that passes through the driving stage output precision of high-pressure side driving stage 160 and low-pressure end driving stage 170 then switches, and decides the state of output signal AT, AB.
Yet the negative terminal power supply VS of the pulsed filter 140 of high-pressure side, latch circuit 150 and high-pressure side driving stage 160 also is not equal to VSS.Therefore, when above-mentioned drive circuit is realized in general high voltage manufacturing process, will be owing to edge of substrate (bulk) the voltage level VSS and the source terminal voltage level VS of N type metal oxide semiconductor field effect transistor are unequal, thereby generation matrix effect, and make critical voltage (VT) become very big, and then derive the not good problem of driving force.In order to eliminate matrix effect, the common practice all is to utilize complexity and special high-pressure process technology (as: Mitsui (Triple Well) manufacturing process) to solve.So, complex manufacturing process not only, and expend cost.
On the other hand, when high-pressure side driving stage 160 when the switch of doing the driving stage output precision switches, its voltage range is VB ~ VS, to such an extent as to high tension voltage position quasi converter 130 can't use general framework.And; continue consumed power for fear of high tension voltage position quasi converter 130; usually can add pulse generator 120 and latch circuit 150 and come the signal of latch pulse generator 120, and then utilize pulsed filter 140 to filter the noise that high tension voltage position quasi converter 130 is produced again when switching moment.But thus, will assembly be increased and further cause raising up of cost.
Be different from above-mentioned drive circuit, the gate driver circuit that the present invention will provide can avoid matrix effect, simplify the high-pressure side circuit and can realize in general high voltage manufacturing process is to overcome the problem that prior art is produced.
Summary of the invention
The object of the present invention is to provide a kind of gate driver circuit and driving method thereof, directly utilizing the voltage level transducer with the accurate scope conversion in the voltage-operated position of input end signal, and adopt the P type metal oxide semiconductor field effect transistor of serial connection to be used as switch at high-pressure side driving stage output precision and switch, to avoid in general high pressure manufacturing process, producing matrix effect.
To achieve these goals, the invention provides a kind of gate driver circuit, comprise input logic circuit, high tension voltage position quasi converter, low voltage voltage position quasi converter, high-pressure side driving stage, low-pressure end driving stage and low voltage detector.High tension voltage position quasi converter and low voltage voltage position quasi converter are carried out switching motion to the accurate scope of voltage of signals operative position that input logic circuit provided.The high-pressure side driving stage is linked to high tension voltage position quasi converter, according to the signal after the conversion of high tension voltage position quasi converter, controls the output signal that produces high-pressure side.The low-pressure end driving stage is linked to low voltage voltage position quasi converter, according to the signal after the conversion of low voltage voltage position quasi converter, controls the output signal that produces low-pressure end.
To achieve these goals, the present invention also provides a kind of grid drive method, in order to the state of the output signal of controlling a gate driver circuit, this method comprises: import an input signal, this input signal has a high state voltage level and a low state voltage level; Change this input signal, to produce at least one high-pressure side output control signal and at least one low-pressure end output control signal, one high state voltage level of this high-pressure side output control signal and this low-pressure end output control signal all is higher than the high state voltage level of this input signal, and a low state voltage level of this high-pressure side output control signal and this low-pressure end output control signal is equal to the low state voltage level of this input signal; Control the output of a high-pressure side of this gate driver circuit according to this high-pressure side output control signal; And the output of controlling a low-pressure end of this gate driver circuit according to this low-pressure end output control signal.
From the above, the present invention directly utilizes the voltage level scope conversion of voltage level transducer with input, with the use of reduction circuit unit, and reduces expending of cost; High-pressure side adopts the PMOS of serial connection to be used as the driving stage output precision in addition, avoiding under general high voltage manufacturing process, and when the PMOS of serial connection is connected to NMOS, the matrix effect that high voltage differential caused that is produced between NMOS edge of substrate and the source terminal.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the gate driver circuit schematic diagram of common technology;
Fig. 2 is the block schematic diagram of the gate driver circuit of content of the present invention;
Fig. 3 is the circuit diagram of common voltage level transducer;
Fig. 4 is the flow chart of the grid drive method of content of the present invention; And
Fig. 5 is the block schematic diagram of the gate driver circuit of content of the present invention.
Wherein, Reference numeral:
Three-phase gate drivers 50
Input logic circuit 110,210
Pulse generator 120
High tension voltage position quasi converter 130,220
Low voltage voltage position quasi converter 230
High-pressure side driving stage 160,240
Low-pressure end driving stage 170,250
Pulsed filter 140
Latch circuit 150
Low voltage detector 180,260
Driving stage output precision 241,242,251,252
Voltage level VCC, VSS, VB, VS, VM, V1
Signal input part HIN, LIN, HI, LI, HI1,
LI1，HI2，LI2，HI3，LI3
High-pressure side signal HD
Low-pressure end signal LD
High-pressure side output control signal HH, HL
Low-pressure end output control signal LX
Voltage level transducer input SI, SIB
Voltage level converter output end SO, SOB
Transistor Q1, Q2, Q3, Q4
Output signal AT, AB, PH, PL, PH1, PL1,
PH2，PL2，PH3，PL3
Embodiment
Please refer to Fig. 2, it is the block schematic diagram of the gate driver circuit of content of the present invention.Gate driver circuit 20 of the present invention comprises an input logic circuit (input logic circuit) 210, one high tension voltage position quasi converter (high voltage level shifter) 220, one low voltage voltage position quasi converter (low voltage level shifter) 230, one high-pressure side driving stage (high side driver) 240, one low-pressure end driving stage (low side driver) 250 and one low voltage detector (low voltagedetector) 260.
High tension voltage position quasi converter 220 is linked to input logic circuit 210, and receive the high-pressure side signal HD that input logic circuit 210 is provided, further this high-pressure side signal HD is carried out conversion, the voltage-operated position that just high-pressure side signal HD is possessed is accurate to be converted to VB to VSS by original VCC to VSS.In addition, high tension voltage position quasi converter 220 this high-pressure side signal of meeting computing HD, to produce high-pressure side output control signal HH and HL, wherein the output of the high-pressure side of high-pressure side output control signal HH control gate driver circuit 20 presents high state (high), and the output of the high-pressure side of high-pressure side output control signal HL control gate driver circuit 20 presents low state (low).
Low voltage voltage position quasi converter 230 is linked to input logic circuit 210, and receive the low-pressure end signal LD that input logic circuit 210 is provided, further this low-pressure end signal LD is carried out conversion, the voltage-operated position that just low-pressure end signal LD is possessed is accurate to be converted to VM to VSS by original VCC to VSS.In addition, quasi converter 230 this low-pressure end signal of meeting computing LD in low voltage voltage position export control signal LX to produce low-pressure end, and the output of the low-pressure end of low-pressure end output control signal LX control gate driver circuit 20 present high state or low state.Wherein, VM also is the power supply of low voltage voltage position quasi converter 230 and low-pressure end driving stage 250 simultaneously.
High-pressure side driving stage 240 is linked to high tension voltage position quasi converter 220, its inside comprises driving stage output precision 241 and 242, wherein driving stage output precision 241,242 all is a P type metal oxide semiconductor field effect transistor (P-type metal oxide semiconductor field effect transistor, P-type MOSFET), and the drain electrode end of driving stage output precision 241 (drain terminal) be connected with the source terminal (source terminal) of driving stage output precision 242.
When the high-pressure side output control signal HH that receives high tension voltage position quasi converter 220 and provided when the gate terminal (gate terminal) of driving stage output precision 241 is low state, driving stage output precision 241 is with conducting, the output signal PH that makes the drain electrode end of driving stage output precision 241 export presents high state, that is to say that the voltage level of output signal PH equals VB.
When the high-pressure side output control signal HL that receives high tension voltage position quasi converter 220 and provided when the gate terminal of driving stage output precision 242 is low state, driving stage output precision 242 is with conducting, the output signal PH that makes the source terminal of driving stage output precision 242 export presents low state, that is to say that the voltage level of output signal PH equals VS.And under initial state, output signal PH is VS.And it for example is 80V and 65V that VB and VS can distinguish at this moment, but also can be different because of the difference of practical application situation.
Low-pressure end driving stage 250 is linked to low voltage voltage position quasi converter 230, its inside comprises driving stage output precision 251 and 252, wherein driving stage output precision 251 is PMOS, driving stage output precision 252 is N type metal oxide semiconductor field effect transistor (N-type metal oxide semiconductor fieldeffect transistor, N-type MOSFET), and the drain electrode end of driving stage output precision 251 be connected to the drain electrode end of driving stage output precision 252.
When the low-pressure end output control signal LX that receives low voltage voltage position quasi converter 230 and provided when the gate terminal of driving stage output precision 251 is low state, driving stage output precision 251 is with conducting, the output signal PL that makes the drain electrode end of driving stage output precision 251 export presents high state, that is to say that the voltage level of output signal PL equals VM.
When the low-pressure end output control signal LX that receives low voltage voltage position quasi converter 230 and provided when the gate terminal of driving stage output precision 252 is high state, driving stage output precision 252 is with conducting, the output signal PL that makes the drain electrode end of driving stage output precision 252 export presents low state, that is to say that the voltage level of output signal PL equals VSS.And under initial state, output signal PL is VSS.And it for example is 0V and 15V that VSS and VM can distinguish at this moment, but also can be different because of the difference of practical application situation.
In addition, the circuit that is adopted in high tension voltage position quasi converter 220 and the low voltage voltage position quasi converter 230, as shown in Figure 3, it is the circuit diagram of common voltage level transducer.
For instance, suppose that the high-pressure side signal HD that input logic circuit 210 inputs to voltage level transducer input SI is a high state, its voltage level equals VCC; And input to voltage level transducer input SIB is the inversion signal of high-pressure side signal HD, is low state, and its voltage level equals VSS, then transistor Q3 with conducting, and transistor Q4 will end.Wherein, voltage level V1 just equals voltage level VB.
When transistor Q3 conducting, voltage level converter output end SO will present low state, and its voltage level equals VSS, and make transistor Q2 conducting.Transistor Q2 after the conducting can make voltage level converter output end SOB present high state, and its voltage level equals VB, and makes transistor Q1 end.Therefore, the voltage level transducer can be converted to the output of required voltage opereating specification to the voltage-operated scope of this input signal.At last, voltage level converter output end SO and SOB will control the change action of high-pressure side driving stage 240 respectively as high-pressure side output control signal HH and HL.At this moment, high-pressure side output control signal HH and HL are because be in order to open or to close the driving stage output precision 241 and 242 that is PMOS equally, but its operational range of event also is restricted to VS ~ VB as known technology, and can operate within the scope of VSS ~ VB.
Though this case utilizes the voltage level transducer of Fig. 3 to be used as the high tension voltage position quasi converter 220 of this case and the embodiment of low voltage voltage position quasi converter 230, but content of the present invention is not limited to this, all scopes that the voltage level transducer of the accurate conversion in voltage of signals position is all content of the present invention that reaches.
According to above-mentioned narration about gate driver circuit 20 internal structure squares as can be known, the output circuit of high-pressure side driving stage 240 adopts PMOS to be used as driving stage output precision 242, therefore can avoid under general high voltage manufacturing process, the high voltage differential that is produced between edge of substrate (bulk) when driving stage output precision 242 adopts NMOS and the source terminal is further to prevent matrix effect (body effect).
For the operation workflow of the gate driver circuit 20 of further setting forth Fig. 2 in the content of the present invention, please refer to shown in Figure 4ly, it is the flow chart of the grid drive method of content of the present invention.At first, import one group of input signal to logical circuit 210, by signal input part HI and LI as step S410.
Because gate driver circuit 20 is in operation, low voltage detector 260 can detect the low-pressure end power supply VM of (comprising low voltage voltage position quasi converter 230 and low-pressure end driving stage 250) at any time, to monitor low-pressure end power supply VM whether less than a default value, as step S420.Therefore, input logic circuit 210 can decide the result of its output according to the result that low voltage detector 260 detects.
As low-pressure end power supply VM during less than this default value, as step S421, low voltage detector 260 can output one control signal to input logic circuit 210, forcing input logic circuit 210 is low state by the output signal PH that high-pressure side signal HD controls high-pressure side driving stage 240, and also is low state by the output signal PL that low-pressure end signal LD controls low-pressure end driving stage 250.
As low-pressure end power supply VM during more than or equal to this default value, as step S430, input logic circuit 210 directly will convert high-pressure side signal HD and low-pressure end signal LD to by the received input signal of signal input part HI, LI, and respectively high-pressure side signal HD is sent to high tension voltage position quasi converter 220, and low-pressure end signal LD is sent to low voltage voltage position quasi converter 230.
Then, as step S440, high tension voltage position quasi converter 220 can utilize its inner circuit structure, the voltage-operated position of changing high-pressure side signal HD is accurate, just according to the state of high-pressure side signal HD, decide two anti-phase high-pressure sides that export high-pressure side driving stage 240 to export the state of control signal HH and HL, with the state of the last output signal PH that exports of further decision high-pressure side.
And on the other hand, as step S440, low voltage voltage position quasi converter 230 also can utilize its inner circuit structure, the voltage-operated position of changing low-pressure end signal LD is accurate, just according to the state of low-pressure end signal LD, decide the state of the low-pressure end output control signal LX that exports low-pressure end driving stage 250 to, with the state of the last output signal PL that exports of further decision low-pressure end.In addition, this moment, low-pressure end output control signal LX was because be in order to open or to close driving stage output precision 251 and 252, can operate within the scope of VSS ~ VM in theory.
Because high-pressure side output control signal HH is sent to the driving stage output precision 241 of high-pressure side driving stage 240, in order to the switch switching of controlling and driving level output precision 241; High-pressure side output control signal HL then is sent to the driving stage output precision 242 of high-pressure side driving stage 240, in order to the switch switching of controlling and driving level output precision 242.In addition on the one hand, low-pressure end output control signal LX is sent to the driving stage output precision 251 and 252 of low-pressure end driving stage 250, in order to the switch switching of controlling and driving level output precision 251 and 252.
Therefore, as step S450, high-pressure side driving stage 240 will be exported the state of control signal HH and HL according to high-pressure side, decide the switch of corresponding driving stage output precision 241,242 to switch, and be high state or low state with the output signal PH that controls high-pressure side; Low-pressure end driving stage 250 will be exported the state of control signal LX according to low-pressure end, decide the switch of driving stage output precision 251,252 to switch, and be high state or low state with the output signal PL that controls low-pressure end.
HH is low state when high-pressure side output control signal, and high-pressure side output control signal HL is when being high state, and high-pressure side output control signal HH can make 241 conductings of driving stage output precision, and high-pressure side output control signal HL then can make driving stage output precision 242 end.Therefore, the high-pressure side of this moment is output as high state, and just output signal PH equals voltage level VB.
HH is a high state when high-pressure side output control signal, and high-pressure side output control signal HL is when being low state, and high-pressure side output control signal HH can make driving stage output precision 241 end, and high-pressure side output control signal HL then can make 242 conductings of driving stage output precision.Therefore, the output of the high-pressure side of this moment is low state, and just output signal PH equals voltage level VS.
When low-pressure end output control signal LX was low state, low-pressure end output control signal LX can make 251 conductings of driving stage output precision, and the control signal of low-pressure end output simultaneously LX also can make driving stage output precision 252 end.Therefore, the low-pressure end of this moment is output as high state, and just output signal PL equals voltage level VM.
When low-pressure end output control signal LX was high state, low-pressure end output control signal LX can make driving stage output precision 251 end, and the control signal of low-pressure end output simultaneously LX also can make 252 conductings of driving stage output precision.Therefore, the low-pressure end of this moment is output as low state, and just output signal PL equals voltage level VSS.
By the structure of above-mentioned gate driver circuit 20 and grid drive method thereof as can be known, content of the present invention is utilized high tension voltage position quasi converter 220, directly the accurate scope in voltage-operated position with the high-pressure side control signal of input (input logic circuit 210) is converted to VB to VSS by VCC to VSS, again according to the signal after the conversion of high tension voltage position quasi converter, control the output signal that high-pressure side driving stage 240 produces high-pressure side, and the accurate scope in voltage-operated position of this output signal is VB to VS; Utilize low voltage voltage position quasi converter 230 simultaneously, the accurate scope in voltage-operated position of the low-pressure end control signal of input (input logic circuit 210) is converted to VM to VSS by VCC to VSS, again according to the signal after the conversion of low voltage voltage position quasi converter, control the output signal that low-pressure end driving stage 250 produces low-pressure end, and the accurate scope in voltage-operated position of this output signal is VM to VSS.Thus, because unnecessary assembly is omitted fully, this gate driver circuit 20 can significantly reduce the use of circuit unit, thereby reduce expending of cost.
Characteristic according to gate driver circuit of the present invention, it can be applied to drive three-phase motor, as shown in Figure 5, gate driver circuit 50 utilizes driver 51,52 and 53 that the grid of drive signal to the N type power metal oxide-semiconductor field-effect transistor that promotes three-phase motor is provided respectively, and three-phase motor is rotated.
The advantage that content of the present invention provided is, directly utilizes the voltage level scope conversion of voltage level transducer with input, with the use of reduction circuit unit, and reduces expending of cost.
Another advantage that content of the present invention provided is, high-pressure side adopts the PMOS of serial connection to be used as the driving stage output precision, avoiding under general high voltage manufacturing process, when the PMOS of serial connection is connected to NMOS, the matrix effect that high voltage differential caused that is produced between NMOS edge of substrate and the source terminal.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (7)
1. a gate driver circuit is characterized in that, comprises:
One input logic circuit;
One high-pressure side is linked to this input logic circuit, and this high-pressure side comprises:
One high tension voltage position quasi converter to the signal that this input logic circuit provided, carries out the accurate conversion in voltage-operated position; And
One high-pressure side driving stage is linked to this high tension voltage position quasi converter, in order to the result by this high tension voltage position quasi converter conversion, controls the state of an output signal of this high-pressure side; This high-pressure side driving stage comprises two driving stage output precisions of serial connection, and described two driving stage output precisions are P type metal oxide semiconductor field effect transistor; The grid of described two P type metal oxide semiconductor field effect transistors links to each other with this high tension voltage position quasi converter;
One low-pressure end is linked to this input logic circuit, and this low-pressure end comprises:
One low voltage voltage position quasi converter to the signal that this input logic circuit provided, carries out the accurate conversion in voltage-operated position; And
One low-pressure end driving stage is linked to this low voltage voltage position quasi converter, in order to the result by this low voltage voltage position quasi converter conversion, controls the state of an output signal of this low-pressure end.
2. gate driver circuit according to claim 1, it is characterized in that, described high-pressure side driving stage comprises two P type metal oxide semiconductor field effect transistors of serial connection, wherein one of them P type metal oxide semiconductor field effect transistor of high-pressure side driving stage is in order to control this high-pressure side driving stage output high state, and another P type metal oxide semiconductor field effect transistor is then in order to control this high-pressure side driving stage output low state.
3. gate driver circuit according to claim 1, it is characterized in that, described low-pressure end driving stage comprises a P type metal oxide semiconductor field effect transistor and a N type metal oxide semiconductor field effect transistor, wherein this P type metal oxide semiconductor field effect transistor is in order to control this low-pressure end driving stage output high state, and this N type metal oxide semiconductor field effect transistor is then in order to control this low-pressure end driving stage output low state.
4. gate driver circuit according to claim 1, it is characterized in that, also further comprise a low voltage detector, it is linked to this input logic circuit, accurate in order to the position of monitoring this low-pressure end power supply, and when the position of this low-pressure end power supply standard was lower than a default value, this low voltage detector forced the output of this high-pressure side driving stage and this low-pressure end driving stage to present low state.
5. a grid drive method is characterized in that, in order to the state of the output signal of controlling a gate driver circuit, this method comprises:
Import an input signal, this input signal has a high state voltage level and a low state voltage level;
Change this input signal, to produce at least one high-pressure side output control signal and at least one low-pressure end output control signal, one high state voltage level of this high-pressure side output control signal and this low-pressure end output control signal all is higher than the high state voltage level of this input signal, and a low state voltage level of this high-pressure side output control signal and this low-pressure end output control signal is equal to the low state voltage level of this input signal;
The high-pressure side driving stage of the P type metal oxide semiconductor field effect transistor of this high-pressure side output control signal by comprising serial connection is controlled the output of a high-pressure side of this gate driver circuit; And
Control the output of a low-pressure end of this gate driver circuit according to this low-pressure end output control signal.
6. grid drive method according to claim 5, it is characterized in that, the position that also further comprises the power supply that detects this low-pressure end at any time is accurate, the action that comes this input signal of control transformation with further generation one control signal, and accurate when the position of this low-pressure end power supply less than a default value, then force to make this high-pressure side and this low-pressure end be output as low state.
7. grid drive method according to claim 5, it is characterized in that, switch the high-pressure side outgoing route of this gate driver circuit according to this high-pressure side output control signal, to determine this high-pressure side to be output as high state or low state, and export the low-pressure end outgoing route that control signal is switched this gate driver circuit according to this low-pressure end, be output as high state or low state to determine this low-pressure end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101877152A CN101442302B (en) | 2007-11-20 | 2007-11-20 | Gate drive circuit and drive method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101877152A CN101442302B (en) | 2007-11-20 | 2007-11-20 | Gate drive circuit and drive method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101442302A CN101442302A (en) | 2009-05-27 |
| CN101442302B true CN101442302B (en) | 2010-11-03 |
Family
ID=40726588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101877152A Active CN101442302B (en) | 2007-11-20 | 2007-11-20 | Gate drive circuit and drive method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101442302B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9978862B2 (en) * | 2013-04-30 | 2018-05-22 | Infineon Technologies Austria Ag | Power transistor with at least partially integrated driver stage |
| US9799643B2 (en) | 2013-05-23 | 2017-10-24 | Infineon Technologies Austria Ag | Gate voltage control for III-nitride transistors |
| US9503074B2 (en) | 2015-03-06 | 2016-11-22 | Qualcomm Incorporated | RF circuit with switch transistor with body connection |
| US10063225B1 (en) * | 2017-06-11 | 2018-08-28 | Nanya Technology Corporation | Voltage switching device and method |
| CN108540121B (en) * | 2018-04-13 | 2020-09-29 | 电子科技大学 | Gate drive circuit without static power consumption |
| CN109102832B (en) * | 2018-09-12 | 2021-07-06 | 中国电子科技集团公司第五十八研究所 | Negative voltage transmission circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1407559A (en) * | 2001-08-29 | 2003-04-02 | 力旺电子股份有限公司 | Booster circuit |
| US6819149B2 (en) * | 2003-01-24 | 2004-11-16 | Mitsubishi Denki Kabushiki Kaisha | Gate drive device for reducing a surge voltage and switching loss |
| CN1773858A (en) * | 2004-11-10 | 2006-05-17 | 三菱电机株式会社 | Power semiconductor device |
-
2007
- 2007-11-20 CN CN2007101877152A patent/CN101442302B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1407559A (en) * | 2001-08-29 | 2003-04-02 | 力旺电子股份有限公司 | Booster circuit |
| US6819149B2 (en) * | 2003-01-24 | 2004-11-16 | Mitsubishi Denki Kabushiki Kaisha | Gate drive device for reducing a surge voltage and switching loss |
| CN1773858A (en) * | 2004-11-10 | 2006-05-17 | 三菱电机株式会社 | Power semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101442302A (en) | 2009-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101442302B (en) | Gate drive circuit and drive method thereof | |
| JP3562725B2 (en) | Output buffer circuit and input / output buffer circuit | |
| CN106656148B (en) | Bidirectional IO circuit for preventing current from flowing backwards | |
| WO2003105193A2 (en) | Low-leakage integrated circuits and dynamic logic circuits | |
| IE861394L (en) | Input buffer | |
| CN101740097A (en) | Data transmitting system | |
| EP2241009A1 (en) | Low-swing cmos input circuit | |
| CN101753129B (en) | High-voltage tolerance output buffer | |
| CN108712166B (en) | Self-adaptive level conversion circuit | |
| CN102064818A (en) | Complementary metal oxide semiconductor (CMOS) input/output interface circuit | |
| US7893722B2 (en) | Clock control of state storage circuitry | |
| CN111082785A (en) | Control circuit | |
| CN102055459A (en) | Bias voltage generation to protect input/output (io) circuits during a failsafe operation and a tolerant operation | |
| US8677166B2 (en) | Semiconductor devices and systems-on-chip having the same | |
| CN105991125A (en) | Inverter circuit, stable-output dynamic comparator and comparison method | |
| CN113014077B (en) | High-voltage PN bridge gate driving circuit | |
| CN100492910C (en) | Level converter using base bias | |
| JP2010166457A (en) | Level shifting circuit and semiconductor device equipped with the same | |
| CN110164495A (en) | Reduce the quiescent dissipation circuit of LPDRAM under deep power down mode | |
| US20050151574A1 (en) | High voltage output level shifter | |
| TW200848976A (en) | Gate driving circuit and the driving method thereof | |
| CN115102539B (en) | Level shift circuit suitable for anti-fuse FPGA | |
| US20100034032A1 (en) | Data output circuit in a semiconductor memory apparatus | |
| US20050270065A1 (en) | Coms buffer having higher and lower voltage operation | |
| CN102751974B (en) | Output buffer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |