CN101421684B - Power converting device, and control method therefor - Google Patents

Abstract

In a flicker suppressing device for suppressing flickers by detecting a load current and outputting the current of the opposite phase, the load current may contain higher harmonics. In this case, the phase of the higher harmonic components to be outputted by the flicker suppressing device may be delayed by the current control delay, and the higher harmonic current of the load may be unable to be canceled, but the higher harmonics may be increased on the contrary. By the Fourier series expansion, therefore, the fundamental wave component amplitude of the load current is calculated to calculate the current command value of the flicker suppressing device on the basis of the calculated amplitude, so that the output current of the flicker suppressing device is controlled according to that current command value. By calculating the current command value from the Fourier series coefficient, the frequency component several times as high as the system frequency can be eliminated from the current command value, so that the flicker suppressing device can reduce the higher harmonics to flow out therefrom while suppressing the flickers.

Description

Power conversion unit and control method thereof

Technical field

The present invention relates to a kind of power conversion unit that is linked to AC system, especially relate to the variation in voltage (flicker: power conversion unit flicker) that inhibition produces because of load change.

Background technology

If be linked to the load change of system, the voltage drop change that is then produced by the impedance of power transmission line or transformer produces variation in voltage (flicker) at the point of contact of load.

For example in No. 2675206 communique of patent, propose to suppress the flicker restraining device of flicker.

Said apparatus is calculated effective current and idle current based on load current, calculates positive part through implementing low pass filter, calculates anti-phase part through implementing high-pass filter.Through the electric current of output with detected load current phase reversal, eliminate from the variation of the electric current of system's inflow, suppress flicker thus.

, when in load current, comprising higher harmonic components, in current instruction value, comprise higher harmonic components.

Constituting by power converter under the situation of electric current generation portion, owing to have the delay of Current Control, so the phase place of the higher harmonic components in the output current of power converter is with respect to the phase delay of the higher hamonic wave in the load current.Therefore, the higher harmonic components that generation is flowed in can not the elimination system can not obtain the problem of sufficient compensation effect.

Summary of the invention

In order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and it detects ac output current; With the Current Control parts; It controls ac output current; So that the output current command value is consistent with the output valve of said current detector; Have current instruction value and calculate device, it flow into detection the output valve fourier progression expanding method of current detector of the electric current of load, calculates said output current command value according to each output valve of this fourier progression expanding method.

In order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and it detects ac output current; The Current Control parts, it controls ac output current, so that the output current command value is consistent with the output valve of said current detector; And sine-wave generator; It produces two sine waves of same frequency and phase phasic difference 90 degree; Have current instruction value and calculate device; It multiplies each other the output valve of this sine-wave generator output valve with the current detector that detects the electric current that flow into load, calculates said output current command value according to this multiplied result being carried out the moving average calculated result.

In order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and it detects ac output current; The Current Control parts, it controls ac output current, so that the output current command value is consistent with the output valve of said current detector; And sine-wave generator; It produces two sine waves of same frequency and phase phasic difference 90 degree; Have current instruction value and calculate device; It multiplies each other the output valve of this sine-wave generator output valve with the current detector that detects the electric current flow into load, and calculating this multiplied result is the cycle integrated between integration period with the sinusoidal wave period of said sine-wave generator output, calculates the output current command value according to this cycle integrated value.

In order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and it detects ac output current; With the Current Control parts; It controls ac output current; So that the output current command value is consistent with said current detector output valve, have current instruction value and calculate device, it flow into detection the output valve fourier progression expanding method of current detector of the electric current of load; This fourier progression expanding method output valve is implemented to make the leading phase compensation filter computing of phase place, and the result calculates the output current command value according to this filtering operation.

In addition; Power conversion unit of the present invention is characterised in that: have current instruction value and calculate device; Its value after to the said multiplied result of moving average computing is implemented to make the leading phase compensation filter computing of phase place, and the result calculates the output current command value according to this filtering operation.

In addition, power conversion unit of the present invention is characterised in that: phase compensation filter is made up of the first-order lead delay filter.

In addition, power conversion unit of the present invention is characterised in that: phase compensation filter is made up of an incomplete differential.

In addition, power conversion unit of the present invention is characterised in that: the sinusoidal wave frequency of sine-wave generator output equates with the system frequency of binding.

In addition, power conversion unit of the present invention is characterised in that: the sinusoidal wave frequency of sine-wave generator output is the integral multiple of the system frequency of binding.

In addition, in order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and it detects ac output current; With the Current Control parts; It controls ac output current; So that the output current command value is consistent with said current detector output valve, have current instruction value and calculate device, it flow into detection the output valve fourier progression expanding method of current detector of the electric current of load; The gain of 2 overtones bands of the system frequency of this fourier progression expanding method output valve being implemented link is less than the filtering operation of the gain of system frequency, and the result calculates the output current command value according to this filtering operation.

In order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and it detects ac output current; The Current Control parts, it controls ac output current, so that the output current command value is consistent with said current detector output valve; And sine-wave generator; It produces two sine waves of same frequency and phase phasic difference 90 degree; Have current instruction value and calculate device; It multiplies each other the output valve of this sine-wave generator output valve with the current detector that detects the electric current that flow into load; Calculating this multiplied result is the cycle integrated between integration period with the sinusoidal wave period of said sine-wave generator output, and the gain of 2 overtones bands of the system frequency that this cycle integrated result is implemented to link is less than the filtering operation of the gain of system frequency, and the result calculates the output current command value according to this filtering operation.

In addition, in order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and it detects ac output current; The Current Control parts, it controls ac output current, so that the output current command value is consistent with said current detector output valve; And sine-wave generator; It produces two sine waves of same frequency and phase phasic difference 90 degree; Have current instruction value and calculate device; It multiplies each other the output valve of said sine-wave generator output valve with the current detector that detects the electric current that flow into load, and the gain of 2 overtones bands of the system frequency that enforcement links to the value after this multiplied result of moving average computing is less than the filtering operation of the gain of system frequency, and the result calculates the output current command value according to this filtering operation.

In addition, power conversion unit of the present invention is characterised in that: by the gain of 2 overtones bands of the notch filter construction system frequency wave filter less than the gain of system frequency.

In addition, power conversion unit of the present invention is characterised in that: through from input signal, deducting the BPF. output valve, the gain of 2 overtones bands that realizes system frequency is less than the wave filter of the gain of system frequency.

In addition, in order to address the above problem amplitude detecting method of the present invention; Signal according to the AC compounent that comprises the amplitude change detects this amplitude; It is characterized in that,, calculate said amplitude according to the value behind the output valve enforcement phase compensation filter of fourier progression expanding method.

In addition; In order to address the above problem, the control method of power conversion unit of the present invention changes service condition according to the electric current that flows in the voltage of the AC system that links or the system; It is characterized in that; With detected alternating voltage or system power fourier progression expanding method, use the value behind the value enforcement phase compensation filter that obtains by this fourier progression expanding method, the ac output voltage of power converter is changed.

In addition; In order to address the above problem; Power conversion unit of the present invention is characterised in that: the signal according to the AC compounent that comprises the amplitude change detects in the amplitude detecting method of this amplitude; According to the value behind the output valve enforcement phase compensation filter of fourier progression expanding method is calculated said amplitude, use the value of calculating that current instruction value is changed.

In addition; In order to address the above problem; Power conversion unit of the present invention is characterised in that: the electric current that in according to the voltage of the AC system that links or system, flows makes in the control method of the power conversion unit that service condition changes; With detected alternating voltage or system power fourier progression expanding method, use the value behind the value enforcement phase compensation filter that obtains by this fourier progression expanding method, the ac output voltage of power converter is changed.

In order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and its detection flow into the load current of load; Current detector, it detects ac output current; With the Current Control parts, it controls ac output current according to current instruction value, only compensates the fundametal compoment that comprises in the said load current.

In addition, power conversion unit of the present invention is characterised in that: the parts that extract the fundametal compoment of load current are fourier progression expanding method devices.

In addition, in order to address the above problem, power conversion unit of the present invention is characterised in that: possess: current detector, and it detects ac output current; With the Current Control parts; It controls ac output current; So that the output current command value is consistent with said current detector output valve, have the output current command value and calculate device, its output valve of current detector that flow into the electric current of load with detection is input; Extract the component that changes at the following amplitude of the above 30Hz of 0.1Hz in the first-harmonic, to the electric current of the addition of output current command value and this current component same phase.

In addition, power conversion unit of the present invention is characterised in that: utilize the fourier progression expanding method device to calculate the fundametal compoment in the following amplitude change of the above 30Hz of 0.1Hz.

In addition, power conversion unit of the present invention is characterised in that: have the phase supplementing and correcting arithmetical unit of the load current fundametal compoment that extracts being implemented the phase supplementing and correcting computing.

In addition, power conversion unit of the present invention is characterised in that: the phase delay that the computing of phase supplementing and correcting arithmetical unit compensation fourier progression expanding method device produces.

In addition, power conversion unit of the present invention is characterised in that: the phase supplementing and correcting arithmetical unit comprises the phase compensation of the delay of phase delay that the computing of fourier progression expanding method device produces and current controller.

In addition, in order to address the above problem, power conversion unit of the present invention possesses: current detector, and it detects ac output current; With the Current Control parts; It controls ac output current; So that the output current command value is consistent with said current detector output valve; Have the current detector that detects the electric current flow into load, the amplitude of the said higher harmonic components in the output current of power conversion unit to the ratio of the amplitude of the higher harmonic components in the load current less than the amplitude of higher harmonic components between the said number of times in the output current of power conversion unit ratio to the amplitude of higher harmonic components between the number of times in the load current.

In addition, power conversion unit of the present invention is characterised in that: the detection system electric current substitutes and detects the electric current that flow into load.

In addition; Power conversion unit of the present invention is characterised in that: infer load current according to the detected value of said system power and the ac output current detected value of power conversion unit output, calculate current instruction value with this load current presumed value as the detected value of the electric current that flow into load.

In addition, in order to address the above problem, power conversion unit of the present invention possesses: current detector, and it detects ac output current; With the Current Control parts; It controls ac output current; So that the output current command value is consistent with said current detector output valve; Current instruction value is the composite value of positive current instruction value and anti-phase current instruction value, said anti-phase current instruction value is limited in below the setting less than the rated current of said power conversion unit, and the positive current instruction value is constrained to rated current and the scope that is limited in the difference of the anti-phase current instruction value below the said setting of getting into.

In addition, in order to address the above problem, power conversion unit of the present invention possesses: current detector, and it detects ac output current; With the Current Control parts; It controls ac output current; So that the output current command value is consistent with said current detector output valve; Current instruction value is the composite value of positive current instruction value and anti-phase current instruction value, said positive current instruction value is limited in below the rated current of said power conversion unit, and the anti-phase current instruction value is constrained in the scope that gets into the difference of positive current instruction value in rated current and the rated current.

In addition, power conversion unit of the present invention is characterised in that: the anti-phase current instruction value is in the scope of the difference of rated current and positive current instruction value, and is limited in below the setting less than rated current.

In addition, power conversion unit of the present invention is characterised in that: through the anti-phase current instruction value multiply by variable gain, limit the anti-phase current instruction value.

In addition, power conversion unit of the present invention is characterised in that: utilize circular limiter restriction anti-phase electric current.

Description of drawings

Fig. 1 is the key diagram of the embodiment of the invention 1.

Fig. 2 is the key diagram of the embodiment of the invention 2.

Fig. 3 is that gain characteristic that the phase supplementing and correcting wave filter of the embodiment of the invention 2 produces is improved the key diagram that effect and phase propetry are improved effect.

Fig. 4 is another embodiment of the phase supplementing and correcting wave filter of the embodiment of the invention 2.

Fig. 5 is the key diagram of the embodiment of the invention 1.

Fig. 6 is the key diagram of the embodiment of the invention 3.

Fig. 7 is the key diagram of the first-harmonic DFT arithmetical unit of the embodiment of the invention 3.

Fig. 8 is the key diagram of 2 DFT arithmetical unit of the embodiment of the invention 3.

Fig. 9 is the action specification figure of the embodiment of the invention 1.

Figure 10 is the key diagram of the variation of the embodiment of the invention 1.

Figure 11 is the key diagram of the embodiment of the invention 4.

Figure 12 is another embodiment of the phase supplementing and correcting wave filter of the embodiment of the invention 4.

Figure 13 is the key diagram of the embodiment of the invention 4.

Embodiment

Below, with accompanying drawing an embodiment of the present invention is described.

(embodiment 1)

With Fig. 1 embodiments of the invention 1 are described.

Flicker restraining device 1 of the present invention is connected with load 3 parallelly connectedly, is connected in AC power 2 through system impedance 7.System impedance 7 refers to power transmission line impedance or transformer impedance.At the point of contact of flicker restraining device 1, if the load current change, the voltage drop amplitude variation that is then produced by system impedance 7 produces variation in voltage, i.e. flicker.The flicker that flicker restraining device inhibition/minimizing load current change of the present invention causes.

Flicker restraining device 1 is made up of with control operational part 100 main circuit portion.The power converter 4 that main circuit is made up of IGBT and diode, filter reactor (reactor) 5, direct current capacitors 6 constitute; Ac output end of power converter 4 is linked to AC system through filter reactor 5, and direct current capacitors 6 is connected in parallel in dc output end of power converter 4.

Control arithmetical unit 100 with point of contact voltage detecting value and the alternating current detected value of flicker restraining device 1, to reach direct current capacitors voltage detecting value be input, the current instruction value of calculating power converter 4 is to keep direct current capacitors voltage.

And; Calculate according to load current detected value and point of contact voltage detecting value and to be used to the current instruction value that suppresses to glimmer; With this current instruction value and the current instruction value sum that is used to keep said direct current capacitors voltage is the current instruction value of new power converter 4, and the ac output voltage command value of calculating power converter 4 makes the alternating current detected value of this current instruction value and power converter 4 consistent.

Control operational part 100 passes through relatively this ac output voltage command value and carrier wave, calculates to the signal of the IGBT of power converter 4, exports power converter 4 to, and the alternating voltage of command value is followed in output.

Below, the formation method of detailed description current instruction value.

At first, the command value operational method that is used to control direct current capacitors voltage is described.

Direct current capacitors voltage is detected by voltage-level detector 14, and detected value VDC is input to subtracter 104.

Subtracter 104 is calculated the poor of direct current capacitors voltage instruction value VDCREF and VDC, exports dc voltage controller 105 to.

Dc voltage controller 105 is input with the direct current capacitors voltage deviation, and the watt current command value IAVR that calculates flicker restraining device 1 is so that direct current capacitors voltage and instruction value VDCREF is consistent.Watt current command value IAVR is input to contrary d-q transducer 112.Contrary d-q transducer 112 according to after the flicker stated suppress output with current instruction value and dc voltage controller 105, calculate the current instruction value of the restraining device 1 that glimmers.

The explanation flicker suppresses the operational method with current instruction value below.

The voltage of system's point of contact of flicker restraining device 1 is detected by voltage sensor 10.Detected value Vu, Vv, Vw are input to phase detectors 101, calculate fundamental phase θ.Here, phase theta is that the fundametal compoment of establishing Vu is that the fundametal compoment of Vcos θ, Vv is the fundametal compoment of Vcos (θ-2/3 π), the Vw phase place when being Vcos (θ-4/3 π).

With phase theta input sine wave form 102,103, sinusoidal wave form 102,103 is calculated cos θ, sin θ respectively.Export cos θ, sin θ to positive DFT arithmetical unit 107, anti-phase DFT arithmetical unit 108, contrary d-q transducer 112, d-q transducer 113.

Load current is detected by current sensor 20,21,22, exports detected value ILU, ILV, ILW to alpha-beta transducer 106.

Alpha-beta transducer 106 is calculated IL α, IL β through the computing shown in the following formula.

$\left[\begin{array}{c}\mathrm{IL\α}\\ \mathrm{IL\β}\end{array}\right]=\left[\begin{array}{ccc}\frac{2}{3}& -\frac{1}{3}& -\frac{1}{3}\\ 0& \frac{1}{\sqrt{3}}& -\frac{1}{\sqrt{3}}\end{array}\right]\left[\begin{array}{c}\mathrm{ILU}\\ \mathrm{ILV}\\ \mathrm{ILW}\end{array}\right]$ (numerical expression 1)

Explanation is calculated as current instruction value aspect new among the present invention, that calculate based on the fourier series coefficient below.

To export positive DFT arithmetical unit 107, anti-phase DFT arithmetical unit 108 by IL α, the IL β that alpha-beta transducer 106 is calculated to.

Positive DFT arithmetical unit 107 is through the computing that (formula 2) illustrates, and calculates amplitude IL1RE and the amplitude IL1IM of positive imaginary axis component of the positive real axis component of load current.

$\left\{\begin{array}{c}\mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{RE}=2f_s\{{\&Integral;}_{t-T}^t(\mathrm{IL\&alpha;}\&times;\mathrm{Cos}\mathrm{\&theta;})\mathrm{Dt}+{\&Integral;}_{t-T}^t(\mathrm{IL\&beta;}\&times;\mathrm{Sin}\mathrm{\&theta;})\mathrm{Dt}\}\\ \mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{Im}=2f_s\{-{\&Integral;}_{t-T}^t(\mathrm{IL\&alpha;}\&times;\mathrm{Sin}\mathrm{\&theta;})\mathrm{Dt}+{\&Integral;}_{t-T}^t(\mathrm{IL\&beta;}\&times;\mathrm{Cos}\mathrm{\&theta;})\mathrm{Dt}\}\end{array}\right.$ (numerical expression 2)

Here, t is a current time, f _sBe the system frequency that links, T=1/f _s

Shown in 2, because the synchronous sine wave of cycle integrated and system voltage is long-pending, so for the load current component of the integral multiple of system frequency, be higher harmonic components, gain is zero.

IL α, when IL β is negative phase sequence component, the IL α of (numerical expression 2) * cos θ+IL β * sin θ and-IL α * sin θ+IL β * cos θ is the component that under the frequency multiplication of system frequency, vibrates, but because with power cycle T integration, so output valve is zero.

Anti-phase DFT arithmetical unit 109 is through the computing that (formula 3) illustrates, and calculates amplitude IL2RE and the amplitude IL2IM of anti-phase imaginary axis component of the anti-phase real axis component of load current.

$\left\{\begin{array}{c}\mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{RE}=2f_s\{{\&Integral;}_{t-T}^t(\mathrm{IL\&alpha;}\&times;\mathrm{Cos}\mathrm{\&theta;})\mathrm{Dt}-{\&Integral;}_{t-T}^t(\mathrm{IL\&beta;}\&times;\mathrm{Sin}\mathrm{\&theta;})\mathrm{Dt}\}\\ \mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{Im}=2f_s\{{\&Integral;}_{t-T}^t(\mathrm{IL\&alpha;}\&times;\mathrm{Sin}\mathrm{\&theta;})\mathrm{Dt}+{\&Integral;}_{t-T}^t(\mathrm{IL\&beta;}\&times;\mathrm{Cos}\mathrm{\&theta;})\mathrm{Dt}\}\end{array}\right.$ (numerical expression 3)

Here, t is a current time, f _sBe the system frequency that links, T=1/f _s

Shown in (numerical expression 3), because the synchronous sine wave of cycle integrated and system voltage is long-pending, so for the load current component of the integral multiple of system frequency, be higher harmonic components, gain is zero.

When IL α, IL β are positive phase component, the component of the IL α of (formula 3) * cos θ-IL β * sin θ and IL α * sin θ+IL β * cos θ under the frequency multiplication of system frequency, vibrating, but because with power cycle T integration, so output valve is zero.

Load current shown in (formula 4), establish shown in Fig. 9 that fundamental frequency is that 60Hz, positive amplitude are that 1pu, anti-phase amplitude are 0.2pu, to contain the higher hamonic wave number of times be 5 times, the waveform of IL α when the higher hamonic wave amplitude is 0.05pu, IL β, IL1RE, IL1IM, IL2RE, IL2IM.

$\left\{\begin{array}{c}\mathrm{ILU}=\mathrm{Cos}(120\mathrm{\&pi;\; t}+\mathrm{\&phi;})+0.2\mathrm{Cos}(-120\mathrm{\&pi;\; t}+\mathrm{\&eta;})+0.05\mathrm{Cos}\left(600\mathrm{\&pi;\; t}\right)\\ \mathrm{ILV}=\mathrm{Cos}(120\mathrm{\&pi;\; t}-\frac{2}{3}\mathrm{\&pi;}+\mathrm{\&phi;})+0.2\mathrm{Cos}(-120\mathrm{\&pi;\; t}-\frac{2}{3}\mathrm{\&pi;}+\mathrm{\&eta;})+0.05\mathrm{Cos}(600\mathrm{\&pi;\; t}-\frac{2}{3}\mathrm{\&pi;})\\ \mathrm{ILW}=\mathrm{Cos}(120\mathrm{\&pi;\; t}-\frac{4}{3}\mathrm{\&pi;}+\mathrm{\&phi;})+0.2\mathrm{Cos}(-120\mathrm{\&pi;\; t}-\frac{4}{3}\mathrm{\&pi;}+\mathrm{\&eta;})+0.05\mathrm{Cos}(600\mathrm{\&pi;\; t}-\frac{4}{3}\mathrm{\&pi;})\end{array}\right.$ (numerical expression 4)

Here, Φ is the phase place of positive phase current, and η is the phase place of anti-phase electric current, Φ=η=0.

Can know owing to comprise higher hamonic wave, thus in IL α, IL β, comprise distortion component, but in IL1RE, IL1IM, IL2RE, IL2IM, do not produce distortion component, can eliminate higher hamonic wave.

And; Can know through cycle integrated IL1RE, IL2RE; Can get rid of that anti-phase in the positive computing is sneaked into, the positive in the anti-phase computing sneaks into, and the value of IL1RE, IL2RE respectively with load current in positive phase component amplitude, negative phase sequence component amplitude consistent, can accurately realize the amplitude computing.

When load 3 no changes; IL1RE, IL1IM, IL2RE, IL2IM are respectively positive active constituent amplitude, positive reactive component amplitude, anti-phase real axis component amplitude, the anti-phase imaginary axis component amplitude of load current; But when load 3 changes, the cycle integrated value of the positive phase component in negative phase sequence component in the positive DFT arithmetical unit 107 and the anti-phase DFT arithmetical unit 109 not exclusively is zero.Therefore, because the frequency multiplication component is not the amplitude of genuine positive phase component, negative phase sequence component, so expectation is removed from command value.

For the above reasons, with the output IL1IM input notch filter 108 of positive DFT arithmetical unit 107, will be by the contrary d-q transducer 112 of value IL1IM2 input behind the frequency multiplication component of notch filter 108 removal system frequencies.

Likewise, with the output IL2RE of anti-phase DFT arithmetical unit 109 input notch filter 110, IL2IM is imported notch filter 111, with the value IL2RE2 behind the frequency multiplication component of removing system frequency, IL2IM2 input d-q transducer 113.

Contrary d-q transducer 112 is input with the output of dc voltage controller 105 with notch filter 108, baseline sinusoidal wave cos θ, sin θ, and positive part current instruction value IL1 α, IL1 β are calculated in the computing that enforcement (numerical expression 5) illustrates.

$\left[\begin{array}{c}\mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{\&alpha;}\\ \mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{\&beta;}\end{array}\right]=\left[\begin{array}{cc}\mathrm{Cos}\mathrm{\&theta;}& -\mathrm{Sin}\mathrm{\&theta;}\\ \mathrm{Sin}\mathrm{\&theta;}& \mathrm{Cos}\mathrm{\&theta;}\end{array}\right]\left[\begin{array}{c}\mathrm{<figure-callout\; id="1"\; label="IAVR\; IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IAVR</figure-callout>}& \\ \mathrm{IL}1\mathrm{IM}2\end{array}\right]$ (numerical expression 5)

D-q transducer 113 is input with output valve IL2RE2, IL2IM2, baseline sinusoidal wave cos θ, the sin θ of notch filter 109,110, implements the computing that (numerical expression 6) illustrates, and calculates anti-phase part current instruction value IL2 α, IL2 β.

$\left[\begin{array}{c}\mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{\&alpha;}\\ \mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{\&beta;}\end{array}\right]=\left[\begin{array}{cc}\mathrm{Cos}\mathrm{\&theta;}& \mathrm{Sin}\mathrm{\&theta;}\\ -\mathrm{Sin}\mathrm{\&theta;}& \mathrm{Cos}\mathrm{\&theta;}\end{array}\right]\left[\begin{array}{c}\mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{<figure-callout\; id="2"\; label="RE"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">RE</figure-callout>}2\\ \mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{IM}2\end{array}\right]$ (numerical expression 6)

To be input to totalizer 114,115 against the output of d-q transducer 112, d-q transducer 113.Because flicker restraining device 1 suppresses flicker through the output and the electric current of load current phase reversal, the value after reverse is current instruction value IC α REF, the Ic β REF of flicker restraining device 1 so the output of establishing totalizer 114,115 is by code reverser 116,117 codes.

As stated, current instruction value IC α REF, IC β REF are calculated by dc voltage controller 105, positive DFT arithmetical unit 107, anti-phase DFT arithmetical unit 109, so in current instruction value, do not comprise higher harmonic components.

In addition; The alternating current of flicker restraining device 1 output is detected by current sensor 11,12,13; Detected value ICU, ICV, ICW are implemented and (numerical expression 1) same computing by alpha-beta transducer 118, export its output IC α, IC β to subtracter 119,120 respectively.

The deviation of operation current command value Ic α REF and Ic α in subtracter 119, the deviation of operation current command value Ic β REF and IC β is input to current controller 121 with its output in subtracter 120.

Current controller 121 is calculated ac output voltage revisal amount in order to reduce the current deviation of being calculated by subtracter 119,120.

Utilize totalizer 123,124 with the output valve of current controller 121 and by voltage V α, V β addition behind alpha-beta transducer 122 conversion alternating voltage detected value Vu, Vv, the Vw.The computing of alpha-beta transducer 122 is same with (numerical expression 1).

The output valve V β REF of the output valve V α REF of totalizer 123 and totalizer 124 is imported 2 phase converter 125 mutually-3,, calculate voltage instruction value VuREF, VvREF, the VwREF of 3 phases through the computing that (numerical expression 7) illustrates.

$\left[\begin{array}{c}\mathrm{VuREF}\\ \mathrm{VvREF}\\ \mathrm{VwREF}\end{array}\right]=\left[\begin{array}{cc}1& 0\\ -\frac{1}{2}& \frac{\sqrt{3}}{2}\\ -\frac{1}{2}& -\frac{\sqrt{3}}{2}\end{array}\right]\left[\begin{array}{c}\mathrm{V\&alpha;\; REF}\\ \mathrm{V\&beta;\; REF}\end{array}\right]$ (numerical expression 7)

With the output valve input PWM arithmetical unit 126 of 2 phases-3 phase converter 125, the triangular wave of calculating device 127 outputs with carrier wave carries out size relatively.PWM arithmetical unit 126 is calculated the IGBT signal of power converter 4 according to big or small comparative result, exports power converter 4 to.

Power converter 4 is exported the alternating voltage according to voltage instruction value VuREF, VvREF, VwREF through according to by the signal conducting of PWM arithmetical unit 126 outputs, by IGBT.

As stated, because for the ac output current of the restraining device 1 that suppresses to glimmer, the flicker restraining device, can suppress to glimmer so can reduce the variation of system power to the positive idle current of load current and the electric current of negative phase sequence component output phase reversal.

In the present embodiment; Detect load current by current sensor 20,21,22; But of Fig. 5, even if infer load current ILU, ILV, ILW, also can obtain same effect from system power ISU, ISV, ISW and flicker restraining device output current ICU, ICV, ICW.

And of Figure 10, through the detection system electric current, the electric current to its positive idle current and negative phase sequence component output phase reversal also can obtain same effect.

According to above-mentioned because the positive idle current of flicker restraining device output load current of the present invention and with the electric current of negative phase sequence component phase reversal, so can reduce the variation of system power, can suppress flicker.

And based on the present invention, owing to do not comprise higher hamonic wave in the current instruction value, so can reduce the higher harmonic components that flows out from flicker restraining device 1, the higher hamonic wave that can avoid Current Control to postpone to cause increases.

(embodiment 2)

With Fig. 2 embodiments of the invention 2 are described.

The difference of present embodiment and embodiment 1 is, in the output of DFT arithmetical unit, phase supplementing and correcting is set and uses wave filter.Use wave filter through phase supplementing and correcting is set, can improve operating lag the load current amplitude of first harmonic change of positive, anti-phase.

Below, only explanation and last embodiment various structure.And, in Fig. 2, except that mentioning especially,, do not carry out repeat specification to attaching with same-sign with Fig. 1 identical function portion.

The advantage of positive DFT arithmetical unit 107 and anti-phase DFT arithmetical unit 109 is; Extract positive fundametal compoment and anti-phase fundametal compoment respectively; Can remove higher harmonic components, but shown in (numerical expression 2), (numerical expression 3), owing to comprise integration in the computing; So change when fast at the amplitude of first-harmonic, produce gain in the amplitude operation result and reduce and phase delay.

Gain reduces and phase delay becomes the reason that the flicker inhibit feature is reduced.

The gain reduction and the phase delay of the amplitude operation result when the flicker restraining device of present embodiment reduces the amplitude of first harmonic change in the load current.

The flicker restraining device 1 and the embodiment 1 of present embodiment likewise calculate positive idle current amplitude IL1IM through anti-phase DFT arithmetical unit 107.Its output is input to phase supplementing and correcting wave filter 130, its output is input to notch filter 108.

The transport function G of phase supplementing and correcting wave filter 130 (s) is the leading delay filter that (numerical expression 8) illustrates.

$G\left(s\right)=\frac{1+T_2\mathrm{<figure-callout\; id="1"\; label="s"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">s</figure-callout>}}{1+T_{1}s}$ (numerical expression 8)

Here, T ₁, T ₂Be time constant, s is the Laplace's operation symbol.Through using this wave filter, can improve gain characteristic, phase propetry.

Likewise, with the output input phase revisal wave filter 131,132 of anti-phase DFT arithmetical unit 109.Phase supplementing and correcting wave filter the 131, the 132nd, the leading delay filter identical with phase supplementing and correcting wave filter 130.

For example, load current shown in (numerical expression 9), the electric current that under frequency f, changes for amplitude I (t).

$\left\{\begin{array}{c}\mathrm{ILU}=I\left(t\right)I\mathrm{Cos}(\mathrm{\&theta;}-\frac{\mathrm{\&pi;}}{2})=I\mathrm{Cos}\left(2\mathrm{\&pi;\; Ft}\right)\mathrm{Cos}(\mathrm{\&theta;}-\frac{\mathrm{\&pi;}}{2})\\ \mathrm{ILV}=I\left(t\right)\mathrm{Cos}(\mathrm{\&theta;}-\frac{\mathrm{\&pi;}}{2}-\frac{2}{3}\mathrm{\&pi;})=I\mathrm{Cos}\left(2\mathrm{\&pi;\; Ft}\right)\mathrm{Cos}(\mathrm{\&theta;}-\frac{\mathrm{\&pi;}}{2}-\frac{2}{3}\mathrm{\&pi;})\\ \mathrm{ILW}=I\left(t\right)\mathrm{Cos}(\mathrm{\&theta;}-\frac{\mathrm{\&pi;}}{2}-\frac{4}{3}\mathrm{\&pi;})=I\mathrm{Cos}\left(2\mathrm{\&pi;\; Ft}\right)\mathrm{Cos}(\mathrm{\&theta;}-\frac{\mathrm{\&pi;}}{2}-\frac{4}{3}\mathrm{\&pi;})\end{array}\right.$ (numerical expression 9)

The transmission characteristic of output IL1IMFIL from current amplitude I (t) to phase supplementing and correcting wave filter 130 shown in Fig. 4.

Transverse axis is amplitude variation frequency f, and the longitudinal axis is represented phase place in Fig. 3 (a) expression gain in Fig. 3 (b).And, dot the frequency characteristic when not using the phase supplementing and correcting wave filter, the frequency characteristic when representing to use the phase supplementing and correcting wave filter with solid line.Here, the system frequency of setting up departments is 60Hz, T ₁=1/100 [s], T ₂=1/350 [s].

Can know since transmission characteristic be equivalent to gain more near 0dB, phase place more near Odeg, then can extract more coefficient, so can improve gain characteristic, phase propetry through use leading delay filter according to Fig. 3 near amplitude of first harmonic I (t).Because people's visibility factor is of the Figure 12 that speciallys permit No. 2793327 communique, and is big to the variation in voltage of 0.1Hz～30Hz, so can improve the flicker inhibit feature greatly.

In the present embodiment; If the phase supplementing and correcting wave filter is the first-order lead delay filter; Even if but made up the wave filter of the leading delay filter of a plurality of phase places or, also can obtain same effect like the said phase supplementing and correcting wave filter that has made up incomplete differential of Fig. 4.

According to above-mentioned because the positive idle current of flicker restraining device output load current of the present invention and with the electric current of negative phase sequence component phase reversal, so can reduce the variation of system power, can suppress flicker.

And based on the present invention, owing to do not comprise higher hamonic wave in the current instruction value, so can reduce the higher harmonic components that flows out from flicker restraining device 1, the higher hamonic wave that can avoid Current Control to postpone to cause increases.

And,, owing to can improve the transmission characteristic of DFT arithmetic unit, change the flicker inhibit feature when fast so can improve amplitude of first harmonic based on present embodiment.

(embodiment 3)

With Fig. 6 the embodiment of the invention 3 is described.

The difference of present embodiment and embodiment 1 is, except that first-harmonic, DFT is set 2 times, calculates amplitude, the phase place of 2 higher harmonic components, is added in the current instruction value.

If the low higher hamonic wave of number of times, then the delay of Current Control is little.Therefore, not only export first-harmonic, also the offset current of exportable specific higher hamonic wave.For example, because when establishing the Current Control response for 1000rad/s, cutoff frequency is 160Hz, so when system frequency is 60Hz, can guarantee current controling characteristic to 2 time higher hamonic wave degree.In the present embodiment, establishing specific higher hamonic wave is 2 higher hamonic waves.

After, only explanation and last embodiment various structure.And, in Fig. 5, except that mentioning especially,, do not carry out repeat specification to paying same-sign with Fig. 1 identical function portion.

The output of dc voltage controller 105, the output of sinusoidal wave form 102,103 of output and the sine wave that output has the system voltage phase place of alpha-beta transducer 106 of calculating the alpha-beta component of load current are input to first-harmonic DFT arithmetical unit 150.First-harmonic DFT arithmetical unit 150 is as shown in Figure 6, implements the computing same with embodiment 1, calculates current instruction value IC α REF, IC β REF.

Below the explanation as aspect new in the present embodiment, 2 higher harmonic current calculation methods.

The phase theta of being calculated by phase detectors 101 by 2 times, is input to sinusoidal wave form 155,156 with its output by multiplier 154.

Sinusoidal wave form 155 is calculated cos2 θ from phase place 2 θ by multiplier 154 outputs, and sinusoidal wave form 156 is calculated sin2 θ, exports DFT arithmetical unit 151 to 2 times.

2 DFT arithmetical unit 151 in addition; Also the output valve with alpha-beta transducer 106 is input; Calculate real axis component amplitude, the imaginary axis component amplitude of 2 higher hamonic waves that comprise in the load current, from this value calculate with load current current instruction value IC α REF2, the IC β REF2 of 2 higher harmonic components phase reversals comprising.

With the output of first-harmonic DFT arithmetical unit 150 and the output difference input summer 152,153 of 2 DFT arithmetical unit 151, calculate new current instruction value IC α REF_N, IC β REF_N.

As stated, the flicker restraining device of present embodiment extracts the fundametal compoment and 2 component of degree n ns of load current, calculates the current instruction value of phase reversal.Because as 2 times, for the higher harmonic current instruction of low order, the delay in the Current Control is little, so can avoid higher hamonic wave to increase phenomenon.

Below, the details of 2 DFT arithmetical unit 151 is described.

The operation blocks of 2 DFT arithmetical unit 151 shown in Fig. 7.

With load current IL α, IL β and sinusoidal wave cos2 θ, sin2 input positive DFT arithmetical unit 1511.Positive DFT arithmetical unit 1511 is implemented the computing that (numerical expression 10) illustrates, and calculates IL1RE2, IL1IM2.

$\left\{\begin{array}{c}\mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{<figure-callout\; id="2"\; label="RE"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">RE</figure-callout>}2=4f_s\{{\&Integral;}_{t-T/2}^t(\mathrm{IL\&alpha;}\&times;\mathrm{<figure-callout\; id="2"\; label="Cos"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Cos</figure-callout>}2\mathrm{\&theta;})\mathrm{Dt}+{\&Integral;}_{t-T/2}^t(\mathrm{IL\&beta;}\&times;\mathrm{<figure-callout\; id="2"\; label="Sin"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Sin</figure-callout>}2\mathrm{\&theta;})\mathrm{Dt}\}\\ \mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{<figure-callout\; id="2"\; label="Im"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Im</figure-callout>}2=4f_s\{-{\&Integral;}_{t-T/2}^t(\mathrm{IL\&alpha;}\&times;\mathrm{<figure-callout\; id="2"\; label="Sin"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Sin</figure-callout>}2\mathrm{\&theta;})\mathrm{Dt}+{\&Integral;}_{t-T/2}^t(\mathrm{IL\&beta;}\&times;\mathrm{<figure-callout\; id="2"\; label="Cos"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Cos</figure-callout>}2\mathrm{\&theta;})\mathrm{Dt}\}\end{array}\right.$ (numerical expression 10)

Here, fs is a system frequency, T=1/fs.Compare difference with (numerical expression 2) and be, integral coefficient becomes 2 times, becomes 1/2 integral time.

IL1RE2, IL1IM2 and (numerical expression 2) are likewise for sinusoidal wave cos2 θ, 2 times positive real axis component when sin2 θ is benchmark, positive imaginary axis component.

Anti-phase DFT arithmetical unit 1512 is implemented the computing that (numerical expression 11) illustrates, and calculates output IL2RE2, TL2IM2.

$\left\{\begin{array}{c}\mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{<figure-callout\; id="2"\; label="RE"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">RE</figure-callout>}2=4f_s\{{\&Integral;}_{t-T/2}^t(\mathrm{IL\&alpha;}\&times;\mathrm{<figure-callout\; id="2"\; label="Cos"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Cos</figure-callout>}2\mathrm{\&theta;})\mathrm{Dt}-{\&Integral;}_{t-T/2}^t(\mathrm{IL\&beta;}\&times;\mathrm{<figure-callout\; id="2"\; label="Sin"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Sin</figure-callout>}2\mathrm{\&theta;})\mathrm{Dt}\}\\ \mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{<figure-callout\; id="2"\; label="Im"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Im</figure-callout>}2=4f_s\{{\&Integral;}_{t-T/2}^t(\mathrm{IL\&alpha;}\&times;\mathrm{<figure-callout\; id="2"\; label="Sin"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Sin</figure-callout>}2\mathrm{\&theta;})\mathrm{Dt}+{\&Integral;}_{t-T/2}^t(\mathrm{IL\&beta;}\&times;\mathrm{<figure-callout\; id="2"\; label="Cos"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Cos</figure-callout>}2\mathrm{\&theta;})\mathrm{Dt}\}\end{array}\right.$ (numerical expression 11)

IL2RE2, IL2IM2 and (numerical expression 3) are likewise for sinusoidal wave cos2 θ, 5 times anti-phase real axis component, anti-phase imaginary axis component when sin2 θ is benchmark.

With the output input notch filter 1513,1514 of positive DFT arithmetical unit 1511, remove 4 times frequency component of system frequency, the contrary d-q transducer 1517 of input.

Contrary d-q transducer 1517 is implemented the computing that (numerical expression 12) illustrates, output output IL1 α 2, IL1 β 2 according to the output of notch filter 1513,1514 and sinusoidal wave cos2 θ, sin2 θ.

$\left[\begin{array}{c}\mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{\&alpha;}2\\ \mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{\&beta;}2\end{array}\right]=\left[\begin{array}{cc}\mathrm{<figure-callout\; id="2"\; label="Cos"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Cos</figure-callout>}2\mathrm{\&theta;}& -\mathrm{<figure-callout\; id="2"\; label="Sin"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Sin</figure-callout>}2\mathrm{\&theta;}\\ \mathrm{<figure-callout\; id="2"\; label="Sin"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Sin</figure-callout>}2\mathrm{\&theta;}& \mathrm{<figure-callout\; id="2"\; label="Cos"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Cos</figure-callout>}2\mathrm{\&theta;}\end{array}\right]\left[\begin{array}{c}\mathrm{<figure-callout\; id="1"\; label="IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">IL</figure-callout>}1\mathrm{RE}2\mathrm{<figure-callout\; id="1"\; label="N\; IL"\; filenames="H2007800133675E00081.png"\; state="\{\{state\}\}">N</figure-callout>}& \\ \mathrm{IL}1\mathrm{IM}2N\end{array}\right]$ (numerical expression 12)

To export totalizer 1519,1520 to against the output IL1 α 5 of d-q transducer 1517, the output of IL1 β 5.

With the output input notch filter 1515,1516 of anti-phase DFT arithmetical unit 1512, remove 4 times frequency component of system frequency, input d-q transducer 1518.

D-q transducer 1518 is implemented the computing that (numerical expression 13) illustrates, output output IL2 α 2, IL2 β 2 according to the output of notch filter 1515,1516 and sinusoidal wave cos5 θ, sin5 θ.

$\left[\begin{array}{c}\mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{\&alpha;}2\\ \mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{\&beta;}2\end{array}\right]=\left[\begin{array}{cc}\mathrm{<figure-callout\; id="2"\; label="Cos"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Cos</figure-callout>}2\mathrm{\&theta;}& \mathrm{<figure-callout\; id="2"\; label="Sin"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Sin</figure-callout>}2\mathrm{\&theta;}\\ -\mathrm{<figure-callout\; id="2"\; label="Sin"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Sin</figure-callout>}2\mathrm{\&theta;}& \mathrm{<figure-callout\; id="2"\; label="Cos"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">Cos</figure-callout>}2\mathrm{\&theta;}\end{array}\right]\left[\begin{array}{c}\mathrm{<figure-callout\; id="2"\; label="IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">IL</figure-callout>}2\mathrm{RE}2\mathrm{<figure-callout\; id="2"\; label="N\; IL"\; filenames="H2007800133675E00021.png,H2007800133675E00101.png"\; state="\{\{state\}\}">N</figure-callout>}& \\ \mathrm{IL}2\mathrm{IM}2N\end{array}\right]$ (numerical expression 13)

Export the output IL2 α 2 of d-q transducer 1518, the output of IL2 β 2 to totalizer 1519,1520.

The output of contrary d-q transducer 1517 of totalizer 1519,1520 additions and d-q transducer 1518, with its with export code reverser 1521,1522 to.

By the reverse value of code reverser 1521,1522 codes and 2 higher harmonic components phase reversals of load, be the output of 2 DFT arithmetical unit 151.

According to above-mentioned, according to present embodiment, except that first-harmonic, also can calculate with load current in the current instruction value of 2 higher harmonic components phase reversals comprising.

Because the delay of Current Control is little for the low order higher harmonic components,, can realize suppressing based on the flicker of 2 higher hamonic waves so can reduce 2 component of degree n ns of the system of flowing out to.

Selecting 2 times in the present embodiment as specific higher hamonic wave, is 3 inferior low order higher hamonic waves but also can select the higher hamonic wave number of times.And, also can possess compensation 2 times, the DFT arithmetical unit of 3 inferior a plurality of low order higher hamonic waves.

According to above-mentioned because the positive idle current of flicker restraining device output load current of the present invention and with the electric current of negative phase sequence component phase reversal, so can reduce the variation of system power, can suppress flicker.

And based on the present invention, owing to do not comprise higher hamonic wave in the current instruction value, so can reduce the higher harmonic components that flows out from flicker restraining device 1, the higher hamonic wave that can avoid Current Control to postpone to cause increases.

And, according to present embodiment, owing to can calculate offset current to the specific higher hamonic wave that comprises in the load current, so can reduce the flicker that causes by the low order higher hamonic wave.

(embodiment 4)

With Figure 11 the embodiment of the invention 5 is described.

The difference of present embodiment and embodiment 1 is current instruction value is provided with limiter 160.

If output anti-phase electric current, the pulsation that then produces the frequency multiplication of system frequency in the direct current capacitors.Because when the change of direct current capacitors voltage is big, becomes the capacitor heating or flow out the reason of higher hamonic wave, so expectation direct current capacitors voltage is suppressed in the specialized range (for example for rated voltage 10%) from power conversion unit.

, worry that then from the phase relation collapse of the anti-phase electric current of the phase place of the anti-phase electric current of power conversion unit output and load generating, flicker suppresses the effect reduction if limit real component, the imaginary part component of anti-phase electric current individually with fixed value.

The present invention considers the problems referred to above, utilizes circular limiter restriction anti-phase electric current, keeps phase relation, only limits compensation rate.

Details is described below.

In Figure 11, with command value IAVR, the output valve IL1IM2 of notch filter 108,110,111, IL2RE2, the IL2IM2 input chopper 160 of dc voltage controller 105.

Limiter 160 restriction current instruction values are suppressed in the output-current rating IMAX with system power ICU, ICV, ICW with power converter 1 output.

Specifically, implement the output valve IL1IM2 of output IAVR that setting priority is a dc voltage controller 105, notch filter 108 and become the limiter computing of order of current instruction value IL2RE2, the IL2IM2 of anti-phase current instruction value.

The structure of limiter shown in Figure 12 160.

The output valve IAVR of dc voltage controller 105 is limited in-below the above IMAX of IMAX, as new positive watt current command value IAVR2, is exported to against d-q transducer 112 by limiter 1601.

Calculate the square value of IMAX by multiplier 1602, calculate the square value of IAVR2, calculate both poor, export square root to and calculate device 1605 with subtracter 1604 by multiplier 1603.

The output valve that square root is calculated device 1605 becomes the higher limit of the limiter 1606 of positive idle current, and the value by multiplier 1607 codes after reverse becomes the lower limit of limiter 1606.The output valve of limiter 1606 becomes new positive idle current command value IL1IM3, exports contrary d-q transducer 112 to.

Through this computing, the amplitude of positive phase current becomes below the IMAX.

Positive watt current command value IAVR2 and positive idle current command value IL1IM3 are input to amplitude and calculate device 1608, output positive current instruction value amplitude I1ABS.

Power converter IMAX and amplitude I1ABS are input to subtracter 1609, and its difference exports minimum value to and calculates device 1611.Because the output valve of subtracter 1609 is the values that deducted the positive current instruction value from the rated current of power conversion unit 1; So if the amplitude of anti-phase current instruction value is poor less than this, then the output current command value of power conversion unit 1 is no more than rated current IMAX.

The method for limiting of anti-phase electric current then is described.

Anti-phase electric current real component IL2RE2 and imaginary part component IL2IM2 input amplitude are calculated device 1610, calculate anti-phase current instruction value amplitude I2ABS.This amplitude is input to minimum value and calculates device 1611.

In addition, the anti-phase current maxima I2MAX that is confirmed by the permission amplitude of direct current capacitors voltage also imports minimum value and calculates device 1611.

It is input to have deducted the value behind the positive current instruction value amplitude of rated current and anti-phase electric current permissible value I2MAX, anti-phase current instruction value amplitude I2ABS that minimum value is calculated device 1611, exports the value of minimum to divider 1612.

Divider 1612 is calculated minimum value the result of device 1611 divided by anti-phase current instruction value amplitude, exports its merchant to multiplier 1613,1614.

Multiplier 1613,1614 multiplies each other the output valve of anti-phase current instruction value IL2RE, IL2IM2 and divider 1613, calculates new anti-phase electric current I L2RE3, IL2IM3.

Through above-mentioned, because minimum electric current is consistent in the enough and to spare that electric current is exported in anti-phase current instruction value amplitude and the rated current, anti-phase current maxima, anti-phase electric current, so can limit the anti-phase electric current.

Owing to can limit the anti-phase current instruction value, so can limit the amplitude of fluctuation of direct current capacitors voltage.

In the present embodiment, show and establish positive phase current the computing when being preferential, but also can establish the anti-phase electric current for preferential, the restriction current instruction value.

Limiter 160 when to establish the anti-phase electric current shown in Figure 13 be preferential.

Anti-phase current instruction value IL2RE2, IL2IM2 are imported into amplitude and calculate device 1610, export amplitude I2ABS to minimum value and calculate device 1611 and divider 1612.

Anti-phase electric current permissible value I2MAX also is input to minimum value calculates device 1611, with value little export divider 1612 and subtracter 1609 to.

The output valve that divider 1612 is calculated device with minimum value exports its value to multiplier 1613,1614 divided by I2ABS.

Respectively anti-phase real component IL2RE2 and anti-phase imaginary part component IL2IM2 are input to multiplier 1613,1614, become new anti-phase current instruction value IL2RE3, IL2IM3, export d-q transducer 113 to.

Thus, because the amplitude of anti-phase current instruction value becomes below the I2MAX, so can suppress the amplitude of direct current capacitors voltage.

It is poor that the difference of the rated current IMAX of power conversion unit 1 and anti-phase current instruction value amplitude is calculated by subtracter 1609, becomes limiter 1601 higher limits of restriction positive current instruction value IAVR, and the value behind the code half reverse of subtracter 1609 becomes lower limit.

The output valve of subtracter 1609 outputs to multiplier 1607, calculates square value.In addition, also be input to multiplier 1603 by the positive active constituent IAVR2 of limiter 1601 restriction, it is poor to be calculated by subtracter 1604, and the value that square root calculation goes out is the higher limit of limiter 1606, and the value of code after reverse is the lower limit of limiter 1606.

Therefore, can preferentially limit the anti-phase current instruction value, positive phase current is limited in the residual current scope of relative rated current.

Through above-mentioned because the positive idle current of flicker restraining device of the present invention output and load current and with the electric current of negative phase sequence component phase reversal, so can reduce the variation of system power, can suppress flicker.

In addition, based on the present invention, owing to do not comprise higher hamonic wave in the current instruction value, so can reduce the higher harmonic components that flows out from power conversion unit 1, the higher hamonic wave that can avoid Current Control to postpone to cause increases.

And, according to present embodiment, owing to can the anti-phase electric current be suppressed at below the setting, so can suppress the amplitude of fluctuation of direct current capacitors voltage.

In the above-mentioned embodiment that illustrates; Because through utilizing the fourier series coefficient to calculate current instruction value; Therefore can from current instruction value, remove the frequency component of the integral multiple of system frequency, so but flicker restraining device limit suppresses flicker, the higher hamonic wave that flows out from the flicker restraining device is reduced on the limit.

Utilizability on the industry

The present invention especially suppresses the power conversion unit because of the variation in voltage (flicker) that load change produces applicable to the power conversion unit that is linked to AC system.

Claims (7)

1. a power conversion unit is characterized in that,

Possess: current detector, it detects ac output current; The power converter that constitutes by IGBT and diode; Calculate the control operational part of the power command value of said power converter,

Said control operational part has:

The load current that flow into load is transformed to the first alpha-beta transducer of two phases from three-phase;

Positive DFT arithmetical unit, it will carry out fourier progression expanding method through the output valve that the said first alpha-beta transducer is calculated, and calculate the amplitude of positive imaginary axis component of amplitude and load current of the positive real axis component of load current;

Reverse DFT arithmetical unit, it will carry out fourier progression expanding method through the output valve that the said first alpha-beta transducer is calculated, and calculate the amplitude of anti-phase imaginary axis component of amplitude and load current of the anti-phase real axis component of load current;

With the output valve addition of the amplitude of the anti-phase imaginary axis component of the output valve of the amplitude of the positive imaginary axis component of said positive DFT arithmetical unit and said reverse DFT arithmetical unit, calculate the totalizer of current instruction value;

The output valve of said current detector is transformed to the second alpha-beta transducer of two phases from three-phase;

The totalizer of the output valve addition of calculating with the output valve of said totalizer with through the said second alpha-beta transducer;

The control ac output current is so that the said current instruction value current controller consistent with the output valve of said current detector; With

The output valve of said current controller is changed to the two phases-three-phase inverter of three-phase from two phase transformations,

The output of the said first alpha-beta transducer is through said positive DFT arithmetical unit and said reverse DFT arithmetical unit; Addition behind wave filter computing, contrary d-q transducer and d-q transducer is subtracted each other through the output of code reverser and the said second alpha-beta transducer afterwards again.

2. power conversion unit according to claim 1 is characterized in that,

The sinusoidal wave form that possesses two sine waves that produce same frequency and phase phasic difference 90 degree.

3. power conversion unit according to claim 1 is characterized in that,

Said control operational part has phase compensation filter, and it implements to make the leading phase compensation filter computing of phase place to the output valve of said positive DFT arithmetical unit and the output valve of said anti-phase DFT arithmetical unit to the value after the moving average computing.

4. power conversion unit according to claim 3 is characterized in that,

Said phase compensation filter is made up of the first-order lead delay filter.

5. power conversion unit according to claim 3 is characterized in that,

Said phase compensation filter is made up of an incomplete differential.

6. power conversion unit according to claim 2 is characterized in that,

The sinusoidal wave frequency that said sinusoidal wave form is exported equates with the system frequency of binding.

7. power conversion unit according to claim 2 is characterized in that,

The sinusoidal wave frequency that said sinusoidal wave form is exported is the integral multiple of the system frequency of binding.

Images