CN101398794B - Bus logical gateway circuit of plurality of break request signals - Google Patents
Bus logical gateway circuit of plurality of break request signals Download PDFInfo
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- CN101398794B CN101398794B CN2007101624110A CN200710162411A CN101398794B CN 101398794 B CN101398794 B CN 101398794B CN 2007101624110 A CN2007101624110 A CN 2007101624110A CN 200710162411 A CN200710162411 A CN 200710162411A CN 101398794 B CN101398794 B CN 101398794B
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Abstract
The invention relates to a bus logical gateway circuit for a plurality of interruption request signals which comprises the following components: an output alternation gate which is provided with a plurality of input ends and an interruption request signal output end; a reverser which is provided with an input end and an output end; wherein, the input end is the interruption request signal output end connected to the output alternation gate; a plurality of gateway circuits used for leading the device end interruption request signals generated by a plurality of target devices to pass the gateway circuits or temporarily maintain in the gateway circuits. Each gateway circuit includes an AND gate and an alternation gate; according to the state of the output end of the AND gate and the interruption request signal output end of the output alternation gate, the alternation gate generates a gateway signal and transmits the signal to the gateway signal input end of the AND gate.
Description
Technical field
The invention relates to a kind of treatment circuit of interrupt request singal, particularly about a kind of bus interface treatment circuit of most interrupt request singals of computer system.
Background technology
In typical computer or digital systems architecture, mainly include nextport hardware component NextPorts such as central processing unit, disk set, input media, output unit, storer, these nextport hardware component NextPorts are the functions that reached binding and data transmission, control by bus.In bus specification now,, different bus specification of many kinds and type are arranged according to different system requirements and characteristics.
At first consult shown in Figure 1ly, it is to show that one includes the calcspar of the computer system or the digital display circuit of isa bus.In a typical computer, include a central processing unit 11, a storer 12, a PCI bridge 13 (PCI Bridge), at least one PCI device 14, a PCI/ISA bridge 15 (PCI/ISA Bridge), several ISA devices D1, D2 ... Dn.Central processing unit 11 is to be connected in system bus 21 with storer 12, and this system bus 21 connects a pci bus 22 (Peripheral Component Interconnect) by PCI bridge 13 again.Pci bus 22 is the bus specifications that proposed by PCISIG association, mainly is to can be used as the high-speed information forwarding function that cooperates in the microprocessing systems.Can be on this pci bus 22 for connecting various PCI devices 14 (for example interface devices such as interface card are gone in local networking interface card, presentation card, output).This pci bus 22 connects an isa bus 23 (Industry Standard Architecture) by PCI/ISA bridge 15, and this isa bus 23 can be for connecting various ISA device D1, D2 ... Dn.Each ISA device D1, D2 ... Dn (target device) can distinguish generation device end interrupt request singal D1_INT, D2_INT ... Dn_INT delivers to an interrupt request singal controller 16 and carries out the corresponding Interrupt Service Routine of this interrupt request singal (Interrupt Service Routine) via this isa bus 23.
The technical matters that institute of the present invention desire solves:
In the present isa bus standard criterion of formulating, isa bus has only the ISA device of supporting maximum 11 request interrupt request singals.If during more than 11 ISA devices that require interrupt request, the present practice is special software or driver to be installed handle this interrupt request singal in system.
For example, in the prior art, if in the time of will supporting overproof interrupt request singal, the device of part interrupt request must be shared the interrupt request singal end that logical circuit is connected to system by some, and system at first must load software special or that the client is specific earlier or driver comes the handling interrupt service routine.
In the prior art, when isa bus is detecting signal that device end sends interrupt request singal when rising edge, if the logical circuit in the employing prior art and do not have software that special/visitor orders or during driver, nearly all interrupt request singal will have the problem that leakage is handled, and the interrupt request input end of this isa bus will be lockable, because the status signal of its logical circuit will always present the accurate position of high state.
This known practice, not only in the problem that has the signal detection leakage aspect the processing of interrupt request singal, even each interrupt request singal of normal process, its processing speed is also slow.And when the system applies of reality, can increase the burden of computer system when the handling interrupt requests signal, also be unfavorable for the system development of dealer manufacturer.
Summary of the invention
Edge this, fundamental purpose of the present invention promptly provides a kind of treatment circuit that is used to handle a plurality of interrupt request singals, the present invention is the interrupt request singal that design receives and each device end of queue processing is sent with logical circuit, so that each device that sends interrupt request singal can both operate smoothly.
Another object of the present invention promptly provides the treatment circuit of a plurality of interrupt request singals of isa bus in a kind of computer system or the digital display circuit, in the hope of not installing or load software or driver special or that the client is specific, can handle the corresponding Interrupt Service Routine of this interrupt request singal smoothly.
The technological means that the present invention deals with problems:
The invention provides a kind of bus logic gateway circuit of a plurality of interrupt request singals, in order to the device end interrupt request singal that receives and a plurality of target devices that are connected in a computer system bus of queue processing are produced, it is characterized in that this bus logic gateway circuit includes:
One output or door have a plurality of input ends and an interrupt request singal output terminal;
A plurality of gateway circuits, be connected between the interrupt request singal output terminal and each target device of this output or door, also include a reverser in each gateway circuit, this reverser has an input end and an output terminal, wherein this input end is the interrupt request singal output terminal that is connected in this output or door, and output terminal is to be connected in this gateway circuit, in order to receive the device end interrupt request singal that this target device is produced, and according to the signal condition of the device end interrupt request singal of the signal condition of interrupt request singal output terminal of this output or door and this target device, and produce a gateway signal, deliver to this output or door or formation with the device end interrupt request singal that determines this target device to be produced in this gateway circuit by this gateway circuit.
Wherein this gateway circuit includes:
One with the door, have a device end interrupt request singal input end, a gateway signal input end and an output terminal, wherein this device end interrupt request singal input end is to be connected to a wherein target device, receiving the device end interrupt request singal that this target device is produced, and this output terminal is a wherein input end that is connected to this output or door;
One or the door, have a first input end, one second input end and an output terminal, wherein this first input end be connected to this with the door output terminal, this second input end is the output terminal that is connected in this reverser, this output terminal be connected to this with the door the gateway signal input end, should or door according to should with the state of the interrupt request singal output terminal of the output terminal of door and output or door, deliver to this and the gateway signal input end of door and produce a gateway signal.
Wherein have a replacement input end with door in this gateway circuit, be connected to a reset signal.
Wherein this bus is an isa bus.
The present invention contrasts the effect of prior art:
Can be under the situation of software of ordering without any need for special/visitor or driver via the technology used in the present invention means, can break through present computer system bus and be limited by and can support the interrupt request singal limited in number.
The interrupt request demand that the present invention comes the treating apparatus end to be sent with easy bus logic gateway circuit.When treatment circuit of the present invention is received more than more than one interrupt request singal, second later interrupt request singal can be given queue processing, and queuing system responds when unoccupied.The invention provides a kind of new interruption and share treatment circuit, and without any need for special software or driver.
When the present invention is applied to the isa bus of present computer system, when some/some interrupt request takes place, bus logic gateway circuit of the present invention will transmit first interrupt request singal and give isa bus, and makes other interrupt request singal formation remain in this logic gateway circuit.After the corresponding Interrupt Service Routine of this first interrupt request singal is finished, this logic gateway circuit can transmit next interrupt request singal and give isa bus, so makes the corresponding Interrupt Service Routine of interrupt request singal institute that each device end sent can be subjected to carrying out processing one by one in proper order.
Description of drawings
Specific embodiment of the present invention will be further described by following embodiment and accompanying drawing, wherein:
Fig. 1 shows that one includes the calcspar of the computer system or the digital display circuit of isa bus.
Fig. 2 shows device end interrupt request singal that bus logic gateway circuit of the present invention and several ISA devices are sent and the circuit connection diagram between isa bus.
Fig. 3 shows the further circuit diagram of bus logic gateway circuit of the present invention.
Fig. 4 is the waveform synoptic diagram that each device end interrupt request singal and sequence are carried out each interrupt request singal in the displayed map 3.
Embodiment
As shown in Figure 2, it shows device end interrupt request singal D1_INT, D2_INT, D3_INT that bus logic gateway circuit 100 of the present invention and several ISA devices are sent ... the circuit connection diagram that Dn_INT and isa bus are 23.Each device end interrupt request singal D1_INT, D2_INT, D3_INT ... Dn_INT delivers to isa bus 23 again through after the bus logic gateway circuit 100 of the present invention.
Consult shown in Figure 3ly, it is the further circuit diagram that shows bus logic gateway circuit 100 of the present invention.Fig. 4 is each device end interrupt request singal D1_INT, D2_INT, D3_INT in the displayed map 3 ... D8_INT3 and sequence are carried out the waveform synoptic diagram of each interrupt request singal.
Please consult Fig. 2-shown in Figure 4 simultaneously, include several gateway circuits 3a, 3b in the bus logic gateway circuit 100 of the present invention ... 3n.Device end interrupt request singal D1_INT, D2_INT, D3_INT that each target device is produced ... Dn_INT delivers to each gateway circuit 3a, the 3b of bus logic gateway circuit 100 respectively ... behind the 3n, again by each gateway circuit 3a, 3b ... 3n produces the logic signal input end 4a of logical signal to an output or door 4 respectively, and the interrupt request singal output terminal 4b by this output or door 4 sends an interrupt request singal INT1 to isa bus 23 again.
Be example now with first gateway circuit 3a, this gateway circuit 3a include one with the door 31 and one or the door 32, wherein have a device end interrupt request singal input end 31a with door 31, be connected to the device end interrupt request singal D1_INT that a target device is produced.Have a gateway signal input end 31b in addition with door 31, be connected to or door 32 output terminal 32c.
Or door 32 has a first input end 32a, is connected to the output terminal 31d with door 31.Or door 32 the second input end 32b is connected to the interrupt request singal output terminal 4b of output or door 4 via a reverser 5, will export or the state of the interrupt request singal INT1 that the interrupt request singal output terminal 4b of door 4 is sent is delivered to this or 32 the second input end 32b.According to this structure, make or door must be according to this state with the interrupt request singal output terminal 4b of the output terminal 31d of door 31 and output or door 4, deliver to this and the gateway signal input end 31b of door 31 and produce a gateway signal S1.
Each gateway circuit 3a, the 3b of bus logic gateway circuit 100 ... among the 3n each in addition can be provided with a replacement input end 31c with door 31, can be connected to a reset signal #RST jointly, with when the initialization operation, by this reset signal #RST reset each and door 31.
When each target device all not during generation device end interrupt request singal, each gateway circuit 3a, the 3b of bus logic gateway circuit 100 ... 3n and output terminal 31d door 31 all are the accurate position of low state current potential, so no interrupt request singal.
When one of them target device generation device end interrupt request singal (for example first target device D1 generation device end interrupt request singal D1_INT), the logical signal that gateway circuit 3a and output terminal 31d door 31 can send the accurate position of high state current potential is delivered to the input end 4a of output or door 4, so the interrupt request singal output terminal 4b of this output or door 4 can send the interrupt request singal INT1 of this target device generation to isa bus 23.
At this moment, because or the first input end 32a of door 32 is the accurate position of high state, though the second input end 32b is the accurate position of low state, or the output terminal 32c of door 32 still is the accurate position of high state, make with the output terminal 31d of door 31 can transition according to the accurate position of the device end interrupt request singal D1_INT of ISA device.But because or door 32 output terminal 32c be the accurate position of high state, so except the first gateway circuit 3a, other each gateway circuit 3b ... 3n is forbidden manufacture with Men Douhui.Even so the time have other ISA device to produce the device end interrupt request singal to its gateway circuit 3b ... among the 3n with door, but this gateway circuit 3b ... among the 3n and output terminal door still can't be exported the logical signal of the accurate position of high state to output or door 4.
Up to the Interrupt Service Routine of the device end interrupt request singal (for example D1_INT) of first ISA device processed intact after, the device end interrupt request singal (for example D2_INT) that just can make second ISA device is via delivering to isa bus 23 with door, output or door among the gateway circuit 3b.That is, the device end interrupt request singal D2_INT of second ISA device can by " maintenance " or " formation " in gateway circuit 3b with door, wait after the device end interrupt request singal D1_INT of first ISA device handles, the device end interrupt request singal D2_INT with this second ISA device sends to isa bus 23 via output or door 4 again.
Because isa bus 23 is reading interrupt request singal D1_INT, D2_INT, D3_INT ... during Dn_INT, be this interrupt request singal of detecting D1_INT, D2_INT, D3_INT ... the signal of Dn_INT rises edge (Rising Edge), so reading the device end interrupt request singal of this second ISA device, do not having the problem of leakage.
The oscillogram of each device end interrupt request singal as shown in Figure 4, for example as D1_INT, D2_INT, D3_INT ... when the interrupt request singal D4_INT among the Dn_INT8 is the accurate position of high state between time t1-t2 signal rises edge L1, bus logic gateway circuit 100 can be exported the accurate position of a high state in response to rising edge L1 in this signal by the interrupt request singal output terminal 4b of output or door 4 interrupt request singal INT1 carries out the corresponding Interrupt Service Routine of this interrupt request singal D4_INT by system again to isa bus.
This moment is when if the signal that interrupt request singal D6_INT is the accurate position of high state in time t2 rises edge L2, bus logic gateway circuit 100 can temporarily keep (formation) in this bus logic gateway circuit 100 this interrupt request singal D6_INT, after the corresponding Interrupt Service Routine of interrupt request singal D4_INT is finished (being that edge L3 falls in signal), just continuous this interrupt request singal D6_INT that carries out.Sequence executive mode according to this can be handled each interrupt request singal in regular turn and rise edge L4, L6 and signal falls edge L5, L7 and sequentially carries out each corresponding Interrupt Service Routine of interrupt request singal institute at the signal that different time t3-t5 produced.
By above embodiment as can be known, the value on the true tool industry of the bus logic gateway circuit of a plurality of interrupt request singals provided by the present invention was so the present invention had accorded with the condition of patent already.Only above narration only be preferred embodiment explanation of the present invention, allly is skillful in this operator when doing other all improvement according to above-mentioned explanation, only these change still belong to invention spirit of the present invention and below in the claim that defined.
Claims (4)
1. the bus logic gateway circuit of a plurality of interrupt request singals in order to the device end interrupt request singal that receives and a plurality of target devices that are connected in a computer system bus of queue processing are produced, is characterized in that this bus logic gateway circuit includes:
One output or door have a plurality of input ends and an interrupt request singal output terminal;
A plurality of gateway circuits, be connected between the interrupt request singal output terminal and each target device of this output or door, also include a reverser in each gateway circuit, this reverser has an input end and an output terminal, wherein this input end is the interrupt request singal output terminal that is connected in this output or door, and output terminal is connected in this gateway circuit, in order to receive the device end interrupt request singal that this target device is produced, and according to the signal condition of the device end interrupt request singal of the signal condition of interrupt request singal output terminal of this output or door and this target device, and produce a gateway signal, deliver to this output or door or formation with the device end interrupt request singal that determines this target device to be produced in this gateway circuit by this gateway circuit.
2. the bus logic gateway circuit of a plurality of interrupt request singals as claimed in claim 1 is characterized in that, wherein this gateway circuit includes:
One with the door, have a device end interrupt request singal input end, a gateway signal input end and an output terminal, wherein this device end interrupt request singal input end is to be connected to a wherein target device, receiving the device end interrupt request singal that this target device is produced, and this output terminal is a wherein input end that is connected to this output or door;
One or the door, have a first input end, one second input end and an output terminal, wherein this first input end be connected to this with the door output terminal, this second input end is the output terminal that is connected in this reverser, this output terminal be connected to this with the door the gateway signal input end, should or door according to should with the state of the interrupt request singal output terminal of the output terminal of door and output or door, deliver to this and the gateway signal input end of door and produce a gateway signal.
3. the bus logic gateway circuit of a plurality of interrupt request singals as claimed in claim 2 is characterized in that, wherein has a replacement input end with door in this gateway circuit, is connected to a reset signal.
4. the bus logic gateway circuit of a plurality of interrupt request singals as claimed in claim 1 is characterized in that, wherein this bus is an isa bus.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101624110A CN101398794B (en) | 2007-09-29 | 2007-09-29 | Bus logical gateway circuit of plurality of break request signals |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101624110A CN101398794B (en) | 2007-09-29 | 2007-09-29 | Bus logical gateway circuit of plurality of break request signals |
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| CN101398794A CN101398794A (en) | 2009-04-01 |
| CN101398794B true CN101398794B (en) | 2010-08-11 |
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Address after: China Taiwan Taipei City Neihu district road six section 13 of the civil rights No. 18 6 floor Patentee after: TrendOn Electronics Co., Ltd. Address before: Ai Road three Taipei City, Taiwan Chinese Daan District No. 136 14 floor Patentee before: TrendOn Electronics Co., Ltd. |