JP2002278920A - Device access system and electronic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit a CPU to efficiently access a plurality of peripheral devices. SOLUTION: In a device access system, the CPU 23 accesses a plurality of devices 26 connected to a data bus Bd and an address bus Ba. A plurality of input/output buffers 27 which can be set into a state where the signals of the respective bit lines of the data bus Bd are taken in, a state where the signals are outputted to the respective bit lines or a state where the signals are separated from the bit lines and an input/output controller 28 which independently controls the state of a plurality of the input/output buffers 27 in a bit unit in accordance with an address signal outputted from the CPU 23 to the address bus Ba are installed in each device 26. The data transmission direction of the data bus Bd can arbitrarily be set in the bit unit by the address signal outputted from the CPU 23 to the address bus Ba.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a technique for a CPU to efficiently access a plurality of peripheral devices.

[0002]

2. Description of the Related Art For example, in electronic equipment such as a measuring device and a communication device, control of a plurality of devices (units) related to the measurement and communication is performed by a microcomputer including a CPU, a ROM, a RAM, and the like.

FIG. 8 shows a CP in such an electronic device.
From U1, a plurality of n devices 10 ₀ , 10 ₁ ,..., 10
₃ shows a configuration for accessing _n-1 .

[0004] Here, the data bus Bd of k bits of CPU1 is connected in parallel to each device ₁₀ 0 _{to 10 n-1,} of the address bus Ba m bits of CPU1, h bits of upper devices It is connected to the selection circuit 15.

[0005] Device selection circuit 15, the device 10 ₀
10 of _n-1, and outputs a selection signal Cs to the device 10 _i which is determined by the upper h-bit data value i of the address signal A.

Further, the CPU 1 controls the control bus Bc.
0 Each device ₁₀ a read-write signal R / W through -
Output to 10 _n-1 .

[0007] Each device ₁₀ 0 _{~10 n-1,} the data bus each bit line b (0) of Bd ~b (k-1) output buffer ₁₁ connected respectively to the 0 (0) to 11
₀ (k-1), 11 ₁ (0) to 11 ₁ (k-1), ...
, 11 _n-1 (0) to 11 _{n -1} (k-1) are provided.

[0008] Each device ₁₀ 0 _{~10 n-1,} the presence or absence of the selection signal Cs from the device selection circuit 15, in accordance with the state of the read-write signal R / W which is input through the control bus Bc, corresponding All the input / output buffers to be loaded with data from the data bus Bd (I
N), a state of outputting data to the data bus Bd (OU
T), output controller ₁₂ 0 _{~12 n-1} to be set in one of the data bus Bd high impedance state disconnected from (Z), respectively.

[0009] In the electronic apparatus having the above configuration, for example, when notifying the data D parameters necessary for measurement and communication from CPU1 to the device 10 _0, CPU
From 1 to the address bus Ba, an address signal A for which the data value i of the high-order p bits becomes 0 is output, a data signal D is output to the data bus Bd, and the read / write signal R / W is in a write state. To

[0010] Device selection circuit 15 where the data values i receives a signal of p bits of 0, and outputs a selection signal Cs with respect to device 10 _0.

[0011] The device 10 ₀ which has received the selection signal Cs
Input / output controller ₁₂₀ of read / write signal R /
W is confirmed to be write state, the corresponding all input and output buffers ₁₁ to 0 (0) _{to 11} sets 0 to (k-1) to the data acquisition state (IN) state.

[0012] Furthermore, the input-output controller 12 ₁ of the other device ₁₀ 1 _{to 10 n-1} not receiving the selection signal Cs
-12n _-1 are all the corresponding input / output buffers 11 _{1
(0) ~11 1 (k-} 1), 11 2 (0) ~11 2 (k
−1),..., 11 _n−1 (0) to 11 _n−1 (k−
1) is set to a high impedance state (Z).

Thus, the other devices 10 ₁ to 10 _1
n-1 is disconnected from the data bus Bd,
Data signal D output from CPU 1 to data bus Bd
There is incorporated into the device 10 _0.

[0014] Incidentally, when the read write signal R / W to the read state, the device 10 ₀ output controller 12
There, all of the input and output buffer _{11 0 (0) ~11 0 (} k-
1) Set the data output state (OUT) state, it is possible to notify the data of the device 10 in the ₀ to CPU 1.

[0015]

However, as described above, one of the devices is selected by the address signal,
In the conventional device access method for exchanging data,
Even if the same type of control is performed for a plurality of devices, data must be exchanged by sequentially accessing each device one by one with an address signal. there were.

An object of the present invention is to solve the above problem and to provide a device access system and an electronic apparatus which can efficiently access a plurality of devices.

[0017]

According to a first aspect of the present invention, there is provided a device access system for accessing a plurality of devices connected to a data bus and an address bus from a CPU according to the present invention. A plurality of input / output buffers respectively connected to each bit line of the data bus and capable of being set to a state of taking in a signal of the bit line, a state of outputting a signal to the bit line, or a state of disconnecting the bit line And an input / output controller that independently controls the state of the plurality of input / output buffers in bit units in accordance with an address signal output from the CPU to the address bus. The data transmission direction of the data bus depends on the address signal output to the bus. It is to be set arbitrarily in bits.

Further, the electronic device according to claim 2 of the present invention has a C
In an electronic apparatus including a control unit including a PU and a plurality of devices commonly connected to a data bus and an address bus of the CPU of the control unit and performing signal processing, each device includes the data A plurality of input / output buffers respectively connected to each bit line of the bus and capable of being set to any of a state for taking in a signal of the bit line, a state for outputting a signal to the bit line, and a state in which the bit line is disconnected; And an input / output controller that independently controls the state of the plurality of input / output buffers on a bit-by-bit basis in accordance with an address signal output from the CPU to the address bus. The data transmission direction of the data bus can be arbitrarily set in bit units by the address signal output to It has to so that.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a measuring device 20 to which the present invention is applied.

[0020] In FIG. 1, the measuring apparatus 20, operation unit 21, the control unit 22, a plurality of devices ₂₆ 0-26
_n-1 , a storage device 30, a display 31, a printer 32, and the like.

The operation unit 21 is for inputting information for determining the operation mode of the measuring device 20 and its operating conditions and the like, and is constituted by key switches, rotary knobs and the like.

The control unit 22 includes a CPU 23, a ROM 24,
A plurality of n devices 26 ₀ to 26
Control for _n-1 is performed.

The storage device 30 is a floppy (registered trademark).
A disk drive, a hard disk drive, a memory card reader, and the like read and write information such as measurement conditions and measurement results to a floppy disk, a hard disk, a memory card, and the like.

The display 31 displays, for example, measurement conditions and measurement results in a liquid crystal type, and the printer 32 prints out the measurement conditions and measurement results in the same manner as the display 31.

On the other hand, each device ₂₆ 0 _{~26 n-1} is
Measuring unit and the operation unit 21 of the measuring device 20, storage device 30, a display unit 31, which constitutes the interface or controller of the printer 32, for example, the device 26 _0, storage device 30 controller, device 26
₁ includes an operation unit 21, display 31 and interface of the printer 32, another device ₂₆ 2 _{~ 26 n-1} is a unit constituting the measuring unit.

[0026] Each of these devices ₂₆ 0-26
_n-1 is constituted by, for example, an FPGA (field programmable gate array), and is connected in parallel to the k-bit data bus Bd and the m-bit address bus Ba of the CPU 23.

Further, each device ₂₆ 0 _{~26 n-1,} each bit line b (0) of the data bus Bd ~b (k
-1) k three-state type input / output buffers 27 ₀ (0) to 27 ₀ (k−1), 27 respectively connected to
₁ (0) to 27 ₁ (k-1), ..., 27 _n-1 (0)
To 27 _n-1 (k-1).

Further, each device ₂₆ 0 _{~26 n-1,} the corresponding output buffer _{27 0 (0) ~27 0 (} k
-1), 27 ₁ (0) to 27 ₁ (k-1), ..., 27
_{n-1 (0) ~27 n} -1 (k-1) output controller 28 for controlling the state of the independently each bitwise ₀
~ 28 _n-1 are provided.

[0029] Each input and output controller ₂₈ 0 _{~28 n-1}
Stores in advance a bit input / output pattern for the address signal A and the read / write signal R / W,
According to the bit input / output pattern corresponding to the address signal A and the read / write signal R / W output from
The state of the input / output buffers 27 _X (0) to 27 _X (k−1) is controlled in bit units.

As described above, each of the devices 26 ₁ to 26 26
_n-1 input / output controllers 28 _{1 to} 28 _n-1
In accordance with the address signal A from the PU23, since the state of the corresponding output buffer _{27 X (0) ~27 X (} k-1) is adapted to be controlled independently of the bits, for example, the common Any of a plurality of devices can be accessed or data can be transferred between the plurality of devices by using the address signal A.

Next, when the number n of devices is 16, and the data signal D
Is 16 and the number m of bits of the address signal A is 1.
An access example in the case of No. 6 will be described.

For example, as shown in FIG.
The upper six bits of the address signal A, a (15), a (14),
.., A (10) is in the range of all 0, the device 26₁~
26 _n-1R0M24 or RAM25 other than
You. At this time, each input / output controller 28₁~ 28
_n-1Are all devices as shown in FIG.
26 ₀~ 26_n-1Input / output buffer 27₀(0) -2
7₀(15), 27₁(0) -27₁(15), ...,
27_n-1(0) -27_n-1The state of (15) is high
Impedance state (Z).

As shown in FIG. 3A, the upper two bits a (15) and a (14) of the address signal A are 0, and at least the following four bits a (13) to a (10) When one is 1, the four bits a (13) to a (1)
0) read / write all the input / output buffers 27 _x (0) to 27 _x (15) corresponding to only the input / output controller 28 _x of the device 26 _x specified by the value x (x = 9 in this example). The input / output controller is set to a state corresponding to the signal R / W, and the other input / output controllers 28 _{0 to} 28 _x−1 and 28 _{x + 1} to 2
8 _n-1 brings the corresponding input / output buffer into the high impedance state Z.

For example, when the read / write signal R / W indicates the write state W, as shown in FIG.
I / O controller 28 _X is I / O buffer 27
_{When all of x} (0) to 27 _x (15) are in the IN state and the read state R is indicated, as shown in FIG.
Input / output buffers 27 _x (0) to 27 _x (15) are all O
Set to UT state.

In this state, the CPU 23 and the address signal A
In is for transmitting and receiving 16-bit data with a single device 26 _x specified, is equivalent to the conventional access mode.

As shown in FIG. 4A, of the upper two bits a (15) and a (14) of the address signal A, a
(15) is 0, a (14) is 1 and the other 4 bits a (1
When 3) to a (10) are all 0, all of the input / output controllers 28 _{0 to} 28 _n-1 output the address signal A to C
Initialization request and interpreted from PU23, as shown in (b) of FIG. 4, ₀ the first input-output controller 28, output buffer ₂₇ of the first bit 0 (0) only the IN state, the other output buffer ₂₇ 0 (1) _{to 27} 0 (15) to the high impedance state Z, 2-th output controller 28 _2, the second bit of the output buffer 27
₁ Only (1) is in the IN state, other input / output buffers 27
₁ (0), 27 ₁ (2) to 27 _i (15) are set to the high impedance state Z, so that the input / output buffers 27 are provided one by one so as not to overlap each other for each device.
To the IN state.

In such a state, the first bit d (0) and the third bit d (0) are output from the CPU 23, for example, as shown in FIG.
When the bit d (2), the tenth bit d (9), and the sixteenth bit d (15) are 1 and a data signal D whose other bits are 0 is output, the device 2 receiving the 1 data
6 _{0, 26 2,} 26 9, _{26 15} initializes the internal.

As shown in FIG. 5A, among the upper two bits a (15) and a (14) of the address signal A, a (15) is 0, a (14) is 1 and the other 4 bits a (1
When all of 3) to a (10) are 1, all of the input / output controllers 28 _{0 to} 28 _{n− 1} output the address signal A.
Is interpreted as an activation request from the CPU 23, and similarly, as shown in FIG. 5B, the input / output buffers 27 are set to the IN state one by one so as not to overlap each other for each device.

In this state, the CPU 23 outputs the second bit d (1) and the fifth bit d (1) as shown in FIG.
When the data signal D whose bit d (4), the eighth bit d (7) and the twelfth bit d (11) are 1 and the other bits are 0 is output, the device 26 ₁ receiving the 1 data,
26 ₄ , 26 ₇ , 26 ₁₁ are activated.

As shown in FIG. 6A, when a (15) of the upper two bits a (15) and a (14) of the address signal A is 1 and a (14) is 0, Means that all of the input / output controllers 28 _{0 to} 28 _n-1 have values p (p in this example) of the following four bits a (13) to a (10).
= 3) to the device 26 _q specified by the value q of 4 bits a (9) to a (6) bits (q = 5 in this example) following the device 26 _p specified by 16 bits data interprets transfer request to transfer, as shown in (b) of FIG. 6, the input-output controller 28 _p all its input and output buffers ₂₇ p (0) of the device 26 _p specified in the transfer source ~ 27 _p (15) is set to the output state, and the input / output controller 28 _q of the device 26 _q designated as the transfer destination sets all the input / output buffers 27 _q (0) to 27
Set _q (15) to the input state.

As shown in FIG. 7A, the upper two bits a (15) and a (14) of the address signal A are both 1, and the following four bits a (13) to a (10) 7), the input / output controller 27 sets the input / output buffer 27 to the OUT state one by one so that the input / output controllers 28 do not overlap with each other, as shown in FIG. The other input / output buffers are set to the high impedance state Z.

[0042] In this state, each device ₂₆ 0-26
_n-1 is a state of outputting the data bit by bit to the data bus Bd, CPU 23 can know the status of each device ₂₆ 0 _{~ 26 n-1} from each bit of the data signal D.

[0043] Similarly, each device ₂₆ 0-26
_n-1 input / output controllers 28 _{0 to} 28 _n-1
According to the bit input / output pattern corresponding to the address signal A from the PU 23, each input / output buffer is controlled in bit units, and data is transmitted and received in bit units between arbitrary devices connected to the data bus Bd.

Although the above-described bit input / output pattern is a relatively simple example of transmitting and receiving data in a one-to-one or one-to-many manner, as described above, each input / output controller has Can control the state of the input / output buffer on a bit-by-bit basis. For example, it is possible to perform complicated control such as sending and receiving data between two devices while the CPU 23 sends data to two devices. Can be done with

As described above, in the measuring device 20 of the embodiment,
Each device ₂₆ 0 _{~26 n-1,} CPU of the control unit 22
Since input / output controllers 28 _{0 to} 28 _n−1 that can independently control an input / output buffer connected to the data bus Bd in units of bits in accordance with the address signal A from the CPU 23 are provided, and between the device ₂₆ 0 _{~ 26 n-1,} the plurality of devices ₂₆ 0 -
Between 26 _n−1 , data can be transmitted on the data bus Bd with an arbitrary number of bits in an arbitrary direction.

Therefore, as described above, even when performing common processing for each device such as initialization, activation, status monitoring, etc., the common address signal A from the CPU 23 is used.
, And quick control is possible.

Although the measuring device 20 has been described here, the present invention can be similarly applied to other electronic devices such as a communication device.

[0048]

As described above, according to the first aspect of the present invention,
A device access system for accessing a plurality of devices connected to a data bus and an address bus from a CPU, wherein each of the devices is connected to each bit line of the data bus; And a plurality of input / output buffers that can be set to any of a state in which a signal is taken in, a state in which a signal is output to the bit line, and a state in which the bit line is disconnected, and an address signal output from the CPU to the address bus. And an input / output controller that independently controls the states of the plurality of input / output buffers in bit units in accordance with
The data transmission direction of the data bus can be arbitrarily set in bit units by an address signal output from the U to the address bus.

For this reason, a common address signal causes the CPU
Data can be exchanged between a plurality of devices and data can be exchanged between a plurality of devices, and access processing to a plurality of devices can be performed extremely quickly.

Further, the electronic device according to the second aspect of the present invention has a C
In a measuring apparatus including a control unit including a PU and a plurality of devices commonly connected to a data bus and an address bus of the CPU of the control unit and performing signal processing, each device includes the data A plurality of input / output buffers respectively connected to each bit line of the bus and capable of being set to any of a state for taking in a signal of the bit line, a state for outputting a signal to the bit line, and a state in which the bit line is disconnected; And an input / output controller that independently controls the state of the plurality of input / output buffers on a bit-by-bit basis in accordance with an address signal output from the CPU to the address bus. The data transmission direction of the data bus can be arbitrarily set in bit units by the address signal output to It has to so that.

For this reason, a common address signal causes the CPU
Can exchange data with a plurality of arbitrary devices, and exchange data between a plurality of devices, and can perform the same kind of control processing on a plurality of devices extremely quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of a main part of the embodiment.

FIG. 3 is a diagram illustrating an operation of a main part of the embodiment.

FIG. 4 is a diagram illustrating an operation of a main part of the embodiment.

FIG. 5 is a diagram illustrating an operation of a main part of the embodiment.

FIG. 6 is a diagram illustrating an operation of a main part of the embodiment.

FIG. 7 is a diagram for explaining an operation of a main part of the embodiment.

FIG. 8 is a diagram showing a configuration of a conventional system.

[Explanation of symbols]

20 measuring device 21 operation unit 22 control unit _{23 CPU 24 ROM 25 RAM 26 0} ~26 n-1 devices _{27 0 (0) ~27 n-} 1 (k) output buffer 28 ₀ ~28 _n-1 output controller 30 Storage device 31 Display device 32 Printer

Claims (2)

[Claims] 1. A device access system for accessing a plurality of devices connected to a data bus and an address bus from a CPU, wherein each of the devices is connected to each bit line of the data bus.
A plurality of input / output buffers that can be set to any of a state of capturing a signal of the bit line, a state of outputting a signal to the bit line, and a state of disconnection of the bit line; and a plurality of input / output buffers output from the CPU to the address bus. And an input / output controller that independently controls the states of the plurality of input / output buffers in units of bits in accordance with the address signals provided by the CPU. A device access system wherein a data transmission direction of a bus can be arbitrarily set in bit units. 2. An electronic apparatus comprising: a control unit including a CPU; and a plurality of devices commonly connected to a data bus and an address bus of the CPU of the control unit for performing signal processing. Is connected to each bit line of the data bus,
A plurality of input / output buffers that can be set to any of a state of capturing a signal of the bit line, a state of outputting a signal to the bit line, and a state of disconnection of the bit line; and a plurality of input / output buffers output from the CPU to the address bus. And an input / output controller that independently controls the states of the plurality of input / output buffers in units of bits in accordance with the address signals provided by the CPU. An electronic device wherein a data transmission direction of a bus can be arbitrarily set in bit units.