CN101393861A - Gate dielectric layer forming method - Google Patents
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- CN101393861A CN101393861A CNA2007100463107A CN200710046310A CN101393861A CN 101393861 A CN101393861 A CN 101393861A CN A2007100463107 A CNA2007100463107 A CN A2007100463107A CN 200710046310 A CN200710046310 A CN 200710046310A CN 101393861 A CN101393861 A CN 101393861A
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Abstract
The invention discloses a method used for forming a grid dielectric layer. The method comprises the steps as follows: forming a silica layer on a substrate; carrying out plasma nitrogenization treatment for the silica layer; carrying out first thermal annealing treatment for the substrate in the nitrogen environment; and carrying out second thermal annealing treatment for the substrate in the oxygen environment. The method for forming the grid dielectric layer is adopted to increase the concentration of nitrogen present in the surface layer of silica. Moreover, the method can ensure that the concentration of nitrogen present in the surface layer of silica can meet the requirement in spite of a device with a relatively low power or a short-lived plasma treatment, thereby preventing the substrate from damages due to the plasma nitrogenization, and enhancing the performance of the device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of gate dielectric layer.
Background technology
Along with the fast development of integrated circuit technology, it is more and more littler that device size becomes, and the thickness of gate oxide is also more and more thinner, when device dimensions shrink to 90nm, according to the scaled down principle, conventional gate oxide (SiO
2) will be as thin as 10
To 20
About, at this moment, the tunnel(l)ing current that passes gate dielectric layer will sharply increase, and the quiescent dissipation of circuit is greatly increased.In addition, what the grid material of PMOS device adopted is boron doped method, its penetrating in the gate oxide of attenuate day by day becomes more and more easier, can cause device function to be degenerated, consequences such as negative bias thermal instability (NBTI, Negative Bias Temperature Instability) is relatively poor, device reliability and life-span reduction.In addition, for this gate oxide as thin as a wafer, the manufacturing process that control it exactly is with the process results of the satisfaction that reaches also difficulty comparatively.
For overcoming the problems referred to above, a kind of new gate dielectric layer structure has been proposed in the Chinese patent application that on October 27th, 2004, disclosed publication number was CN1540769A, it has adopted sandwich structure: elder generation is at the silicon oxynitride layer of surface of silicon growth thin layer, growth one deck high dielectric constant material layer on this silicon oxynitride layer again, at last, on this high dielectric constant material, covered one deck silicon nitride layer again.After adopting this structure as gate dielectric layer, having improved the single silicon oxide layer of above-mentioned employing to a certain extent is the problem of gate dielectric layer, but this method implements comparatively complexity, increased the extra operation of multistep, in addition, because the thickness of each layer is all thinner, its technology controlling and process is also relatively poor.
At present, commonly used is a kind of method that will mix the silicon oxide layer of nitrogen as gate dielectric layer, this silicon oxide layer that mixes nitrogen have relative higher dielectric constant, effectively boron diffusion barrier functionality (can improve the negative bias thermal instability of PMOS device) and with advantage such as conventional cmos technological process compatibility.Wherein, the increase of gate dielectric layer dielectric constant means with pure gate oxide and compares that it can use thicker dielectric layer, thereby can reduce the leakage current of grid, and improves the accuracy to the gate dielectric layer technology controlling and process.Notice, employing is mixed the silicon oxide layer of nitrogen as gate dielectric layer, importantly to make nitrogen be distributed in the top layer of silicon oxide layer than the concentrated area, this can play effective barrier effect to boron penetration on the one hand, also can between silicon substrate and gate oxide, keep interface state preferably on the other hand, can not have influence on the mobility of channel carrier, make the leakage current of grid that significant reduction is arranged.
Fig. 1 is the flow chart of the formation method of existing gate dielectric layer, introduces at present formation method as the silicon oxide film that mixes nitrogen of gate dielectric layer below in conjunction with Fig. 1.
At first, on silicon substrate, utilize thermal oxidation method (RTO, Rapid Thermal Oxidation) or original position steam to produce the silicon oxide layer (S101) that method (ISSG, In-suit Stream Generation) forms thin layer.The thickness of this silicon oxide layer is determined by concrete device.
Then, utilize nitrogen plasma that silicon oxide layer is carried out nitrogen treatment (S102).Formed the plasma of nitrogen in this step, nitrogen has been incorporated into the surface of silicon oxide layer.Uniformity and controllability that the nitriding method of this kind plasma can make nitrogen distribute in sheet are all better.
Then, carry out annealing in process (S103) after the nitrogenize.Annealing in process (PNA after the nitrogenize of this step, Post Nitridation Anneal) in, fed nitrogen and oxygen simultaneously substrate has been carried out annealing in process, nitrogen in first can stable silicon oxide layer, second can the interface between silica and silicon substrate be reoxidized, repair interfacial state, reduce defective.
Adopt the formation method of existing gate dielectric layer; can form the nitrogen of higher concentration on the surface of silicon oxide layer; but; for the surface energy that makes silicon oxide layer has certain density nitrogen; power required in the pecvd nitride step higher (usually can several hectowatts in addition on kilowatt) or required processing time longer; this can cause to a certain degree damage to substrate, and is unfavorable to the further raising of device performance.
Summary of the invention
The invention provides a kind of formation method of gate dielectric layer, further improved the distribution situation of nitrogen in silicon oxide layer, alleviated because of silicon oxide layer being carried out the damage that plasma nitridation process causes to device.
The formation method of a kind of gate dielectric layer provided by the invention comprises step:
On substrate, form silicon oxide layer;
Described silicon oxide layer is carried out plasma nitridation process;
Under nitrogen atmosphere, described substrate is carried out first thermal anneal process;
Under oxygen-containing atmosphere, described substrate is carried out second thermal anneal process.
Wherein, the power of described plasma nitridation process is between 100 to 2000W, and the time of described plasma nitridation process is between 10 to 60 seconds.
Wherein, described nitrogen atmosphere refers to that nitrogen content accounts for more than 95%.
Wherein, described oxygen-containing atmosphere is made of jointly oxygen and nitrogen.Preferably, oxygen content accounts for 5% to 50% in the described oxygen-containing atmosphere.
Wherein, the temperature of described first thermal anneal process is between 1000 to 1100 ℃, and the chamber pressure of described first thermal anneal process is between 1 to 30Torr, and the time of described first thermal anneal process is between 20 to 60 seconds.
Wherein, the temperature of described second thermal anneal process is between 1000 to 1100 ℃, and the chamber pressure of described second thermal anneal process is between 1 to 50Torr, and the time of described second thermal anneal process is between 20 to 90 seconds.
Wherein, described formation silicon oxide layer comprises and utilizes thermal oxidation method to form silicon oxide layer or utilize original position steam generation method to form silicon oxide layer that the thickness of described silicon oxide layer is 10 to 20
Between.
The present invention has the formation method of the another kind of gate dielectric layer of identical or relevant art feature, comprises step:
On substrate, form silicon oxide layer;
Definite nitrogen concentration that need in described silicon oxide layer, form;
The situation of first thermal anneal process that will carry out according to described nitrogen concentration and back is determined the process conditions of the pecvd nitride that will carry out;
According to described process conditions to described silicon oxide layer is carried out plasma nitridation process;
Under nitrogen atmosphere, described substrate is carried out first thermal anneal process;
Under oxygen-containing atmosphere, described substrate is carried out second thermal anneal process.
Wherein, the process conditions of described plasma nitridation process comprise power and time at least, and described power is between 100 to 1500W, and the described time is between 10 to 30 seconds.
Wherein, described nitrogen atmosphere refers to that nitrogen content accounts for more than 95%.
Wherein, described oxygen-containing atmosphere is made of jointly oxygen and nitrogen, and preferably, oxygen content accounts for 5% to 50% in the described oxygen-containing atmosphere.
Wherein, the temperature of described first thermal anneal process is between 1000 to 1100 ℃, and the chamber pressure of described first thermal anneal process is between 1 to 30Torr, and the time of described first thermal anneal process is between 20 to 60 seconds.
Wherein, the temperature of described second thermal anneal process is between 1000 to 1100 ℃, and the chamber pressure of described second thermal anneal process is between 1 to 50Torr, and the time of described second thermal anneal process is between 20 to 90 seconds.
Wherein, described formation silicon oxide layer comprises and utilizes thermal oxidation method to form silicon oxide layer or utilize original position steam generation method to form silicon oxide layer that the thickness of described silicon oxide layer is 10 to 20
Between.
Wherein, the situation of first thermal anneal process that will carry out according to described nitrogen concentration and back is determined the process conditions of the pecvd nitride that will carry out, and comprises step:
Process conditions according to the definite pecvd nitride that will carry out of described nitrogen concentration;
The situation of first thermal anneal process that will carry out according to the back is adjusted described process conditions.
Compared with prior art, the present invention has the following advantages:
The formation method of gate dielectric layer of the present invention, by the thermal anneal process after plasma nitrided is divided under the nitrogen atmosphere and oxygenous atmosphere under two steps carry out, further improved the distribution situation of nitrogen in silicon oxide layer, can be under the condition that adopts lower-wattage or the plasma treatment of short period, the surface that is implemented in oxide layer reaches the nitrogen concentration that meets the demands, reduced because of plasma nitridation process to the damage that device brings, improved device performance.
Description of drawings
Fig. 1 is the flow chart of the formation method of existing gate dielectric layer;
Fig. 2 is the flow chart of first embodiment of gate dielectric layer formation method of the present invention;
Fig. 3 is the device profile map that forms among first embodiment of gate dielectric layer formation method of the present invention behind the silicon oxide layer;
Fig. 4 is for carrying out the device profile map after the plasma nitridation process among first embodiment of gate dielectric layer formation method of the present invention;
Fig. 5 is for carrying out the device profile map after first thermal anneal process among first embodiment of gate dielectric layer formation method of the present invention;
Fig. 6 is for carrying out the device profile map after second thermal anneal process among first embodiment of gate dielectric layer formation method of the present invention;
Fig. 7 is for adopting the NBTI characteristic schematic diagram of the preceding device of formation method of the present invention;
Fig. 8 is the NBTI characteristic schematic diagram of the device after the employing formation method of the present invention;
Fig. 9 is the flow chart of second embodiment of gate dielectric layer formation method of the present invention;
Figure 10 is the comparison schematic diagram of the nitrogen concentration in the silica top layer of adopting formation method of the present invention front and back.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Processing method of the present invention can be widely used in the every field; and can utilize many suitable material; be to be illustrated below by specific embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
Form in the process of gate dielectric layer, in order to obtain relative higher dielectric constant and to realize effective boron diffusion barrier functionality, often need in silicon oxide layer, form the silicon oxide layer of nitrogenize with certain nitrogen concentration, and wish that the distribution of this nitrogen concentration in silicon oxide layer concentrates in the top layer of silica more, it helps the raising of device performance.In addition, to the nitrogen treatment of silicon oxide layer, normally utilize plasma bombardment to realize, this can cause certain damage to substrate, and is unfavorable to the further raising of device performance.In order to alleviate the damage that plasma nitridation process ionic medium body causes substrate, also wish under the prerequisite that the nitrogen concentration in guaranteeing the silica top layer meets the demands, reduce the power of plasma or shorten processing time of plasma.
For this reason, the present invention proposes a kind of formation method of new gate dielectric layer, the thermal anneal process condition of carrying out after the nitrogenize of article on plasma body is improved, change a traditional step annealing method into the double annealing method, in the silica top layer, to realize higher nitrogen concentration (improving the distribution situation of nitrogen in silicon oxide layer in other words).In addition, the formation method of gate dielectric layer of the present invention can also nitrogen concentration meets the demands in guaranteeing the silica top layer in, reduce the power of plasma treatment or reduce time of plasma treatment, reach the purpose that reduces plasma damage.
Fig. 2 is the flow chart of first embodiment of gate dielectric layer formation method of the present invention, Fig. 3 to Fig. 6 describes in detail to first embodiment of gate dielectric layer formation method of the present invention below in conjunction with Fig. 2 to Fig. 6 for the device profile schematic diagram of first embodiment of explanation gate dielectric layer formation method of the present invention.
At first, on substrate, form silicon oxide layer (S201).In this step, on silicon substrate, utilize thermal oxidation method (RTO, Rapid Thermal Oxidation) or original position steam to produce the silicon oxide layer that method (ISSG, In-suit Stream Generation) forms thin layer.Wherein, preceding a kind of method is to utilize oxidation furnace or rapid thermal annealing chamber, under oxygen atmosphere substrate is carried out 600 to 900 ℃ thermal oxidation and realizes; The back is a kind of to be in the rapid thermal annealing chamber, feeds hydrogen and oxygen, is combined to water vapour in the silicon face original position of heat, closes the process that forms silica with silication again.No matter adopt which kind of method, the thickness of the silicon oxide layer that forms in this step all is arranged on 10 usually
To 20
About.
Fig. 3 is the device profile map that forms among first embodiment of gate dielectric layer formation method of the present invention behind the silicon oxide layer, as shown in Figure 3, has formed the silicon oxide layer 302 of thin layer on silicon substrate 301.
Then, described silicon oxide layer is carried out plasma nitridation process (S202).In the present embodiment, employing be the coupling pecvd nitride method (DPN, Decoupled Plasma Nitridation) of taking off, it adopts inductive couplings to produce nitrogen plasma, and high state nitrogen (high level ofnitrogen) is incorporated into silicon oxide layer.In the plasma bombardment process, nitrogen plasma is broken SiO
2Film makes nitrogen ion/bioactive molecule and SiO2 film bonding, forms silicon oxynitride film.
Fig. 4 is for carrying out the device profile map after the plasma nitridation process among first embodiment of gate dielectric layer formation method of the present invention, as shown in Figure 4, through after the plasma nitridation process, in the surface combination of silicon oxide layer 302 a large amount of nitrogen 303, formed silicon oxynitride layer.But the bombardment processing meeting of the plasma in this step causes certain damage in substrate, as among the figure 304 be shown in silicon substrate 301 and 302 of silicon oxide layers have formed some defectives, caused certain interfacial state, this is unfavorable to device performance.
In the present embodiment, the process conditions of this step pecvd nitride can be set to: chamber pressure as is 50mTorr between 10 to 100mTorr; Power is between 100 to 2000W, as is 900W; The time of plasma bombardment is 10 to 60 seconds, as is 20 seconds; The gas that feeds can only be nitrogen, also can be the mist of nitrogen and inert gas, as be the mist of nitrogen and helium or nitrogen and argon gas, and the total flow of feeding gas as is 200sccm between 100 to 400sccm.
After carrying out plasma nitridation process, under nitrogen atmosphere, substrate is carried out first thermal anneal process (S203).In the present embodiment, this step thermal annealing is to carry out in rapid thermal anneler, and used temperature can be between 1000 to 1100 ℃, and the pressure in the stove can be between 1 to 30Torr, and the time of processing as was 30 seconds between 20 to 60 seconds.
Wherein, the nitrogen atmosphere in the present embodiment is meant that nitrogen content accounts for major part, as, nitrogen and 5% other following gases more than 95% can be arranged, as oxygen.Under this kind nitrogen atmosphere, compare with a traditional step annealing method: first, the probability that the interior nitrogen that exists of plasma nitridation process rear oxidation silicon layer is moved to the top layer increases, combination rate in the top layer between nitrogen and the silicon also increases thereupon, can in the top layer of silicon oxide layer, form more nitrogen compound, improved the distribution of nitrogen concentration, made the more densification of silicon oxynitride that forms in the top layer; Second, the nitrogen of the free state of squeezing in the plasma nitridation process process diminishes to silicon substrate 301 and the probability that silicon oxide layer 302 interface places move, and can reduce the interfacial state of the two.
Fig. 5 is for carrying out the device profile map after first thermal anneal process among first embodiment of gate dielectric layer formation method of the present invention, as shown in Figure 5, for above-mentioned reasons, after first thermal anneal process, formed the higher silicon oxynitride layer of fine and close nitrogen concentration 310 on silicon oxide layer 302 surfaces, simultaneously, also tailed off at silicon substrate 301 and 302 interfacial states 304 that cause because of plasma nitridation process of silicon oxide layer.
Follow again, under oxygen-containing atmosphere, described substrate is carried out second thermal anneal process (S204).In the present embodiment, this step thermal annealing is still in rapid thermal anneler and carries out, and used temperature can be between 1000 to 1100 ℃, and the pressure in the stove can be between 1 to 50Torr, and the time of processing is between 20 to 90 seconds, as 60 seconds.
Wherein, the oxygen-containing atmosphere in the present embodiment is meant in the gas of feeding and contains oxygen, as, can contain the oxygen about 5% to 50%, and remainder can not participate in the gas composition of reacting by other, as other inert gases such as nitrogen, helium, argon gas.The effect of this second thermal anneal process, suitable with the effect of a traditional step annealing method: this step thermal annealing can make the oxidized again part of surface of silicon on the one hand, make the interfacial state of original appearance defective upwards slightly mobile, form new interfacial state with less defective; This step thermal annealing can reduce the number of defects (not shown) in the whole oxide layer on the other hand.
Fig. 6 is for carrying out the device profile map after second thermal anneal process among first embodiment of gate dielectric layer formation method of the present invention, as shown in Figure 6, after second thermal anneal process, silicon oxide layer 302 further expands in silicon substrate 301, itself and 301 of silicon substrates have formed new interface, compare after this defective 304 at the interface and first thermal anneal process, reduce to some extent again, can further improve the performance of device.
So far, formed the gate dielectric layer of forming by the silicon oxide layer after the nitrogenize, it had both had bigger dielectric constant, requirement to its thickness can be relaxed (relaxing to some extent aspect the stringency of technology controlling and process) to some extent, have stronger boron blocking capability again, can effectively improve the NBTI characteristic of device (especially PMOS device).
Fig. 7 is for adopting the NBTI characteristic schematic diagram of the preceding device of formation method of the present invention, and as shown in Figure 7, the pressing time when abscissa is test, ordinate is the rate of change of drain saturation current, and used experiment condition is 125 ℃ of temperature, voltage 1.32V.Each data wire that is linked to be respectively by each data point 701 among the figure has been represented the different test result of different components, as can be seen, adopt the device (this place refers to the PMOS device) of a traditional step thermal anneal process for such, drain saturation current rate of change during test has reached 15.7%, the NBTI performance of proof device is not very desirable, need further to improve the nitrogen concentration (improving the nitrogen distribution curve in the silicon oxide layer in other words) in its silica top layer, to strengthen blocking capability to boron.
Fig. 8 is the NBTI characteristic schematic diagram of the device after the employing formation method of the present invention, as shown in Figure 8, pressing time when abscissa is test, ordinate is the rate of change of drain saturation current, used experiment condition is similarly 125 ℃ of temperature, voltage 1.32V, each data wire that is linked to be respectively by each data point 801 among the figure has been represented the different test result of different components.At this moment, in the manufacturing process of each device, except having adopted two step thermal annealing methods, all the other process conditions (as, the process conditions of plasma nitridation process) are all identical with corresponding device among Fig. 7.Can see, after adopting two step thermal anneal process methods of the present invention, the rate of change of drain saturation current has dropped to 11.6% by original 15.7% during test, after proof adopts two step thermal annealing methods of the present invention, even do not change other process conditions, also can realize the increase of nitrogen concentration in the silica top layer, the blocking capability of boron correspondingly increases, and the NBTI performance of device has also obtained further improvement.
After the first embodiment of the present invention had adopted two step thermal anneal process, under the constant situation of other process conditions, the nitrogen concentration on the gate dielectric layer surface of device was improved, thereby has improved the NBTI characteristic of device (mainly being the PMOS device).
In other embodiments of the invention, can also utilize this two steps thermal anneal process method, under the prerequisite that the nitrogen concentration on gate dielectric layer top layer meets the demands, the processing time of power when reducing plasma treatment or shortening plasma, to effectively reduce the damage that plasma bombardment brings, further improve the performance of device.
Fig. 9 is the flow chart of second embodiment of gate dielectric layer formation method of the present invention, below in conjunction with Fig. 9 the second embodiment of the present invention is described in detail.
At first, on substrate, form silicon oxide layer (S901).Usually can utilize thermal oxidation method (RTO, Rapid Thermal Oxidation) or original position steam to produce method (ISSG, In-suitStream Generation) forms thin layer on silicon substrate silicon oxide layer, the thickness of this silicon oxide layer is usually 10 to 20
About.
Then, determine the nitrogen concentration (S902) that needs form according to the specific requirement of device in silicon oxide layer.The emphasis difference that different devices will be paid close attention to when making, the requirement on devices nitrogen concentration that has is high more good more, but the device that has may more focus on the damage of device being introduced when plasma nitrided, only require that nitrogen concentration reaches certain value and gets final product, therefore, before making a device, can specifically determine the nitrogen concentration that it requires the gate dielectric layer of formation earlier according to the characteristics of this device.
Then, the situation of first thermal anneal process that will carry out according to described nitrogen concentration and back is determined the process conditions (S903) of the pecvd nitride that will carry out.Specifically can comprise step in this step:
A, determine the process conditions of the pecvd nitride that will carry out according to described nitrogen concentration,, determine that by the traditional handicraft method process conditions of pecvd nitride are power 865W, 25 seconds processing times earlier as when the nitrogen concentration that requires to realize is 5.18%.
The situation of B, first thermal anneal process that will carry out according to the back is adjusted these process conditions.Owing to adopted two step thermal anneal process in the present embodiment, the nitrogen atmosphere of first thermal anneal process wherein can have influence on the nitrogen concentration in the silica top layer, therefore, can be in view of the above with determined process conditions in the steps A, carry out certain adjustment (reduce power or shorten the processing time) as power or processing time, as being adjusted into power 865W, 20 seconds processing times.
Follow again, according to described process conditions to described silicon oxide layer being carried out plasma nitridation process (S904).After this step, the nitrogen concentration in the silica top layer can temporarily not reach the value of requirement.In the present embodiment, the process conditions of this step pecvd nitride can be set to: chamber pressure as is 50mTorr between 10 to 100mTorr; Power is between 100 to 1500W, as is 900W; The time of plasma bombardment is 10 to 30 seconds, as is 20 seconds; The gas that feeds can only be nitrogen, also can be the mist of nitrogen and inert gas, as be the mist of nitrogen and helium or nitrogen and argon gas.The total flow that feeds gas as is 200sccm between 100 to 400sccm.
Then, under nitrogen atmosphere, described substrate is carried out first thermal anneal process (S905).Concrete process conditions can for: temperature is between 1000 to 1100 ℃, and the pressure in the stove is between 1 to 30Torr, and the time of processing is between 20 to 90 seconds.Wherein, nitrogen atmosphere refers to that nitrogen content accounts for major part, as accounts for more than 95%.
Then, under oxygen-containing atmosphere, described substrate is carried out second thermal anneal process (S906).Concrete process conditions can for: temperature is between 1000 to 1100 ℃, and the pressure in the stove is between 1 to 50Torr, and the time of processing is between 20 to 90 seconds.Wherein, oxygen-containing atmosphere refers to that oxygen content accounts for 5% to 50%.
So far, formed the gate dielectric layer of forming by the silicon oxide layer after the nitrogenize in the present embodiment, its nitrogen concentration can satisfy device requirement (as, the NBTI characteristic requires), simultaneously, the plasma damage that device is subjected in the present embodiment is less, and is favourable to the performance of further raising device.
Figure 10 is the comparison schematic diagram of the nitrogen concentration in the silica top layer of adopting formation method of the present invention front and back, as shown in figure 10, abscissa is the time of carrying out plasma treatment among the figure, ordinate is for utilizing X ray photoelectricity energy disperse spectroscopy (XPS, X-ray photo-electron spectrometry) nitrogen concentration in the silica top layer that obtains of test, on behalf of plasma power 1365W, the triangle number strong point among the figure shown in 1001 handle after 15 seconds down, carried out in the top layer after the step thermal anneal process nitrogen concentration (at this moment, though its nitrogen concentration is higher, its plasma damage that is subjected to is also bigger); After diamond data points shown in 1002 has been represented and handled different time under the plasma power 865W, carried out the nitrogen concentration in the top layer after the step thermal anneal process; After on behalf of plasma power 865W, the Square Number strong point shown in 1003 down handle different time, carried out the nitrogen concentration in the top layer after the two step thermal anneal process of the present invention.
As shown in Figure 10, after carrying out plasma treatment, if adopt a traditional step thermal annealing method, then if will in the silica top layer, reach 5.18% nitrogen concentration, at this step plasma power is under the situation of 865W, and the time of processing needs 25 seconds, and after adopting two step thermal annealing methods of the present invention, the time of handling can foreshorten to 20 seconds, can effectively reduce the damage that plasma bombardment brings to device.In addition, after two step of the employing thermal annealing methods, the power of handling at equal processing time decline low plasma also can reach identical nitrogen concentration in the top layer.Therefore, adopt method of the present invention after, can effectively reduce the damage that plasma brings to device by reducing plasma power or shortening plasma treatment time.
In addition, in the present embodiment, also utilize contactless C-V detection method to test respectively to have obtained the situation that adopts the interfacial state before and after the two step thermal anneal process methods of the present invention, reaching under the situation of identical nitrogen concentration, if adopt a traditional step thermal annealing method (supposing that its process conditions are following 25 seconds of 865W), then testing the interfacial state that obtains is 106.62 * E
10EV/cm
2, if adopt two step thermal annealing methods (corresponding process conditions are following 20 seconds of 865W) of the present invention, then testing the interfacial state that obtains is 95.12 * E
10EV/cm
2After confirm adopting method of the present invention, under the identical situation of the nitrogen concentration in the gate dielectric layer top layer, the interfacial state situation between silicon substrate and silicon oxide layer has obtained effective improvement, and this has further improved the performance of device.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (30)
1, a kind of formation method of gate dielectric layer is characterized in that, comprises step:
On substrate, form silicon oxide layer;
Described silicon oxide layer is carried out plasma nitridation process;
Under nitrogen atmosphere, described substrate is carried out first thermal anneal process;
Under oxygen-containing atmosphere, described substrate is carried out second thermal anneal process.
2, formation method as claimed in claim 1, it is characterized in that: the power of described plasma nitridation process is between 100 to 2000W.
3, formation method as claimed in claim 1 or 2 is characterized in that: the time of described plasma nitridation process is between 10 to 60 seconds.
4, formation method as claimed in claim 1, it is characterized in that: described nitrogen atmosphere refers to that nitrogen content accounts for more than 95%.
5, formation method as claimed in claim 1, it is characterized in that: described oxygen-containing atmosphere is made of jointly oxygen and nitrogen.
6, as claim 1 or 5 described formation methods, it is characterized in that: oxygen content accounts for 5% to 50% in the described oxygen-containing atmosphere.
7, formation method as claimed in claim 1 is characterized in that: the temperature of described first thermal anneal process is between 1000 to 1100 ℃.
8, formation method as claimed in claim 1, it is characterized in that: the chamber pressure of described first thermal anneal process is between 1 to 30Torr.
9, formation method as claimed in claim 1 is characterized in that: the time of described first thermal anneal process is between 20 to 60 seconds.
10, formation method as claimed in claim 1 is characterized in that: the temperature of described second thermal anneal process is between 1000 to 1100 ℃.
11, formation method as claimed in claim 1, it is characterized in that: the chamber pressure of described second thermal anneal process is between 1 to 50Torr.
12, formation method as claimed in claim 1 is characterized in that: the time of described second thermal anneal process is between 20 to 90 seconds.
13, formation method as claimed in claim 1 is characterized in that: described formation silicon oxide layer comprises and utilizes thermal oxidation method to form silicon oxide layer or utilize original position steam generation method to form silicon oxide layer.
14, formation method as claimed in claim 1, it is characterized in that: the thickness of described silicon oxide layer is 10 to 20
Between.
15, a kind of formation method of gate dielectric layer is characterized in that, comprises step:
On substrate, form silicon oxide layer;
Definite nitrogen concentration that need in described silicon oxide layer, form;
The situation of first thermal anneal process that will carry out according to described nitrogen concentration and back is determined the process conditions of the pecvd nitride that will carry out;
According to described process conditions to described silicon oxide layer is carried out plasma nitridation process;
Under nitrogen atmosphere, described substrate is carried out first thermal anneal process;
Under oxygen-containing atmosphere, described substrate is carried out second thermal anneal process.
16, formation method as claimed in claim 15, it is characterized in that: the process conditions of described plasma nitridation process comprise power and time at least.
17, formation method as claimed in claim 16, it is characterized in that: described power is between 100 to 1500W.
18, formation method as claimed in claim 16 is characterized in that: the described time is between 10 to 30 seconds.
19, formation method as claimed in claim 15, it is characterized in that: described nitrogen atmosphere refers to that nitrogen content accounts for more than 95%.
20, formation method as claimed in claim 15, it is characterized in that: described oxygen-containing atmosphere is made of jointly oxygen and nitrogen.
21, as claim 15 or 20 described formation methods, it is characterized in that: oxygen content accounts for 5% to 50% in the described oxygen-containing atmosphere.
22, formation method as claimed in claim 15 is characterized in that: the temperature of described first thermal anneal process is between 1000 to 1100 ℃.
23, formation method as claimed in claim 15, it is characterized in that: the chamber pressure of described first thermal anneal process is between 1 to 30Torr.
24, formation method as claimed in claim 15 is characterized in that: the time of described first thermal anneal process is between 20 to 60 seconds.
25, formation method as claimed in claim 15 is characterized in that: the temperature of described second thermal anneal process is between 1000 to 1100 ℃.
26, formation method as claimed in claim 15, it is characterized in that: the chamber pressure of described second thermal anneal process is between 1 to 50Torr.
27, formation method as claimed in claim 15 is characterized in that: the time of described second thermal anneal process is between 20 to 90 seconds.
28, formation method as claimed in claim 15 is characterized in that: described formation silicon oxide layer comprises and utilizes thermal oxidation method to form silicon oxide layer or utilize original position steam generation method to form silicon oxide layer.
29, formation method as claimed in claim 15, it is characterized in that: the thickness of described silicon oxide layer is 10 to 20
Between.
30, formation method as claimed in claim 15 is characterized in that, the situation of first thermal anneal process that will carry out according to described nitrogen concentration and back is determined the process conditions of the pecvd nitride that will carry out, and comprises step:
Process conditions according to the definite pecvd nitride that will carry out of described nitrogen concentration;
The situation of first thermal anneal process that will carry out according to the back is adjusted described process conditions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100463107A CN101393861A (en) | 2007-09-20 | 2007-09-20 | Gate dielectric layer forming method |
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| CN101997037A (en) * | 2010-09-20 | 2011-03-30 | 友达光电股份有限公司 | Semiconductor structure and manufacturing method thereof |
| US8609460B2 (en) | 2010-09-13 | 2013-12-17 | Au Optronics Corporation | Semiconductor structure and fabricating method thereof |
| CN103972071A (en) * | 2014-04-22 | 2014-08-06 | 上海华力微电子有限公司 | Manufacturing method for nitrogenous grid electrode oxidation layer |
| CN104183470A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN104347515A (en) * | 2013-08-01 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for flash memory |
| CN104465355A (en) * | 2014-12-24 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Technological method for gate oxide layer |
| CN105161525A (en) * | 2015-07-30 | 2015-12-16 | 上海华力微电子有限公司 | Method for preparing gate dielectric layer |
| CN105990234A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method of forming semiconductor device |
| CN106033720A (en) * | 2015-03-20 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN107706090A (en) * | 2017-09-22 | 2018-02-16 | 德淮半导体有限公司 | Fleet plough groove isolation structure, semiconductor structure and preparation method thereof |
| CN109003879A (en) * | 2017-06-06 | 2018-12-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of gate dielectric layer |
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| CN105990234B (en) * | 2015-01-30 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
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| CN107706090A (en) * | 2017-09-22 | 2018-02-16 | 德淮半导体有限公司 | Fleet plough groove isolation structure, semiconductor structure and preparation method thereof |
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