CN101388348A - Wafer stage package cutting method protecting connection pad - Google Patents
Wafer stage package cutting method protecting connection pad Download PDFInfo
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- CN101388348A CN101388348A CNA2007101537451A CN200710153745A CN101388348A CN 101388348 A CN101388348 A CN 101388348A CN A2007101537451 A CNA2007101537451 A CN A2007101537451A CN 200710153745 A CN200710153745 A CN 200710153745A CN 101388348 A CN101388348 A CN 101388348A
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Abstract
The invention discloses a cutting method for protecting the wafer-level packaging of a connecting pad, which comprises forming a plurality of cavities and pre-cutting channels on the front of an upper cover wafer, wherein the depth of each pre-cutting channel is smaller than the depth of each cavity, then bonding the upper wafer and an element wafer whose surface is provided with a plurality of elements and a plurality of connecting pads, then conducting the upper wafer cutting technology, cutting through the upper cover wafer along the pre-cutting channels, removing partial upper cover wafer which is not bonded with the element wafer to expose the connecting pads, finally conducting the element wafer cutting technology to form a plurality of package tube cores.
Description
Technical field
The present invention relates to a kind of cutting method of protecting the wafer-class encapsulation of connection gasket, particularly a kind ofly form precut road, to simplify cutting technique, improve rate of finished products and to protect the cutting method of the wafer-class encapsulation of connection gasket in upper cover wafer.
Background technology
The encapsulation of semiconductor element (packaging) is the important step of its technology; so-called encapsulation is meant the core texture in the device is combined; the effect of encapsulation is to protect the semiconductor element (as optical element, microcomputer electric component etc.) of fragility to avoid being subjected to the infringement (as mechanical force injury or particle contamination etc.) of external environment, and shoulders the function of mechanical support and signal output or input.
Known packaging technology is as follows: at first will finish the wafer cutting and separating that adds technology processing and be many tube core (die), the tube core of many separation is placed on the lead frame and fixing with epoxy (epoxy), that this step claims is sticking brilliant (mount), via steps such as routing or flip-chips, aforesaid die package is finished again.The package die size that this kind packaged type is produced is bigger, and encapsulation process is loaded down with trivial details, and does not meet present electronic product and stress demand frivolous and that volume is little, and needs the individuation operation, and very the person needs manual work, and is not suitable for producing in batches; Moreover the bottleneck of this kind encapsulation technology often appears in the middle of the cutting technique in later stage, and external mechanical force may cause structural destruction, and the particulate that produced may polluted product in the process of cutting, causes decrease in yield.
Summary of the invention
Main purpose of the present invention is to provide a kind of cutting method of protecting the wafer-class encapsulation of connection gasket, to promote finished product rate and reliability.
For reaching above-mentioned purpose, the invention provides a kind of cutting method of protecting the wafer-class encapsulation of connection gasket.At first, one upper cover wafer is provided, and this upper cover wafer comprises a positive and back side, and a surperficial definition process is carried out in this front of this upper cover wafer certainly, form a plurality of cavitys and a plurality of precut road simultaneously in this upper cover wafer, and respectively should precut the thickness of the degree of depth in road less than this upper cover wafer.One element wafer also is provided, one surface of this element wafer is provided with a plurality of elements and a plurality of connection gasket, then engage this upper cover wafer and this element wafer, these cavitys and this element wafer form a plurality of airtight chambeies, seal these elements respectively, carry out a upper cover wafer cutting technique from this back side of this upper cover wafer then, after cutting this upper cover wafer along these precut roads, make and do not break away from this upper cover wafer of element wafer engaging portion, to expose these connection gaskets on this element wafer surface, carry out an element wafer cutting technique afterwards, form a plurality of independently package die.
The cutting method of this wafer-class encapsulation can be simplified cutting technique, destruction and pollution that reduction is caused because of cutting, and be applicable to the encapsulation of general electronic component, microcomputer electric component (MEMS device) and optical element (optical device), can effectively reduce last part technology (as wafer cutting, sliver, cleaning ... etc.) loss of the rate of finished products that causes.In addition, this technology compatible in general semiconductor technology, be applicable to batch produce and have measure easily, advantages such as high finished product rate, and can overcome the difficult problem of known technology.
Description of drawings
The schematic diagram of the manufacture method that the wafer that Fig. 1 to Fig. 6 is illustrated for a foundation preferred embodiment of the present invention cuts.
Fig. 7 to Figure 10 is the schematic diagram of the manufacture method of the foundation wafer that another preferred embodiment of the present invention illustrated cutting.
Description of reference numerals
10 first wafers, 12 second wafers
The front of 14 upper cover wafer, 16 upper cover wafer
18 cavitys, 20 precut roads
The surface of 22 element wafers, 24 element wafers
26 elements, 28 connection gaskets
30 grafting materials, 32 airtight chambeies
The back side 36 Cutting Roads of 34 upper cover wafer
38 package die, 42 first wafers
First wafer of front 422 parts of 421 first wafers
The back side 44 second wafers of 423 first wafers
46 adhesion coatings, 48 chip carriers
50 cavity laterals, 52 precut roads
54 cavitys, 56 upper cover wafer
The front of 561 upper cover wafer
Embodiment
Please refer to Fig. 1 to Fig. 6, the schematic diagram of the manufacture method that the wafer that Fig. 1 to Fig. 6 is illustrated for a foundation preferred embodiment of the present invention cuts.As shown in Figure 1, first wafer 10 and second wafer 12 are provided, engage (fusion bonding) or plasma-activated bonding method known wafer joint technologies such as (plasma activation bonding) through anodic bonding (anodic bonding), eutectic joint (eutectic bonding), fusion and engage first wafer 10 and second wafer 12, to form upper cover wafer 14.First wafer 10 can comprise a standard wafer, a silicon wafer or the figuratum wafer of a definition, second wafer 12 can be a chip glass or an encapsulated wafer, a silicon wafer or the wafer of other materials, moreover the selection of upper cover wafer 14 is not limited to that this preferred embodiment is described to be engaged and get by two wafer, and the standard wafer of monolithic or silicon wafer also can be used as upper cover wafer 14 uses.
As shown in Figure 2, carry out a picture on surface definition process, form a plurality of cavitys (cavity) 18 and many precut roads (precutting line/prescribe line) 20 in a front 16 of upper cover wafer 14 simultaneously.This preferred embodiment is for forming a photoresist layer (figure does not show) earlier in the front 16 of upper cover wafer 14, then carry out exposure imaging technology with a photomask with cavity pattern and precut road pattern, purpose is the cavity pattern and precuts the road design transfer to this photoresist layer, and then carry out an etch process, for example a wet etching process or a dry etching process, first wafer 10 is carried out etching, define cavity 18 and precut road 20 simultaneously in the front 16 of upper cover wafer 14, wherein the size of cavity 18 is not done specific restriction at this, the live width in precut road 20 then is the smaller the better, preferred live width is less than 70 microns (micro-meter, μ m).
With Fig. 2 is example, and (inductive coupling plasma, ICP) etch process carry out the picture on surface definition process of this preferred embodiment, with SF by induction type plasma coupling
6, C
4F
8And O
2Deng being etching gas; coil power during etching (coil power) is between 0-3000 watt (W); platform power power (platen power) is about between 0-250 watt; the degree of depth in precut road 20 usually can be less than the degree of depth of cavity 18 itself; and the design in precut road 20 is to be principle not run through upper cover wafer 14, and its degree of depth can be less than or equal to the thickness of first wafer 10 itself.With this preferred embodiment is example, cavity 18 can be less than 10 to 1 with precut road 20 preferred live width ratios, cavity 18 is about 500 μ m and 200 μ m with the degree of depth in precut road 20, yet the degree of depth that precuts road 20 is a principle with eating thrown upper cover wafer 14 not, and for example its degree of depth can reach 450 μ m.On technology, the degree of depth in cavity 18 and precut road 20 can change along with the live width size, because the live width in precut road 20 is less than cavity 18, thus, after induction type plasma coupling etch process was finished, the degree of depth in each precut road 20 will be less than the degree of depth of each cavity 18.In addition, the degree of depth in precut road 20 will increase and deepen with live width, when for example the live width in precut road 20 is set in 5 microns, its degree of depth is about about 200 microns, when yet the live width when precut 20 is amplified to 50 microns, its degree of depth will with add and be deep to about 390 microns, see thus, precut road 20 degree of depth of the present invention and the visual different demands of live width size adjust.
As shown in Figure 3, other provides element wafer 22, and the surface 24 of element wafer 22 is provided with a plurality of elements (device) 26 and a plurality of connection gasket 28 as electrode, and element 26 can comprise optical element, microcomputer electric component or general electronic component.Thereafter, first wafer, 10 surfaces of desiring to engage with element wafer 22 in upper cover wafer 14 form grafting material 30, for example in the mode of wire mark at first wafer, 10 surperficial wire mark one deck glass cements (glass frit), or will have the material of joint capacity with other technology modes, for example macromolecule grafting material or metal are coated with or are deposited on the front 16 of upper cover wafer 14.Grafting material 30 is not limited to be formed on the front 16 of upper cover wafer 14, also can be formed at the 24 corresponding positions, surface of element wafer 22.What will remark additionally in addition is, it is described that process sequence of the present invention is not limited to this preferred embodiment: form precut road 20 in the front 16 of upper cover wafer 14 earlier and form grafting material 30 again, also can earlier after the front of upper cover wafer 14 forms grafting material 30, form precut road 20 again.
Then as shown in Figure 4; air-tightness engages upper cover wafer 14 and element wafer 22; the mode of its joint can utilize glass cement to engage (glass frit bonding) shown in this preferred embodiment or the mode that engages by eutectic engages two plates; and the cavity 18 of upper cover wafer 14 will correspond to the element 26 on the surface 24 of being located at element wafer 22 respectively; engage 22 of rear chamber 18 and element wafers and form a plurality of airtight chambeies (sealing chamber) 32; these elements 26 are sealed in respectively in each airtight chamber 32, are positioned at the element 26 in airtight chamber 32 with protection.
Please refer to Fig. 5, carry out a upper cover wafer cutting technique, cut to put on from the back side 34 of upper cover wafer 14 and along precut road 20 and cover wafer 14.As shown in Figure 6, when a cutter tool carried out upper cover wafer 14 cutting techniques, can the be more preformed precut road of formed a plurality of Cutting Road 36 live widths of cutting tool 20 was big, but not as limit.Because preformed precut road 200 minutes is narrow, only there are a spot of current to flow down along pre-incisor path 20, therefore institute's trickle white residue that produces or other pollutions are difficult for connection gasket 28 on the lesion element wafer 22 in the cutting process, electrically stable and avoid connection gasket 28 to be polluted to keep product, in general, in the ban precut road 20 live widths of Xing Chenging more hour, in the wafer cutting technique, connection gasket 28 probability contaminated or damage are also just low more, and the finished product rate is also just good more.Yet, cut and put on the method for covering wafer 14 and be not limited to above-mentioned cutting tool, in addition can change and to carry out with dry etching process or wet etching process, the big I of formed Cutting Road 36 live widths is done appropriateness adjustment, for example form and the identical Cutting Road 36 of precut road 20 live widths size, can reach the purpose of cutting upper cover wafer 14 equally.In addition, if second wafer 12 in the upper cover wafer 14 is the chip glass or the wafer of other light-permeables, when carrying out this wafer cutting technique, when if preformed pre-incisor path 20 degree of depth are touched second wafer 12, carry out to know the position of seeing precut road 20 before the wafer cutting technique, therefore can precisely control cutting position, and reduce cutting error.
Please refer to Fig. 6, after will not removing with element wafer 22 engaging portion upper cover wafer 14, making originally, covered connection gasket 28 exposes, at this moment, can directly carry out a wafer level test (wafer level test), for all be packaged in elements 26 in the annular seal space 32 carry out synchronously function or electrically on test.Afterwards, carry out an element wafer cutting technique again, separate these airtight chambeies 32 and be located at element 26 in the airtight chamber 32, with the tube core 38 that forms a plurality of individual packages, above-mentioned package die 38 by follow-up processing assembling, can be used in the various consumption electronic products again.
Except that aforesaid preferred embodiment, the present invention provides a kind of cutting method of wafer-class encapsulation in addition, except that the encapsulation that is applicable to general motor electronic element, be specially adapted to charge-coupled device (Charge-CoupledDevice, CCD), CMOS (Complementary Metal Oxide Semiconductor) inductor (CMOS Image Sensor, optics sensing element such as CIS), or digital light is handled (Digital Light Processing, DLP), monocrystalline silicon display panels (Liquid Crystal on Silicon, the encapsulation of optical display element such as LCoS), its implementing procedure such as Fig. 7 are to shown in Figure 10.Consider optical element meticulous requirement to light incident after encapsulation, the encapsulating optical element gets second wafer 44 (as shown in figure 10) that upper cover wafer comprises first wafer 42 (as shown in Figure 7) and a transparent material, wherein first wafer 42 can comprise a standard wafer or a silicon wafer, and preferred second wafer, 44 materials comprise a chip glass or a quartz wafer.Please refer to Fig. 7, integrality for second wafer, 44 surfaces of guaranteeing transparent material in technology, in this preferred embodiment, earlier with first wafer 42 with adhesion coating 46, for example a ultraviolet tape (UV tape), thermal separation gel band (thermal releasetape) or other have the mating substance of biadhesive, first wafer 42 is fixed to chip carrier (carrier) 48, for example a chip glass or a silicon wafer.Then as shown in Figure 8, a surperficial definition process is carried out in front 421 to first wafer 42, for example on the front 421 of first wafer 42, form a photoresist layer (figure does not show) earlier and then carry out exposure imaging technology with a photomask with cavity lateral (cavity trench) pattern and precut road pattern, purpose is cavity lateral pattern and precuts the road design transfer to this photoresist layer, and then carry out an etch process, for example a wet etching process or a dry etching process, first wafer 42 is carried out etching, define cavity lateral 50 and precut road 52 simultaneously positive 421.In this preferred embodiment, define these cavity laterals 50 and these precut roads 52 by induction type plasma coupling etch process, carry out the picture on surface definition process of this preferred embodiment, with SF
6, C
4F
8And O
2Deng being etching gas; coil power during etching is between 0-3000 watt; platform power power is about between 0-250 watt; the degree of depth in precut road 52 usually can be less than the degree of depth of cavity lateral 50; and the cavity lateral 50 of this preferred embodiment runs through first wafer 42; and the design in precut road 52 is to be principle not run through first wafer 42, and its degree of depth can be less than or equal to the thickness of first wafer 42 itself.For enabling the position and the pattern in cavity lateral among clearer understanding the present invention 50 and precut road 52, as shown in Figure 9, Fig. 9 is the overlooking surface schematic diagram of first wafer 42 after the surperficial definition process of experience, wherein the tangent line AA ' among Fig. 9 corresponds to the AA ' of Fig. 8, with this preferred embodiment is example, cavity lateral 50 is about 500 μ m and 3 μ m with the live width in precut road 52, preferred live width ratio can be less than 10 to 1, cavity lateral 50 is about 500 μ m and 200 μ m with the degree of depth in precut road 52, the degree of depth in wherein precut road 52 is with eating thrown first wafer 42 not, its degree of depth can reach 450 μ m, in addition, cavity lateral 50 surrounds one " mouth " font, and first wafer 422 with a part surrounds respectively.
Please refer to Figure 10 afterwards, remove adhesion coating 46 and chip carrier 48, and have the back side 423 of first wafer 42 of precut road pattern to be engaged to second wafer 44 definition.Because it is the silicon wafer of a standard thickness that this preferred embodiment uses first wafer, its thickness is about about 500 microns, utilization removes the technology of adhesion coating, for example: when being adhesion coating 46 with the ultraviolet tape, utilize a ultraviolet radiation (UVradiation) technology, make ultraviolet tape lose viscosity; Perhaps, when being adhesion coating 46 with the thermal separation gel band, then utilize a heating process, make thermal separation gel band lose viscosity, the equipment that can utilize wafer chuck or electrostatic chuck etc. to move wafer separates with adhesion coating 46 first wafer 42 with chip carrier 48 afterwards.Because when previous step, first wafer 422 of part is surrounded by cavity lateral 50 and is independent, when removing adhesion layer 46, part first wafer 422 that is positioned at 52 of cavity laterals will be detained on adhesion coating 46, and has first wafer 42 in precut road 52 to separate with definition.After being engaged to second wafer 44, because being positioned at part first wafer 422 in 52 in precut road originally has been removed, the space that is available will form a plurality of cavitys 54 jointly with second wafer 44 that engages, therefore, first wafer 42 behind the joint and second wafer 44 constitute upper cover wafer 56, and front 561 definition of upper cover wafer 56 have cavity pattern and precut road pattern, for the follow-up usefulness that encapsulates.Encapsulation flow process afterwards is identical with last preferred embodiment, and its schematic flow sheet and related description please refer to Fig. 3 to Fig. 6 of last preferred embodiment, and to form the tube core of a plurality of individual packages, process will not redescribed at this.
Compare with last preferred embodiment, this preferred embodiment is when the pattern of the front of definition first wafer 42, only etch the cavity lateral 50 of the about 500 μ m of live width, with part first wafer 42 that independently goes out 50 of cavity laterals, when removing adhesion coating 46, part first wafer 422 of 50 of cavity laterals is removed in the lump, and engage to after the upper cover wafer 56 with second wafer 44 with first wafer 42, cavity lateral 50 originally is the border into cavity 54, define the size and the pattern of cavity 54 in the front 561 of upper cover wafer 56, hence one can see that, when the front 421 of etching first wafer 42 (as shown in Figure 9), only need etch cavity lateral 50 and go out the border of cavity 54, not need the pattern of whole cavity 52 is carried out etching, can significantly reduce etching period required in the technology with simple defining.Moreover, first wafer 42 just engages with second wafer 44 behind cavity lateral 50 and precut road 52, second wafer 44 does not experience etch process repeatedly, guaranteeing the smooth of second wafer, 44 surfaces, in order to avoid unnecessary scattering or reflection take place during light penetration after encapsulation.
By aforesaid these preferred embodiments as can be known, the present invention uses a surperficial definition process, only with single processing step, on upper cover wafer, form a plurality of cavitys and many precut roads simultaneously, replace known need form cavity or Cutting Road respectively with the processing step more than the secondary process, shorten whole process time and effective cutting technique of simplifying after wafer engages, and can precisely control and desire the cutting position and the degree of depth.Because preformed precut road live width is very narrow and small, can effectively avoid putting on the white residue that cover in the wafer process or polluting the connection gasket of attacking on the element wafer cutting, prevent the facts generation of connection gasket surface contamination.Moreover before being divided into other package die, the wafer that full wafer has encapsulated can be participated in detection directly, and again, the package die after cutting apart is close with naked brilliant size, meets the trend of electronic goods microminiaturization, and is suitable for producing in batches, is advantage of the present invention place.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (15)
1, a kind of cutting method of protecting the wafer-class encapsulation of connection gasket comprises:
One upper cover wafer is provided, and this upper cover wafer comprises the front and the back side;
Carry out a surperficial definition process from this front of this upper cover wafer, forming simultaneously a plurality of cavitys and a plurality of precut road in this upper cover wafer, and the degree of depth that respectively should precut road is less than the degree of depth of this cavity respectively;
One element wafer is provided, and the surface of this element wafer is provided with a plurality of elements and a plurality of connection gasket;
Engage this upper cover wafer and this element wafer, these cavitys are alignd these elements so that form a plurality of airtight chambeies between this upper cover wafer and this element wafer, seal respectively this element respectively;
Carry out a upper cover wafer cutting technique from this back side of this upper cover wafer, cut this upper cover wafer, make not break away to expose these connection gaskets of this element wafer with this upper cover wafer of this element wafer engaging portion along these precut roads; And
Carry out an element wafer cutting technique, form a plurality of independently package die.
2, cutting method as claimed in claim 1 wherein should precut the live width in road less than 70 microns.
3, cutting method as claimed in claim 1 should the surface definition process be an etch process wherein.
4, cutting method as claimed in claim 3, wherein the live width in these precut roads is less than the live width of these cavitys, thus behind this etch process the degree of depth in these precut roads less than the degree of depth of these cavitys.
5, cutting method as claimed in claim 1, wherein this upper cover wafer cutting technique comprises an etch process.
6, cutting method as claimed in claim 1, wherein this upper cover wafer cutting technique comprises and utilizes a cutter tool to carry out this upper cover wafer cutting technique.
7, cutting method as claimed in claim 1, other includes after these connection gaskets of this element wafer expose, and carries out a wafer level test.
8, a kind of cutting method of protecting the wafer-class encapsulation of connection gasket comprises:
First wafer is provided;
One adhesion coating is provided, fixes the back side to one chip carrier of this first wafer;
Carry out a surperficial definition process from a front of this first wafer, form a plurality of cavity laterals and a plurality of precut road simultaneously in this first wafer, these cavity laterals are positioned between these precut roads and surround first wafer of part, and the degree of depth that respectively should precut road is less than the degree of depth of this cavity lateral respectively;
Part first wafer that removes this adhesion coating, this chip carrier and surrounded by these cavity laterals;
Engage this back side to the second wafer of this first wafer, form a upper cover wafer, with a plurality of cavitys that are defined between these precut roads of a positive formation in this upper cover wafer;
One element wafer is provided, and a surface of this element wafer is provided with a plurality of elements and a plurality of connection gasket;
Engage this upper cover wafer and this element wafer, make these cavitys and this element wafer form a plurality of airtight chambeies, these elements of each self seals;
Carry out a upper cover wafer cutting technique from a back side of this upper cover wafer, cut this upper cover wafer, make not break away from, to expose these connection gaskets of this element wafer with this upper cover wafer of this element wafer engaging portion along these precut roads;
Carry out a wafer level test; And
Carry out an element wafer cutting technique, form the tube core of a plurality of individual packages.
9, cutting method as claimed in claim 8, wherein this second wafer comprises a chip glass or a quartz wafer.
10, cutting method as claimed in claim 8 wherein should precut the live width in road less than 70 microns.
11, cutting method as claimed in claim 8, wherein respectively this cavity compares less than 10 to 1 with the live width that respectively should precut the road.
12, cutting method as claimed in claim 8 should the surface definition process be an etch process wherein.
13, cutting method as claimed in claim 12, wherein the live width in these precut roads is less than the live width of these cavity laterals, thus behind this etch process the degree of depth in these precut roads less than the degree of depth of these cavity laterals.
14, cutting method as claimed in claim 8, wherein this upper cover wafer cutting technique comprises an etch process.
15, cutting method as claimed in claim 8, wherein this upper cover wafer cutting technique comprises and utilizes a cutter tool to carry out this upper cover wafer cutting technique.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101537451A CN100570842C (en) | 2007-09-14 | 2007-09-14 | The cutting method of the wafer-class encapsulation of protection connection gasket |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101537451A CN100570842C (en) | 2007-09-14 | 2007-09-14 | The cutting method of the wafer-class encapsulation of protection connection gasket |
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| CN101388348A true CN101388348A (en) | 2009-03-18 |
| CN100570842C CN100570842C (en) | 2009-12-16 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104555898A (en) * | 2014-12-05 | 2015-04-29 | 华进半导体封装先导技术研发中心有限公司 | Method for reusing seal cover in wafer level package |
| CN105328804A (en) * | 2014-06-20 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Cutting method of wafer |
| CN110838462A (en) * | 2018-08-15 | 2020-02-25 | 北科天绘（苏州）激光技术有限公司 | Mass transfer method and system of device array |
| CN111438444A (en) * | 2018-12-28 | 2020-07-24 | 北京北科天绘科技有限公司 | Laser cutting method and system based on device array mass transfer |
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2007
- 2007-09-14 CN CNB2007101537451A patent/CN100570842C/en not_active Expired - Fee Related
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| CN105328804A (en) * | 2014-06-20 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Cutting method of wafer |
| CN105328804B (en) * | 2014-06-20 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of cutting method of wafer |
| CN104555898A (en) * | 2014-12-05 | 2015-04-29 | 华进半导体封装先导技术研发中心有限公司 | Method for reusing seal cover in wafer level package |
| CN110838462A (en) * | 2018-08-15 | 2020-02-25 | 北科天绘（苏州）激光技术有限公司 | Mass transfer method and system of device array |
| CN110838462B (en) * | 2018-08-15 | 2022-12-13 | 北科天绘(合肥)激光技术有限公司 | Mass transfer method and system of device array |
| CN111438444A (en) * | 2018-12-28 | 2020-07-24 | 北京北科天绘科技有限公司 | Laser cutting method and system based on device array mass transfer |
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