CN101373639B - Memory time sequence measuring circuit and test method thereof - Google Patents
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Abstract
The invention relates to a memory time sequence measuring circuit and a test method thereof. A time sequence measuring circuit of a memory conducts different delays for a plurality of balanced test signals so as to generate a plurality of test signals after the delays. Each test signal after the delay is sent to one of a plurality of input pins of a subsystem of the memory. With the help of the adjustment of the retardation of a test signal source after the delays, alternation time sequence parameters of the subsystem of the memory are tested and measured. When the time sequence circuit is in a circular oscillation, the resolution factors thereof can be measured.
Description
Technical field
The present invention relates to a kind of memory time sequence measuring circuit, memory construction and its method of testing.
Background technology
In memory test, it is essential how correctly to measure interchange sequential (AC timing) parameter.Generally speaking, exchanging time sequence parameter comprises at least: setting-up time (setup time) parameter, retention time (hold time) parameter and access time (access time) parameter.
In the past, normally utilize automatic test machine platform (ATE, automatic testing machine) to exchange the test of time sequence parameter.But, can cause several shortcomings like this:
(1) because the resolution (resolution) of automatic test machine platform is very big, the interchange time sequence parameter that is unsuitable for storer is measured.Generally speaking, the resolution of automatic test machine platform may be up to 350ps (pico-second, psec); Yet the interchange time sequence parameter of storer may have only dozens of ps.This precision that also easily causes measuring reduces.
(2) test signal sent of automatic test machine platform may have error.When transferring to the circuit board that is loaded with storer to be measured, this test signal will cause error (signal change) bigger by coiling on the circuit board and signal wire.
(3) be difficult for learning real time-ordered measurement value in the time-ordered measurement.This is because the time-ordered measurement value can only be learnt by the automatic test machine platform, but the signal sequence of memory inside can only be known by inference by the measuring-signal that the automatic test machine platform is sent.
(4) because test signal, control signal and clock signal are all sent into by the storer outside, will cause the pin count of storer very high, increase chip area.
For improving above-mentioned shortcoming, the present invention proposes a kind of memory time sequence measuring circuit, memory construction and its method of testing.
Summary of the invention
The invention provides a kind of memory time sequence measuring circuit, memory construction and its method of testing, it can provide the time-ordered measurement of pinpoint accuracy.
The invention provides a kind of memory time sequence measuring circuit, memory construction and its method of testing, it can reduce the used output and input pins quantity of time-ordered measurement.
The invention provides a kind of memory time sequence measuring circuit, memory construction and its method of testing, it can improve efficiency of measurement.
The invention provides a kind of memory time sequence measuring circuit, memory construction and its method of testing, its signal sequence that can reduce chip exterior changes the influence to test result caused.
The invention provides a kind of memory time sequence measuring circuit, memory construction and its method of testing, it can finish time-ordered measurement easily.
The invention provides a kind of memory time sequence measuring circuit, memory construction and its method of testing, it can measure the Measurement Resolution of this memory time sequence measuring circuit.
Example of the present invention proposes a kind of memory chip, comprising: a memory sub-system, be used to store data, and it comprises a plurality of pins; One clock trees is synchronously sent a testing source; An and sequential metering circuit, this testing source that reception is sent by this clock trees, this time sequence measuring circuit distinctly postpones this testing source to produce a plurality of delays back test signal, test signal is delivered to the described pin of this memory sub-system after described the delay, and the storer of testing this memory sub-system by the sequential of adjusting described delay back testing source exchanges time sequence parameter.
Another example of the present invention proposes a kind of time sequence measuring circuit of memory chip.This memory chip comprises: a memory sub-system and the clock trees that a testing source is synchronously sent.This time sequence measuring circuit comprises: a plurality of time-ordered measurements unit, each time-ordered measurement unit are coupled to one of a plurality of pins of this memory sub-system to measure the memory parameter of this memory sub-system.Each time-ordered measurement unit comprises: a switch has: a control end, receive an external switch control signal, and one first end receives this testing source that this clock trees is sent, and one second end receives an external data, one the 3rd end, and one the 4th end; The delay circuit of a plurality of serial connections, one input end of one first order delay circuit of described delay circuit is coupled to the 4th end of this switch, the afterbody of described delay circuit can be exported a ring oscillator output signal, a resolution of this this time sequence measuring circuit of ring oscillator output signal representative; And a multiplexer, have: a control end receives an external delay control signal; A plurality of input ends are coupled to a plurality of output terminals of described delay circuit respectively; And an output terminal, be coupled to this corresponding pin of this memory sub-system.This external switch control signal is controlled the operator scheme of this time-ordered measurement unit, and this external delay control signal is controlled the mistiming between this output signal of this testing source and this multiplexer.
Another example of the present invention proposes a kind of method of testing of storer, and this method comprises: synchronously send a test signal; Postpone this test signal respectively to produce a plurality of delays back test signal respectively, to input to a plurality of pins of this storer; And check that a output data that this storer exports is whether correct and described the delays back test signal of the described pin that inputs to this storer carried out the sequential adjustment, to measure an interchange time sequence parameter of this storer.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 shows the calcspar of the memory chip that has memory time sequence measuring circuit according to an embodiment of the invention.
Fig. 2 is the synoptic diagram according to the memory time sequence measuring circuit of the embodiment of the invention.
Fig. 3 is the synoptic diagram according to the time-ordered measurement unit of the embodiment of the invention.
Fig. 4 a and 4b show the signal timing diagram according to the close beta signal of memory chip of the present invention.
The reference numeral explanation
10: memory chip
11a, 11b: memory sub-system
12: control circuit
13a, 13b: time sequence measuring circuit
14: frequency divider
15: multiplexer
16: clock trees
17: the output data register
19: the automatic test machine platform
21a-21g: time-ordered measurement unit
31: switch
32: multiplexer
33a-33d: phase inverter is right
INV1-INV9: phase inverter.
Embodiment
At present embodiment, for reducing the test signal change of chip exterior, all test signals are all produced by clock trees (clock tree).This clock trees receives single clock signal; That is this single clock signal can be considered the root point (root) of this clock trees.This clock trees with test signal evenly (synchronously) deliver to each time-ordered measurement unit, with the interchange time sequence parameter of testing memory.
Fig. 1 shows the calcspar of the memory chip that has memory time sequence measuring circuit according to an embodiment of the invention.As shown in Figure 1, this memory chip 10 comprises: memory sub-system 11a and 11b, control circuit 12, time sequence measuring circuit 13a and 13b, frequency divider 14, multiplexer 15, clock trees 16 and output data register 17.
Memory sub-system is used to store data, and it is tested object.Though note that to demonstrate two memory sub-system 11a and 11b in Fig. 1, the memory sub-system quantity that memory chip of the present invention comprised is not limited to this.In addition, the memory capacity of these memory sub-systems is unnecessary equates.The quantitative relation of memory sub-system and time sequence measuring circuit is 1 pair 1.
For reducing the control signal pin of memory chip 10, control circuit 12 can comprise shift register, and this shift register comprises the register of many groups.One group of register is used for keeping in and exporting the required control signal of some time sequence measuring circuits.Control signal is delivered to control circuit 12 in the memory chip 10 by the outside via control signal pin CTL_IN.
Time sequence measuring circuit is used to measure the interchange time sequence parameter of memory sub-system.Fig. 2-Fig. 4 under the detailed structure of time sequence measuring circuit please refer to operation.
When memory chip 10 comprised a plurality of time sequence measuring circuit, multiplexer 15 can select to take out the output signal RING_OUT of which time sequence measuring circuit.In Fig. 1, (a plurality of) input end of frequency divider is coupled to (a plurality of) output terminal of (a plurality of) time sequence measuring circuit, and the output terminal of frequency divider then is coupled to the input end of multiplexer.Existing this skill person is when knowing that it is shown that the relation that couples of multiplexer and frequency divider is not subject to Fig. 1.Such as, the relation of coupling of multiplexer and frequency divider can be varied to, and the output signal RING_OUT that multiplexer receives (a plurality of) time sequence measuring circuit therefrom selects one and exports to frequency divider; That is (a plurality of) input end of multiplexer is coupled to (a plurality of) output terminal of (a plurality of) time sequence measuring circuit, and the output terminal of multiplexer then is coupled to the input end of frequency divider
When memory sub-system when carrying out functional test, automatic test machine platform 19 can be sent the required external function testing signal D_EXT of memory sub-system to time sequence measuring circuit.External function testing signal D_EXT is such as comprising: address signal, data input signal, write-enable signal (WEB), output enable signal (OE), chip select signal (CSB) and clock signal C K etc.
Fig. 2 is the synoptic diagram according to the time sequence measuring circuit of the embodiment of the invention.Time sequence measuring circuit 13a is essentially similar or identical with the structure of 13b.Now please refer to Fig. 2, time sequence measuring circuit 13a comprises a plurality of time-ordered measurements unit (timing measurement unit, TMU) 21a-21g.For illustrating, memory sub-system comprises: address signal input pin A, data input pin DI, write-enable signal input pin WEB, output enable signal input pin OE, chip select signal input pin CSB, clock signal input pin CK and data output connecting pin DO etc.
Each time-ordered measurement unit is coupled to one of input pin of memory sub-system 11a.Such as, time-ordered measurement unit 21a is coupled to address signal input pin A.Time-ordered measurement unit 21b is coupled to data input pin DI.Time-ordered measurement unit 21c is coupled to write-enable signal input pin WEB.Time-ordered measurement unit 21d is coupled to output enable signal input pin OE.Time-ordered measurement unit 21e is coupled to chip select signal input pin CSB.Time-ordered measurement unit 21f is coupled to clock signal input pin CK.Time-ordered measurement unit 21g is coupled to data output connecting pin DO.
Each time-ordered measurement unit 21a-21g can carry out the different mode operation and test signal T_CK is applied different retardations under the control of control signal SW and D_SEL.As shown in Figure 2, time-ordered measurement unit 21a postpones into signal A_IN with test signal T_CK, to input to address signal input pin A.Time-ordered measurement unit 21b postpones into signal DI_IN with test signal T_CK, to input to data input pin DI.Time-ordered measurement unit 21c postpones into signal WEB_IN with test signal T_CK, to input to write-enable signal input pin WEB.Time-ordered measurement unit 21d postpones into signal OE_IN with test signal T_CK, to input to output enable signal input pin OE.Time-ordered measurement unit 21e postpones into signal CSB_IN with test signal T_CK, to input to chip select signal input pin CSB.Time-ordered measurement unit 21f postpones into signal CK_IN with test signal T_CK, to input to clock signal input pin CK.Time-ordered measurement unit 21g postpones into signal DO_IN with test signal T_CK, to input to output data register 17.The access time that time-ordered measurement unit 21g and output data register 17 can be used for testing this memory sub-system.
The operator scheme of time-ordered measurement unit can be understood with Fig. 4 with reference to figure 3 with the delay operation.
Fig. 3 is the synoptic diagram according to the time-ordered measurement unit of the embodiment of the invention.The structure of each time-ordered measurement unit 21a-21g is mutually the same basically or similar.As shown in Figure 3, time-ordered measurement unit 21a comprises: switch 31, the phase inverter of a plurality of serial connections is right, impact damper INV9, and multiplexer 32.Fig. 3 is that example is done explanation with the phase inverter of 4 serial connections to 33a-33d, but the present invention is not limited to this.Delayed control signal D_SEL can determine the retardation of time-ordered measurement unit.
The switch 31 controlled switch controlling signal SW[1:0 that are formed on].According to switch controlling signal SW[1:0] value, switch 31 has four kinds of operator schemes.These four kinds of operator schemes are listed in table 1.
Table 1
In table 1, " x " representative unimportant (don ' t care).
Operator scheme 2 can be described as the inverse delayed pattern again.In operator scheme 2, switch controlling signal SW[1:0] be [0,1].Under this operator scheme, the input end of first phase inverter to 33a just leads after switch 31 is can be with input signal T_CK anti-phase.Similarly, delayed control signal D_SEL can determine the mistiming between output signal A_IN and test signal T_CK.
Operator scheme 3 can be described as external schema again.In operator scheme 3, switch controlling signal SW[1:0] be [1,0].Under this operator scheme, switch 31 can the input end of first phase inverter to 33a lead with external input signal D_EXT (being provided by automatic test machine platform 19).That is to say that under this operator scheme, output signal A_IN can be considered the address signal after the delay.Delayed control signal D_SEL can determine the mistiming between output signal A_IN and external input signal D_EXT.
Operator scheme 4 can be described as ring oscillator (ring oscillator) pattern again.In operator scheme 4, switch controlling signal SW[1:0] be [1,1].Under this operator scheme, switch 31 can make phase inverter that 33a-33d and impact damper INV9 are become a ring oscillator.That is switch 31 can be coupled to the input end of first phase inverter to 33a with the output terminal of impact damper INV9.
Each phase inverter is to comprising the phase inverter of a plurality of serial connections.Such as, phase inverter comprises the phase inverter INV1 and the INV2 of serial connection to 33a.Phase inverter comprises the phase inverter INV3 and the INV4 of serial connection to 33b.Phase inverter comprises the phase inverter INV5 and the INV6 of serial connection to 33c.Phase inverter comprises the phase inverter INV7 and the INV8 of serial connection to 33d.One of the input end that the right output terminal of each phase inverter can be coupled to multiplexer 32 input end right with the phase inverter of next stage.Each phase inverter postpones signal treating as delay circuit.
Impact damper INV9 can be used for improving the driving force of the right output signal of the phase inverter of afterbody.Signal RING_OUT is exported by impact damper INV9.
Suppose that frequency divider is the frequency divider (N is a positive integer) divided by N.When the sequential measuring unit is in operator scheme 4 (annular vibration) following time, the one-period of signal RING_OUT equals the resolution of twice.The resolution of time sequence measuring circuit can be expressed as: (1/2) * (1/N) * (1/R_OUT).R_OUT represents the frequency of the output signal R_OUT of frequency divider.
Fig. 4 a and 4b show the signal timing diagram according to the close beta signal of memory chip of the present invention.For simplicity, Fig. 4 a and 4b only demonstrate address pin A and the test signal A_IN of clock pin CK and the sequential chart of CK_IN that is applied to memory sub-system.
Fig. 4 a is shown in test signal A_IN when being used to measure setting-up time T_SETUP and the sequential chart of CK_IN.Shown in Fig. 4 a, for the operation of guaranteeing memory sub-system is correct, after test signal A_IN transition, to pass through setting-up time T_SETUP at least, test signal CK_IN could transition.Just, signal A_IN leads over signal CK_IN.In the present embodiment, still be down correct at the output data DO of memory sub-system, amount time delay by adjusting time-ordered measurement unit 21a or 21f obtains minimum setting-up time T_SETUP.
Fig. 4 b is shown in test signal A_IN when being used to measure retention time T_HOLD and the sequential chart of CK_IN.Shown in Fig. 4 b, for the operation of guaranteeing memory sub-system is correct, after test signal CK_IN transition, to pass through retention time T_HOLD at least, test signal A_IN could transition.Just, signal A_IN lags behind signal CK_IN.In the present embodiment, still be down correct at the output data DO of memory sub-system, amount time delay by adjusting time-ordered measurement unit 21a or 21f obtains minimum retention time T_HOLD.
In the prior art, test signal is produced and is delivered to memory chip to be measured by the automatic test machine platform of outside.So,, will have influence on accuracy of test if outside test signal has sequential change or error.In the present embodiment, test signal is produced by memory chip is inner, so can improve accuracy of test and raise the efficiency.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (13)
1. memory chip comprises:
One memory sub-system is used to store data, and it comprises a plurality of pins;
One clock trees is synchronously sent a testing source; And
One sequential metering circuit, this testing source that reception is sent by this clock trees, this time sequence measuring circuit distinctly postpones this testing source to produce a plurality of delays back test signal, test signal is delivered to the described pin of this memory sub-system after described the delay, and the storer of testing this memory sub-system by the sequential of adjusting described delay back testing source exchanges time sequence parameter.
2. memory chip as claimed in claim 1 more comprises:
One control circuit is used to control the operator scheme of this time sequence measuring circuit and the retardation of described delay back test signal.
3. memory chip as claimed in claim 1 more comprises:
One frequency divider, the ring oscillator output signal that reception and this time sequence measuring circuit of frequency division are exported.
4. memory chip as claimed in claim 3, wherein, when this time sequence measuring circuit comprises a plurality of time-ordered measurements unit, ring oscillator output signal of each time-ordered measurement unit output, a plurality of ring oscillator output signals of described time sequence measuring circuit are coupled to this frequency divider, and this memory chip more comprises:
One multiplexer is coupled to this frequency divider, in order to select one of described ring oscillator output signal of described time sequence measuring circuit.
5. memory chip as claimed in claim 1 more comprises:
One output data register receives an output data of this memory sub-system.
6. memory chip as claimed in claim 4, wherein, each time-ordered measurement unit is coupled to one of described pin of this memory sub-system.
7. memory chip as claimed in claim 6, wherein, each time-ordered measurement unit comprises:
One switch determines its operator scheme according to a switch controlling signal;
The delay circuit of a plurality of serial connections, an input end of each delay circuit are coupled to an output terminal of this switch or an output terminal of previous stage delay circuit, and the afterbody of described delay circuit is exported this ring oscillator output signal; And
One multiplexer receives a plurality of outputs of described delay circuit, and produces this delay back test signal this corresponding pin to this memory sub-system.
8. the time sequence measuring circuit of a memory chip, this memory chip comprises: a memory sub-system and the clock trees that a testing source is synchronously sent; This time sequence measuring circuit comprises:
A plurality of time-ordered measurements unit, each time-ordered measurement unit are coupled to one of a plurality of pins of this memory sub-system to measure the memory parameter of this memory sub-system; Each time-ordered measurement unit comprises:
One switch has: a control end, receive an external switch control signal, and one first end receives this testing source that this clock trees is sent, and one second end receives an external data, one the 3rd end, and one the 4th end;
The delay circuit of a plurality of serial connections, one input end of one first order delay circuit of described delay circuit is coupled to the 4th end of this switch, the afterbody of described delay circuit is exported a ring oscillator output signal, and this ring oscillator output signal is indicated a resolution of this time sequence measuring circuit; And
One multiplexer has: a control end receives an external delay control signal; A plurality of input ends are coupled to a plurality of output terminals of described delay circuit respectively; And an output terminal, be coupled to this corresponding pin of this memory sub-system;
Wherein, this external switch control signal is controlled the operator scheme of this time-ordered measurement unit, and this external delay control signal is controlled the mistiming between this output signal of this testing source and this multiplexer.
9. the method for testing of a storer, this method comprises:
Synchronously send a test signal;
Postpone this test signal respectively to produce a plurality of delays back test signal respectively, to input to a plurality of pins of this storer; And
Check that a output data that this storer exports is whether correct and described the delays back test signal of the described pin that inputs to this storer carried out the sequential adjustment, to measure an interchange time sequence parameter of this storer.
10. method as claimed in claim 9 more comprises:
In response to an external control signal, external testing data are delivered to this storer, to carry out functional test.
11. method as claimed in claim 10 more comprises:
In response to this external control signal, make the sequential measuring unit in this storer carry out an annular vibration, to measure a delay resolution.
12. method as claimed in claim 9 more comprises:
This delays back test signal that order inputs to an address pin of this storer is led over back test signal of this delay of a clock pin that inputs to this storer, to measure a setting-up time parameter.
13. method as claimed in claim 9 more comprises:
This delays back test signal that order inputs to an address pin of this storer lags behind back test signal of this delay of a clock pin that inputs to this storer, to measure a retention time parameter.
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| EP2481050A1 (en) * | 2009-09-23 | 2012-08-01 | Conor Maurice Ryan | A flash memory device and control method |
| EP2605855A4 (en) | 2010-08-20 | 2014-05-14 | Pieter Stroeve | Apparatus to manipulate colloidal particles in a bistable medium |
| JP6530216B2 (en) * | 2015-03-27 | 2019-06-12 | 株式会社メガチップス | Test circuit of semiconductor integrated circuit and test method using the same |
| CN106297897B (en) * | 2015-05-27 | 2019-07-30 | 华邦电子股份有限公司 | Storage unit and its test method |
| US9723631B2 (en) * | 2015-10-26 | 2017-08-01 | Microsoft Technology Licensing, Llc | Bulk fine timing measurement allocation message |
| CN115542131B (en) * | 2022-11-23 | 2023-03-10 | 北京紫光青藤微系统有限公司 | Chip testing method and circuit |
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| US6397312B1 (en) * | 1997-07-04 | 2002-05-28 | Fujitsu Limited | Memory subsystem operated in synchronism with a clock |
| CN1574628A (en) * | 2003-06-12 | 2005-02-02 | 安捷伦科技有限公司 | Method and apparatus for clock gating clock trees to reduce power dissipation |
| CN1734280A (en) * | 2004-08-09 | 2006-02-15 | 华为技术有限公司 | Time sequence test method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6397312B1 (en) * | 1997-07-04 | 2002-05-28 | Fujitsu Limited | Memory subsystem operated in synchronism with a clock |
| CN1574628A (en) * | 2003-06-12 | 2005-02-02 | 安捷伦科技有限公司 | Method and apparatus for clock gating clock trees to reduce power dissipation |
| CN1734280A (en) * | 2004-08-09 | 2006-02-15 | 华为技术有限公司 | Time sequence test method |
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