CN101369607B - Flash memory unit structure and preparation thereof - Google Patents
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- CN101369607B CN101369607B CN200710045015XA CN200710045015A CN101369607B CN 101369607 B CN101369607 B CN 101369607B CN 200710045015X A CN200710045015X A CN 200710045015XA CN 200710045015 A CN200710045015 A CN 200710045015A CN 101369607 B CN101369607 B CN 101369607B
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Abstract
A flash memory unit structure comprises a semiconductor substrate, a first dielectric layer positioned on the semiconductor substrate, an electric charge storage layer positioned on the first dielectric layer, a second dielectric layer positioned on the electric charge storage layer, and a grid positioned on a three-layer stacked structure composed of the first dielectric layer/ the electric charge storage layer/ the second dielectric layer, as well as a source and a drain positioned at the two sides of the three-layer stacked structure in the semiconductor substrate, wherein, the electric charge storage layer comprises a nonmetallic discrete atom island. The invention also provides a manufacturing method of the flash memory unit structure. The invention can effectively restrain drift of a threshold voltage, can improve the electric charge storage ability of the flash memory structure unit, and can avoid the problem of the pollution of metal ions caused by using a metal material.
Description
Technical field
The present invention relates to semiconductor device and preparation method thereof, particularly flash memory unit structure and preparation method thereof.
Background technology
Flash memory (Flash Memory) device is one of device that is widely used at present in the large scale integrated circuit field.Flush memory device has the function of storage data, and writing, read and erase operation of data can be provided as a kind of semiconductor memory, even cut off the electricity supply, the content of its storage does not disappear yet, and has the function of preserving data.The storage data function of flush memory device is to realize by the flash cell of inside.Flash cell is the storage area of data, and main part is the array of flash memory unit structure, and the corresponding binary numeral of each flash memory unit structure is used for storing " 0 " or " 1 ".By the flash cell that the flash memory unit structure with storage data function is formed, be one of core part of flush memory device.
The common flash memory unit structure of industry mainly contains " floating boom (Floating-Gate) structure " and " silica nitrogen-oxygen-silicon (SONOS) structure " two kinds at present.The both can satisfy the different flash array patterns and the needs of mode of operation, can keep the time data memory that reaches more than 10 years.
Along with the continuous development of integrated circuit technique, its integrated level improves constantly, and live width constantly reduces.For the flash memory unit structure below the 65nm node, because device size diminishes, especially grid length diminishes, various factors, approximate such as the drain electrode abrupt junction, influence becomes obvious all the more to the raceway groove modulating action, has therefore limited the further development of floating gate structure, and what replace then is the SONOS structure.
Existing SONOS structure and manufacture craft thereof are followed successively by bottom layer silicon dioxide 2, silicon nitride layer 3, top layer silicon dioxide 4 and grid 5 on Semiconductor substrate 1 surface as shown in Figure 1, and the both sides of grid 5 are source electrode 6 and drain electrode 7.Grid 5 is in order to apply driving voltage to the whole unit structure.Silicon nitride layer 3 adopts the method for chemical vapour deposition (CVD) to form, and the position is between top layer silicon dioxide 4 and bottom layer silicon dioxide 2.Interface between silicon nitride 3 and top layer silicon dioxide 4 and the bottom layer silicon dioxide 2 has charge trap, can play the effect of stored charge, is the stored charge layer in the flash memory structure.Bottom layer silicon dioxide 2 is the passage of charge charging and discharge, under the situation of no driving voltage, bottom layer silicon dioxide 2 can be blocked the migration of silicon nitride layer 3 charge stored to Semiconductor substrate 1 direction, but applying under the condition of certain bias voltage, electric charge just can enter into Semiconductor substrate 1 in the mode of tunnelling by bottom layer silicon dioxide 2, realizes programming, the erase operation of flash memory structure.Top layer silicon dioxide 4 is used for the conducting between block charge and the grid 5, avoids electric charge to the migration of grid 5 directions, operates by 4 pairs of silicon nitride layer 3 charge stored of top layer silicon dioxide in order to realize grid 5.
In following Chinese patent application 200410011656.X, can also find more information relevant with technique scheme, in manufacturing process, pass through optimal design to processing step, under the situation that does not increase process complexity and extra lithography step, can obtain high-quality SONOS structure.
Yet, find that in actual applications the threshold voltage of SONOS structure can produce the drift phenomenon of threshold voltage owing to be subjected to the influence of electric charge lateral transfer effect in the work of device, this has had a strong impact on the sensitivity of device.The stored charge layer adopts the nanocrystal of discrete distribution as charge storage structure, its material that adopts can be silicon, metal or some high dielectric constant material, the diameter of crystal grain is about a few nanometer to tens nanometers, and be in discrete each other discrete state, therefore can suppress the lateral transfer of electric charge effectively, the improvement threshold voltage drift.People such as K.Joo were published in article " the Novel transition layerengineered Si nano-crystal flash memory with MHSOS structure featuring largeV of International Electronics Device Meeting in 2005
ThWindows and fast P/E speed ", people such as Y.Lin was published in IEEE Trans onElectron Devices magazine 53 volume the 4th phase 782 pages article " Novel 2-bit HfO in 2006
2Nano-crystal nonvolatile flash memory " and people such as Y.Liu be published in IEEETrans on Electron Devices magazine 53 volume the 10th phase 2598 pages articles " Improvedperformance of SiGe nano-crystal memory with VARIOT tunnel barrier " in 2006, respectively to adopting nanocrystal to do detailed disclosure as the flash memory structure unit of charge storage structure.
This kind adopts the stored charge layer of nanocrystal, and the diameter of its charge storage and nanocrystal is closely related, and diameter is more little, and the ability of unit are stored electric charge is strong more.Adopt nanocrystalline charge storage structure as the flash memory structure unit, though can solve the threshold voltage shift problem, shortcoming is that crystallite dimension is big, the ability of stored charge is relatively poor.
Therefore, reach the purpose that improves charge storage efficient, just need further to reduce the size of crystal grain, make the crystal grain of the greater number that can distribute in the unit are, improve charge storage efficient.Adopt discrete atom island as charge storage structure, can improve charge storage efficient effectively.Discrete atom island as charge storage structure, the diameter of its diameter and single atom is in the same order of magnitude, the diameter of ratio nano crystalline substance hangs down one more than the quantity, therefore its technology of preparing is relatively more difficult, with the undersized discrete island structure of the very difficult realization of the means of traditional chemical deposition or physical deposition.In the prior art, a kind of technological means that forms discrete atom island is the ion injection method that adopts titanium or other metal materials, forms the atom island of discrete distribution, as charge storage layer.The article " Suppression of lateralcharge redistribution using advanced impurity trap memory for improving hightemperature retention " that people such as Hiroshi Sunamura delivered on the International Electronics Device Meeting in 2006 has at length disclosed the technical scheme that the method that adopts ion to inject forms the discrete atom island of metal.
Yet owing to adopt metal material to make discrete atom island, the employing of metal ion can make the preceding road processing step in the integrated circuit technology flow process be subjected to the pollution of metal ion.Metal ion in the semiconductor technology stains, may badly influence the material surface evenness, may in semiconductor energy gap, introduce dark electron energy level, thereby have influence on semi-conductive carrier mobility and conductivity, may have influence on the dielectric property of dielectric material.Therefore, adopt the discrete atom island of metal material, had a strong impact on the performance of semiconductor device and integrated circuit, thereby cause the yield of production line to descend.
In sum, in the prior art, the SONOS structure can produce the drift phenomenon of threshold voltage in the work of device, influenced its further application; Adopt nanocrystalline charge storage structure as the flash memory structure unit, though can solve the threshold voltage shift problem, shortcoming is that crystallite dimension is big, the ability of stored charge is relatively poor; The discrete atom island of adopting the metal material making is as charge storage structure, and the ability of stored charge is better than nanocrystalline, also can avoid the problem of threshold voltage shift, but can bring metal ion pollution.
Summary of the invention
Technical problem to be solved by this invention provides and a kind ofly both can solve threshold voltage shift, has again than forceful electric power lotus storage capacity, and can avoid flash memory unit structure that metal ion stains and preparation method thereof.
In order to address the above problem, the invention provides a kind of flash memory unit structure, comprise Semiconductor substrate, be positioned at first dielectric layer on the Semiconductor substrate, be positioned at the stored charge layer on first dielectric layer, be positioned at second dielectric layer on the stored charge layer, with the structural grid of three level stack that is positioned at by first dielectric layer/stored charge layer/second dielectric layer is formed, and the source electrode and the drain electrode that are positioned at three level stack structure both sides in the Semiconductor substrate, described stored charge layer includes nonmetal discrete atom island.
The material on optionally, described nonmetal discrete atom island is silicon nitride, silica, silicon oxynitride or silicon.
Optionally, the diameter on described nonmetal discrete atom island is 3 dusts～20 dusts.
The present invention also provides a kind of manufacture method of flash memory unit structure, comprising: form first dielectric layer on Semiconductor substrate; On first dielectric layer, form the stored charge layer, include nonmetal discrete atom island; On the stored charge layer, form second dielectric layer; Annealing; Both sides in the three level stack structure of being made up of first dielectric layer/stored charge layer/second dielectric layer form source electrode and drain electrode; On the three level stack structure, form grid.
The material on optionally, described nonmetal discrete atom island is silicon nitride, silica, silicon oxynitride or silicon.
The method on the nonmetal discrete atom of optionally, described formation island is an atomic layer deposition method.
Optionally, described atomic layer deposition method comprises: earlier first precursor gases is flowed to first dielectric layer of the semiconductor substrate surface in the atomic layer deposition chamber, form the first discrete individual layer on first dielectric layer; The inert purge gas direction of flow is in the indoor Semiconductor substrate of ald; Second precursor gases flows to atomic layer deposition chamber, and first precursor gases reaction with forming first individual layer forms nonmetal discrete atom island; Inert purge gas direction of flow atomic layer deposition chamber.
Optionally, the first described precursor gases is SiH
4, Si (OC
2H
5)
4, SiH
2[NH (C
4H
9)]
2, SiH (OC
2H
5)
3, Si
2Cl
6Or SiHN[(CH
3)
2]
3
Optionally, described first precursor gases is SiH
4The time, the flow that first precursor gases flows on first dielectric layer in the atomic layer deposition chamber is 0.1slm～1.0slm, 1 second～10 seconds inlet time, and 0.9 kPa～1 kPa of the indoor pressure of ald, temperature is 400 ℃～550 ℃,
Optionally, described second precursor gases is NH
3, N
2O, N
2, O
2, O
3Perhaps H
2O.
Optionally, described inert purge gas is He, Ne or Ar.
The diameter on optionally, described nonmetal discrete atom island is 3 dusts～20 dusts.
Optionally, the required gas of described annealing is nitrogen, He, Ne or Ar.
Optionally, annealing temperature is 850 ℃～1000 ℃.
Optionally, annealing time is 10 minutes～60 minutes.
Compared with prior art, flash memory unit structure of above technical scheme narration and preparation method thereof adopts nonmetal discrete atom island as charge storage structure, has following advantage:
(1) the lateral transfer effect of electric charge in the SONOS structure can be avoided in nonmetal discrete atom island, therefore can suppress the drift of threshold voltage effectively.
(2) can avoid adopting nanocrystalline as charge storage structure because the relatively poor problem of ability of the big stored charge that brings of crystallite dimension.
(3) can avoid adopting metal material to make nonmetal discrete atom island, preceding road technology be produced the problem that ion stains owing to what the employing of metal brought.
Description of drawings
Fig. 1 is existing flash memory unit structure schematic diagram;
Fig. 2 is the schematic diagram of the described flash memory unit structure of first embodiment of the invention;
Fig. 3 is the implementing procedure figure of the described flash memory unit structure manufacture method of second embodiment of the invention;
Fig. 4 to Fig. 8 is the implementation step schematic diagram of the described flash memory unit structure manufacture method of second embodiment of the invention.
Embodiment
Flash memory unit structure provided by the invention adopts nonmetal discrete atom island as charge storage structure, has than forceful electric power lotus storage capacity, both can solve threshold voltage shift, can avoid metal ion to stain again.
The method of the employing ald of the manufacture method of the flash memory unit structure that present embodiment provides realizes the making on nonmetal discrete atom island.Existing employing method for implanting forms the technology on discrete atom island, can only adopt metal ion, and nonmetallic ion is difficult for quickening because atomic mass is big, and the nucleation difficulty, therefore can't be used for above-mentioned technology.This law is bright in the process of making discrete atom island, utilizes the method for ald, can realize adopting nonmetallic materials to make discrete atom island, has avoided the contamination problem that adopts the discrete atom island of metal to cause.Traditional atom layer deposition process is used to deposit the continuous films structure, the invention provides a kind of new atomic layer deposition technology, can realize discrete atom island but not the making of continuous film.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Embodiment one
Present embodiment provides a kind of flash memory unit structure.With reference to the accompanying drawings shown in 2, comprise Semiconductor substrate 101, be positioned at first dielectric layer 102 on the Semiconductor substrate 101, be positioned at stored charge layer 103 on first dielectric layer 102, be positioned at second dielectric layer 105 on the stored charge layer 103, be positioned at " first dielectric layer, 102/ stored charge layer, 103/ second dielectric layer 105 " the structural grid 106 of three level stack and Semiconductor substrate 101 is positioned at the source electrode 107 and the drain electrode 108 of the three level stack structure both sides of " first dielectric layer, 102/ stored charge layer, 103/ second dielectric layer 105 ".Described stored charge layer 103 includes nonmetal discrete atom island 104.
In this example, described Semiconductor substrate 101 can be the various semi-conducting materials that the semiconductor applications technical staff knows, the silicon or the SiGe (SiGe) that comprise monocrystalline or polycrystalline structure, can also be to contain for example silicon or the SiGe that mix of N type or P type of dopant ion, also can comprise compound semiconductor structure, for example carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs, gallium antimonide, gallium nitride, aluminium nitride, indium nitride alloy semiconductor or its combination; It also can be silicon-on-insulator (SOI); Also can be strained silicon, stress SiGe or other strain gauge materials.Described Semiconductor substrate can be blank semiconductive material substrate, also can be the Semiconductor substrate that has formed various semiconductor structures, device and circuit.
In this example, the material of described first dielectric layer 102 is the silica (Coral of silicate glass layer (FSG), silane sesquichloride (HSQ) and the carbon dope of silica, silicon nitride, silicon oxynitride, aluminium oxide, tantalum oxide, scandium oxide, hafnium oxide, fluoridize
TM, Black Diamond) etc. inorganic material or organic material or their combinations such as poly aromatic alkene ether (Flare), aromatic hydrocarbons (SILK) and dimethylbenzene plastics.
In this example, the thickness of described first dielectric layer 102 is 1 nanometer～15 nanometers, and concrete thickness is 1 nanometer, 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, 10 nanometers, 11 nanometers, 12 nanometers, 13 nanometers, 14 nanometers or 15 nanometers etc. for example.
In this example, described first dielectric layer 102 is as the bottom medium, the main present flash memory unit structure of acting body programme and the process of erase operation in, as the passage of charge migration; Be at flash memory unit structure under the state of signal maintenance, can between stored charge layer 103 and Semiconductor substrate 101, realize the insulation isolation, guarantee that flash memory unit structure still can keep its intrinsic signal after operation level disappears.
In this example, the material on described nonmetal discrete atom island 104 is the silicon nitride of silicon nitride, silica, silicon oxynitride, silicon, Silicon-rich, the silica of Silicon-rich or the nonmetallic materials such as silicon oxynitride of Silicon-rich.Adopt nonmetallic materials can avoid the pollution of metal ion, improve transistorized rate of finished products semiconductor technology.The dangling bonds density that silicon nitride dielectric constant height, surface are used for stored charge is big, relatively is suitable as the material on nonmetal discrete atom island.Silica and silicon are the modal materials of present semicon industry, prepare simple, with low cost, process stabilizing, therefore also can be as the material on nonmetal discrete atom island.The nonmetallic materials of the Silicon-rich such as silicon oxynitride of the silicon nitride of employing Silicon-rich, the silica of Silicon-rich or Silicon-rich, because the material structure of its Silicon-rich, the surface on nonmetal discrete atom island has bigger suspension and hangs key density, therefore the density height of stored charge can improve the charge storage efficient on nonmetal discrete atom island.
In this example, described nonmetal discrete atom island 104 is present in the stored charge layer 103, and is in released state between island and the island.Separating between island and the island, can suppress electric charge and move along the horizontal direction of stored charge layer, this migration effect can cause threshold voltage shift.Released state between island and the island helps reducing the drift of threshold voltage.
In this example, when described nonmetal discrete atom island 104 was the silicon nitride of Silicon-rich, the ratio of silicon and nitrogen-atoms number was 3: 4～3: 0, concrete ratio for example 3: 4,3: 3.5,3: 3,3: 2.5,3: 2,3: 1.5,3; 1,3: 0.5 or 3: 0 etc.
In this example, when described nonmetal discrete atom island 104 is the silica of Silicon-rich, the ratio of silicon and oxygen atomicity is 1: 2～1: 0, concrete ratio for example 1: 2.0,1: 1.8,1: 6,1: 1.4,1: 1.2,1: 1.0,1: 0.8,1: 0.6,1: 0.4,1: 0.2 or 1: 0 etc.
In this example; the diameter on described nonmetal discrete atom island 104 is 3 dusts～20 dusts, and concrete diameter is 3 dusts, 4 dusts, 5 dusts, 6 dusts, 7 dusts, 8 dusts, 9 dusts, 10 dusts, 11 dusts, 12 dusts, 13 dusts, 14 dusts, 15 dusts, 16 dusts, 17 dusts, 18 dusts, 19 dusts or 20 dusts etc. for example.
Nonmetal discrete atom island 104 is used to realize the function of charge storage in flash memory unit structure.The influence that nonmetal discrete atom island 104 can avoid the lateral transfer of electric charge that threshold voltage is caused; Adopt nonmetal discrete atom island 104, the hovering that can increase surface, atom island is hung chemical bond density, thereby increases the number of charge trap in the unit are, has higher charge storage efficient; The material that adopt on nonmetal discrete atom island 104 is nonmetallic materials such as silicon nitride or silica, has avoided the contamination of metal ion.
In this example, the material of described second dielectric layer 105 is inorganic material or the organic material or their combinations such as poly aromatic alkene ether, aromatic hydrocarbons and dimethylbenzene plastics such as silica of silicate glass layer, silane sesquichloride and the carbon dope of silica, silicon nitride, silicon oxynitride, aluminium oxide, tantalum oxide, scandium oxide, hafnium oxide, fluoridize.
In this example, the thickness of described second dielectric layer 105 is 4 nanometers～30 nanometers, and concrete thickness is 4 nanometers, 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, 10 nanometers, 11 nanometers, 12 nanometers, 13 nanometers, 14 nanometers, 15 nanometers, 16 nanometers, 17 nanometers, 18 nanometers, 19 nanometers, 20 nanometers, 21 nanometers, 22 nanometers, 23 nanometers, 24 nanometers, 25 nanometers, 26 nanometers, 27 nanometers, 28 nanometers, 29 nanometers or 30 nanometers etc. for example.
In this example, described source electrode 107 and drain electrode 108 are positioned at the Semiconductor substrate 101 of the three level stack structure both sides of " first dielectric layer, 102/ stored charge layer, 103/ second dielectric layer 105 ".
In this example, described source electrode 107 and drain electrode 108, their position can exchange.
In this example, the material of described grid 106 can be the silicon or the germanium silicon of monocrystalline or polycrystalline, also can be that the silicon of the monocrystalline that mixes of N type or P type or polycrystalline or germanium silicon also can make be copper, aluminium, gold, platinum, nickel, titanium, tin, silver or other metals in a kind of, also can be their combination.
Embodiment two
Present embodiment provides a kind of manufacture method of flash memory unit structure.Implementing procedure figure shown in 3 with reference to the accompanying drawings.Step S201 forms first dielectric layer on Semiconductor substrate; Step S202 forms the stored charge layer on first dielectric layer, include nonmetal discrete atom island; Step S203 forms second dielectric layer on the stored charge layer; Step S204, annealing; Step S205 forms source electrode and drain electrode in the both sides of the three level stack structure of being made up of first dielectric layer/stored charge layer/second dielectric layer; Step S206 forms grid on the three level stack structure.
Fig. 4 to Fig. 8 is the example structure schematic diagram that the present invention forms flash memory unit structure.As shown in Figure 4, on Semiconductor substrate 201, form first dielectric layer 202.
In this example, refer step S201, described Semiconductor substrate 201 can be the various semi-conducting materials that the semiconductor applications technical staff knows, the silicon or the SiGe that comprise monocrystalline or polycrystalline structure, can also be to contain for example silicon or the SiGe that mix of N type or P type of dopant ion, also can comprise compound semiconductor structure, for example carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs, gallium antimonide, gallium nitride, aluminium nitride, indium nitride alloy semiconductor or its combination; It also can be silicon-on-insulator; Also can be strained silicon, stress SiGe or other strain gauge materials.Described Semiconductor substrate can be blank semiconductive material substrate, also can be the Semiconductor substrate that has formed various semiconductor structures, device and circuit.
In this example, continue refer step S201, the material of described first dielectric layer 202 is inorganic material or the organic material or their combinations such as poly aromatic alkene ether, aromatic hydrocarbons and dimethylbenzene plastics such as silica of silicate glass layer, silane sesquichloride and the carbon dope of silica, silicon nitride, silicon oxynitride, aluminium oxide, tantalum oxide, scandium oxide, hafnium oxide, fluoridize.
In this example, continue refer step S201, the formation method of described first dielectric layer 202 is chemical vapour deposition technique, physical deposition method, magnetron sputtering method, thermal evaporation, electron-beam vapor deposition method, vacuum magnetic filtered arc sedimentation, ion beam assisted depositing method, laser assistant depositing method, thermal oxidation method, plasma ion assisted deposition method or their combination.
In this example, if refer step S201 during the formation method thermal oxidation method of the first described dielectric layer 202, can adopt dry method thermal oxidation, means of wet thermal oxidation or their combination.
In this example, continue refer step S201, the thickness of described first dielectric layer 202 is 1 nanometer～15 nanometers, and concrete thickness is 1 nanometer, 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, 10 nanometers, 11 nanometers, 12 nanometers, 13 nanometers, 14 nanometers or 15 nanometers etc. for example.
As shown in Figure 5, on first dielectric layer 202, form stored charge layer 203, include nonmetal discrete atom island 204.
In this example, refer step S202, the material on described nonmetal discrete atom island 204 is the silicon nitride of silicon nitride, silica, silicon oxynitride, silicon, Silicon-rich, the silica of Silicon-rich or the nonmetallic materials such as silicon oxynitride of Silicon-rich.
In this example, continue refer step S202, described nonmetal discrete atom island 204 is present in the stored charge layer 203, and is in released state between island and the island.
In this example, continue refer step S202, when described nonmetal discrete atom island 204 was the silicon nitride of Silicon-rich, the ratio of silicon and nitrogen-atoms number was 3: 4～3: 0, concrete ratio for example 3: 4,3: 3.5,3: 3,3: 2.5,3: 2,3: 1.5,3: 1,3: 0.5 or 3: 0 etc.
In this example, continue refer step S202, when described nonmetal discrete atom island 204 was the silica of Silicon-rich, the ratio of silicon and oxygen atomicity was 1: 2～1: 0, concrete ratio for example 1: 2.0,1: 1.8,1: 6,1: 1.4,1: 1.2,1: 1.0,1: 0.8,1: 0.6,1; 0.4,1: 0.2 or 1: 0 etc.
In this example; continue refer step S202; the diameter on described nonmetal discrete atom island 204 is 3 dusts～20 dusts, and concrete diameter is 3 dusts, 4 dusts, 5 dusts, 6 dusts, 7 dusts, 8 dusts, 9 dusts, 10 dusts, 11 dusts, 12 dusts, 13 dusts, 14 dusts, 15 dusts, 16 dusts, 17 dusts, 18 dusts, 19 dusts or 20 dusts etc. for example.
In this example, continue refer step S202, the method preparation of ald is adopted on described nonmetal discrete atom island 204.
Existing employing method for implanting forms the technology on discrete atom island, can only adopt metal ion, and nonmetallic ion is difficult for quickening because atomic mass is big, and the nucleation difficulty, therefore can't be used for above-mentioned technology.Refer step S202 utilizes the method for ald in the process of making discrete atom island 204, can realize adopting nonmetallic materials to make discrete atom island, has avoided the contamination problem that adopts the discrete atom island of metal to cause.
Traditional atom layer deposition process, be used to deposit the continuous films structure, the atomic layer deposition technology that refer step S202 provides is by adjusting flow, the flushing time of gas, and the temperature of reative cell, pressure and other parameters, can realize discrete atom island but not the making of continuous film.
The method of described ald comprises: earlier first precursor gases is flowed to first dielectric layer of the semiconductor substrate surface in the atomic layer deposition chamber, form the first discrete individual layer on first dielectric layer; The inert purge gas direction of flow is in the indoor Semiconductor substrate of ald; Second precursor gases flows to atomic layer deposition chamber, and first precursor gases reaction with forming first individual layer forms nonmetal discrete atom island; Inert purge gas direction of flow atomic layer deposition chamber.
In this example, continue refer step S202, the method for described ald, first precursor gases is SiH
4, Si (OC
2H
5)
4, SiH
2[NH (C
4H
9)]
2, SiH (OC
2H
5)
3, Si
2Cl
6Or SiHN[(CH
3)
2]
3
In this example, continue refer step S202, the method for described ald, described first precursor gases is SiH
4The time, the flow that first precursor gases flows on first dielectric layer in the atomic layer deposition chamber is 0.1slm～1.0slm, and concrete flow is 0.1slm, 0.2slm, 0.3slm, 0.4slm, 0.5slm, 0.6slm, 0.7slm, 0.8slm, 0.9slm or 1.0slm for example.
In this example, continue refer step S202, first precursor gases that described Atomic layer deposition method adopted is SiH
4The time, first precursor gases flows to 1 second～10 seconds inlet time on first dielectric layer in the atomic layer deposition chamber, concrete for example 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds, 6 seconds, 7 seconds, 8 seconds, 9 seconds or the 10 seconds time.
In this example, continue refer step S202, the method for described ald is when first precursor gases is SiH
4The time, 0.9 kPa～1 kPa of the indoor pressure of ald, for example 0.9 kPa, 0.91 kPa, 0.92 kPa, 0.93 kPa, 0.94 kPa, 0.95 kPa, 0.96 kPa, 0.97 kPa, 0.98 kPa, 0.99 kPa or 1 kPa of concrete pressure.
In this example, continue refer step S202, the method for described ald is when first precursor gases is SiH
4The time, the indoor temperature of ald is 400 ℃～550 ℃, for example 400 ℃, 410 ℃, 420 ℃, 430 ℃, 440 ℃, 450 ℃, 460 ℃, 470 ℃, 480 ℃, 490 ℃ or 500 ℃ of actual temps.
In this example, continue refer step S202, described second precursor gases is NH
3, N
2O, N
2, O
2, O
3Perhaps H
2O.
In this example, continue refer step S202, the method for described ald, inert purge gas is He, Ne or Ar.
As shown in Figure 6, on stored charge layer 203, form second dielectric layer 205.
In this example, refer step S203, the formation method of described second dielectric layer 205 is chemical vapour deposition technique, physical deposition method, magnetron sputtering method, thermal evaporation, electron-beam vapor deposition method, vacuum magnetic filtered arc sedimentation, ion beam assisted depositing method, laser assistant depositing method, plasma ion assisted deposition method or their combination.
In this example, continue refer step S203, the material of described second dielectric layer 205 is inorganic material or the organic material or their combinations such as poly aromatic alkene ether, aromatic hydrocarbons and dimethylbenzene plastics such as silica of silicate glass layer, silane sesquichloride and the carbon dope of silica, silicon nitride, silicon oxynitride, aluminium oxide, tantalum oxide, scandium oxide, hafnium oxide, fluoridize.
In this example, continue refer step S203, the thickness of described second dielectric layer 205 is 4 nanometers～30 nanometers, and concrete thickness is 4 nanometers, 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, 10 nanometers, 11 nanometers, 12 nanometers, 13 nanometers, 14 nanometers, 15 nanometers, 16 nanometers, 17 nanometers, 18 nanometers, 19 nanometers, 20 nanometers, 21 nanometers, 22 nanometers, 23 nanometers, 24 nanometers, 25 nanometers, 26 nanometers, 27 nanometers, 28 nanometers, 29 nanometers or 30 nanometers etc. for example.
In this example, refer step S204, the required gas of described annealing is nitrogen, He, Ne or Ar etc.
In this example, continue refer step S204, described annealing temperature is 800 ℃～950 ℃, for example 800 ℃, 810 ℃, 820 ℃, 830 ℃, 840 ℃, 850 ℃, 860 ℃, 870 ℃, 880 ℃, 890 ℃, 900 ℃, 910 ℃, 920 ℃, 930 ℃, 940 ℃ of actual temps or 950 ℃ etc.
In this example, continue refer step S204, described annealing time is 10 minutes～60 minutes, concrete for example 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes time or 60 minutes etc.
As shown in Figure 7, form source electrode 206 and drain electrode 207 in the both sides of the three level stack structure of forming by first dielectric layer, 202/ stored charge layer, 203/ second dielectric layer 205.
In this example, refer step S205, described source electrode and drain electrode can adopt the method for dry etching or wet etching to form.
In this example, continue refer step S205, described source electrode 206 and drain electrode 207 are positioned at the Semiconductor substrate 201 of the three level stack structure both sides of " first dielectric layer, 202/ stored charge layer, 203/ second dielectric layer 205 ", mix other elements by ion injection, diffusion or other method, change the conduction type of source electrode 206 and drain electrode 207, make its conductivity type opposite with Semiconductor substrate 201.
In this example, continue refer step S205, described source electrode 206 and drain electrode 207, their position can exchange.
In this example, continue refer step S205, described source electrode 206 and drain electrode 207, when substrate 201 was the Semiconductor substrate of P type for conduction types such as P type silicon substrate, P type SOI substrate or P type strained silicon substrate, its doping element can be a kind of in boron, aluminium, gallium, the indium or their combination.
In this example, continue refer step S205, described source electrode 206 and drain electrode 207, when substrate 201 was the Semiconductor substrate of N type for conduction types such as N type silicon substrate, N type SOI substrate or N type strained silicon substrate, its doping element can be a kind of in nitrogen, phosphorus, arsenic, the antimony or their combination.
As shown in Figure 8, on the three level stack structure, form grid 208.
In this example, refer step S206, the material of described grid 208 can be the silicon or the germanium silicon of monocrystalline or polycrystalline, also can be that the silicon of the monocrystalline that mixes of N type or P type or polycrystalline or germanium silicon also can make be copper, aluminium, gold, platinum, nickel, titanium, tin, silver or other metals in a kind of, also can be their combination.
In this example, continue refer step S206, the formation method of described grid 208 is chemical vapour deposition technique, physical deposition method, magnetron sputtering method, thermal evaporation, electron-beam vapor deposition method, vacuum magnetic filtered arc sedimentation, ion beam assisted depositing method, laser assistant depositing method, plasma ion assisted deposition method or their combination.
Flash memory unit structure that above embodiment provided and preparation method thereof, adopt the charge storage structure of nonmetal discrete atom island as flash memory unit structure, can avoid the lateral transfer effect of electric charge in the SONOS structure, therefore can suppress the drift of threshold voltage effectively; Can avoid adopting nanocrystalline as charge storage structure because the relatively poor problem of ability of the big stored charge that brings of crystallite dimension; Can avoid adopting metal material to make nonmetal discrete atom island, preceding road technology be produced the problem that ion stains owing to what the employing of metal brought.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (16)
1. flash memory unit structure, comprise Semiconductor substrate, be positioned at first dielectric layer on the Semiconductor substrate, be positioned at the stored charge layer on first dielectric layer, be positioned at second dielectric layer on the stored charge layer, with the structural grid of three level stack that is positioned at by first dielectric layer/stored charge layer/second dielectric layer is formed, and the source electrode and the drain electrode that are positioned at three level stack structure both sides in the Semiconductor substrate, it is characterized in that, described stored charge layer includes nonmetal discrete atom island, and the material on described nonmetal discrete atom island is a silicon nitride, silica, silicon oxynitride or silicon.
2. the flash memory unit structure according to claim 1 is characterized in that: the diameter on described nonmetal discrete atom island is 3 dusts～20 dusts.
3. the manufacture method of a flash memory unit structure is characterized in that, comprises the following steps:
On Semiconductor substrate, form first dielectric layer;
Form the stored charge layer on first dielectric layer, include nonmetal discrete atom island, the material on described nonmetal discrete atom island is silicon nitride, silica, silicon oxynitride or silicon;
On the stored charge layer, form second dielectric layer;
Annealing;
Both sides in the three level stack structure of being made up of first dielectric layer/stored charge layer/second dielectric layer form source electrode and drain electrode;
On the three level stack structure, form grid.
4. according to the manufacture method of the described flash memory unit structure of claim 3, it is characterized in that: the diameter on described nonmetal discrete atom island is 3 dusts～20 dusts.
5. according to the manufacture method of the described flash memory unit structure of claim 3, it is characterized in that: the method that forms nonmetal discrete atom island is an atomic layer deposition method.
6. according to the manufacture method of the described flash memory unit structure of claim 5, it is characterized in that: described atomic layer deposition method comprises: earlier first precursor gases is flowed to first dielectric layer of the semiconductor substrate surface in the atomic layer deposition chamber, form the first discrete individual layer on first dielectric layer; The inert purge gas direction of flow is in the indoor Semiconductor substrate of ald; Second precursor gases flows to atomic layer deposition chamber, and first precursor gases reaction with forming first individual layer forms nonmetal discrete atom island; Inert purge gas direction of flow atomic layer deposition chamber.
7. according to the manufacture method of the described flash memory unit structure of claim 6, it is characterized in that: described first precursor gases is SiH
4, Si (OC
2H
5)
4, SiH
2[NH (C
4H
9)]
2, SiH (OC
2H
5)
3, Si
2Cl
6Or SiHN[(CH
3)
2]
3
8. according to the manufacture method of claim 6 or 7 described flash memory unit structures, it is characterized in that: described first precursor gases is SiH
4The time, the flow that first precursor gases flows on first dielectric layer in the atomic layer deposition chamber is 0.1slm～1.0slm.
9. according to the manufacture method of claim 6 or 7 described flash memory unit structures, it is characterized in that: described first precursor gases is SiH
4The time, first precursor gases flows to 1 second～10 seconds inlet time on first dielectric layer in the atomic layer deposition chamber.
10. according to the manufacture method of claim 6 or 7 described flash memory unit structures, it is characterized in that: when first precursor gases is SiH
4The time, 0.9 kPa～1 kPa of the indoor pressure of ald.
11. the manufacture method according to claim 6 or 7 described flash memory unit structures is characterized in that: when first precursor gases is SiH
4The time, the indoor temperature of ald is 400 ℃～550 ℃.
12. the manufacture method according to the described flash memory unit structure of claim 6 is characterized in that: described second precursor gases is NH
3, N
2O, N
2, O
2, O
3Perhaps H
2O.
13. the manufacture method according to the described flash memory unit structure of claim 6 is characterized in that: described inert purge gas is He, Ne or Ar.
14. the manufacture method according to the described flash memory unit structure of claim 3 is characterized in that: the required gas of described annealing is nitrogen, He, Ne or Ar.
15. the manufacture method according to the described flash memory unit structure of claim 3 is characterized in that: annealing temperature is 800 ℃～950 ℃.
16. according to the manufacture method of claim 3 or 14 or 15 described flash memory unit structures, it is characterized in that: annealing time is 10 minutes～60 minutes.
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