CN101359644B - Integrated circuit package structure - Google Patents
Integrated circuit package structure Download PDFInfo
- Publication number
- CN101359644B CN101359644B CN 200810120426 CN200810120426A CN101359644B CN 101359644 B CN101359644 B CN 101359644B CN 200810120426 CN200810120426 CN 200810120426 CN 200810120426 A CN200810120426 A CN 200810120426A CN 101359644 B CN101359644 B CN 101359644B
- Authority
- CN
- China
- Prior art keywords
- connection pad
- pin
- support plate
- chip support
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to an integrated circuit package structure which is applied in the technical field of high-power integrated circuit encapsulation. The integrated circuit package structure comprises a lead frame and a packaging colloid. A chip carrier is arranged at the middle of the lead frame and a plurality of pins are arranged around the chip carrier; a chip is fixed on the chip carrier and an electric joint area for the pins is arranged above the chip carrier; and a connection pad element is arranged between the pins and the chip carrier, in the projection of the corresponding electric connection point area on the chip carrier. The electric connection point area and the connection pad element, and the connection pad element and the chip carrier are both in non-clearance contact, thus ensuring the reliability of the contacts on the pins at the time of electric connection process of the products in package so as to improve yield and reliability of the products.
Description
Technical field
The present invention relates to a kind of integrated circuit package structure, be meant that particularly a kind of pin layer is parallel with the chip support plate layer, and the upright projection of the electrical wiring joining zone of pin layer is positioned at the encapsulating structure of chip support plate layer plane, is applied in the high-power integrated circuit encapsulation technology.
Background technology
Along with the application of integrated circuit is extensive day by day, improving constantly of microelectronics Packaging (Packaging), high-power encapsulation technology seen a kind of high-power integrated circuit method for packing of novelty is used gradually more.Its principal character is the top of pin perpendicular to chip support plate, and the upright projection at pin electrical wiring contact position is positioned at the chip support plate layer plane.This encapsulating structure can increase effective heat-conducting area of pin, has reduced the thermal resistance of circuit, and realizes the microminiaturized purpose of integrated circuit encapsulation.But a shortcoming of this encapsulating structure is that electrical wiring adds man-hour, and is unsettled above chip support plate because of the contact position of pin, makes to add man-hour pin contact position and can not compacting fix, and easily floating makes the processing of electrical wiring contact unreliable, causes and opens circuit.Even or utilize the elasticity of pin that the electrical wiring contact position of pin is pressed on the chip support plate, but because of the safe distance between pin and chip support plate, can make the electrical wiring joining zone surface of pin produce an oblique angle, thereby make the decrease in yield of electrical wiring processing with the chip support plate plane.
Summary of the invention
At the existing problem of above-mentioned existing encapsulating structure, purpose of the present invention just provides a kind of qualification rate integrated circuit package structure reliable, product of processing.
According to above-mentioned purpose, the technical scheme that the present invention takes is, a kind of integrated circuit package structure, comprise lead frame and packing colloid, in the middle of the lead frame is a chip support plate, be provided with number of pins around the chip support plate, chip is fixed on the chip support plate, above chip support plate, form the electric connection point district of pin, it is characterized in that: between pin and chip support plate, be provided with the connection pad element, the connection pad element places on the chip support plate corresponding electric connection point district projected position, between electric connection point district and the connection pad element, and contacts for no gap between connection pad element and the chip support plate.
The further setting of the present invention is:
The connection pad element adopts insulating material high temperature resistant, hard to make.
The connection pad element comprises connection pad base and connection pad boss, the connection pad base is arranged between pin and the chip support plate, between electric connection point district and the connection pad base, and contact for no gap between connection pad base and the chip support plate, the connection pad boss extends to outstanding pin end face to pin end face direction.
The connection pad boss preferably exceeds 0.3～0.8 millimeter of pin end face.
The shape of connection pad boss is identical with the shape in pin gap.
Leave 0.1～0.2 mm clearance between connection pad boss and pin.
Beneficial effect of the present invention is: by the insulation connection pad element of a plurality of high temperature resistant, hard is set between pin and chip support plate, so that the electric connection point region surface of pin and chip support plate plane parallel, thereby help the electrical wiring processing between pin and the chip, improve reliability and rate of finished products.Can improve in the high-power encapsulating structure, pin contact position can not be fixed in compacting, easily floating opens circuit unreliable the causing of electrical wiring contact processing, and the electrical wiring joining zone of pin is surperficial and the chip support plate plane produces an oblique angle, thereby makes the problem of the decrease in yield of electrical wiring processing.
Further understand for allowing state with other purposes, feature, advantage on the present invention, now be described in detail as follows with embodiment in conjunction with the accompanying drawings:
Description of drawings
Fig. 1 is the overall schematic of integrated circuit package structure of the present invention;
Fig. 2 is the internal structure schematic diagram of the embodiment of the invention;
Fig. 3 is A-A cutaway view of Fig. 2;
Fig. 4 is the partial enlarged drawing of Fig. 2;
Fig. 5 is the structural representation of connection pad element of the present invention;
Number in the figure:
10 lead frames; 11 chip support plates; 12 pins; 13 electric connection point districts; 20 connection pad elements; 21 connection pad bases; 22 connection pad boss; 30 chips; 40 packing colloids
Embodiment
As Fig. 1, Fig. 2, shown in Figure 3, the present invention includes lead frame 10 and packing colloid 40, in the middle of the lead frame 10 is a chip support plate 11, be provided with number of pins 12 around the chip support plate 11, chip 30 is fixed on the chip support plate 11 in the bonding mode of solder, above chip support plate 11, form the electric connection point district 13 of pin 12, between pin 12 and chip support plate 11, be provided with connection pad element 20, connection pad element 20 adopts high temperature resistant, the insulating material of hard is made, connection pad element 20 places pin electric connection point district 13 projected positions corresponding on the chip support plate 11, between pin electric connection point district 13 and the connection pad element 20, and contact for no gap between connection pad element 20 and the chip support plate 11.
With reference to shown in Figure 4, connection pad element 20 comprises the connection pad base 21 and the connection pad boss 22 that are arranged between pin 12 and the chip support plate 11, connection pad base 21 in-scopes have comprised pin electric connection point district 13, between pin electric connection point district 13 and the connection pad base 21, and contact for no gap between connection pad base 21 and the chip support plate 11.The connection pad boss 22 of connection pad element 20 extends to outstanding pin 12 end faces to pin 12 end face directions, and usually, connection pad boss 22 exceeds pin 12 end faces and is advisable for 0.3 to 0.8 millimeter.The shape of connection pad boss 22 is consistent with gap shape between the pin 12, and leaves 0.1 to 0.2 mm clearance.In conjunction with shown in Figure 5, opposition was arranged on chip support plate 11 both sides about connection pad element 20 was.
The present invention's insulation connection pad element 20 high temperature resistant by below pin electric connection point district 13, installing additional, hard, it is arranged between pin 12 and the chip support plate 11, it mainly acts on as follows: the insulation connection pad element 20 that 1, passes through high temperature, hard, make and isolate between pin 12 and the chip support plate 11 and insulation, prevented the generation of opening circuit; 2, between pin electric connection point district 13 and the connection pad element 20, and contact for no gap between connection pad element 20 and the chip support plate 11, make the surface, electric connection point district 13 and chip support plate 11 plane parallel of pin 12, like this, when chip 30 and 13 lines in pin electric connection point district, contact is more reliable, and then improves product percent of pass.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to restriction the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; but can do various changes and improvement, so the present invention's protection range is as the criterion when looking the claim person of defining.
Claims (5)
1. integrated circuit package structure, comprise lead frame (10) and packing colloid (40), in the middle of the lead frame (10) is a chip support plate (11), be provided with number of pins (12) around the chip support plate (11), chip (30) is fixed on the chip support plate (11), form the electric connection point district (13) of pin (12) in the top of chip support plate (11), it is characterized in that: also be provided with connection pad element (20), connection pad element (20) places chip support plate (11) to go up corresponding electric connection point district (13) projected position, connection pad element (20) comprises connection pad base (21) and connection pad boss (22), connection pad base (21) is arranged between pin (12) and the chip support plate (11), contact for no gap between electric connection point district (13) and the connection pad base (21) and between connection pad base (21) and the chip support plate (11), connection pad boss (22) extends to outstanding pin (12) end face to pin (12) end face direction.
2. a kind of integrated circuit package structure as claimed in claim 1 is characterized in that: connection pad element (20) adopts insulating material high temperature resistant, hard to make.
3. a kind of integrated circuit package structure as claimed in claim 1 is characterized in that: connection pad boss (22) exceeds 0.3～0.8 millimeter of pin (12) end face.
4. as claim 1 or 3 described a kind of integrated circuit package structures, it is characterized in that: the shape of connection pad boss (22) is identical with the shape in pin (12) gap.
5. as claim 1 or 3 described a kind of integrated circuit package structures, it is characterized in that: leave 0.1～0.2 mm clearance between connection pad boss (22) and pin (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810120426 CN101359644B (en) | 2008-09-04 | 2008-09-04 | Integrated circuit package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810120426 CN101359644B (en) | 2008-09-04 | 2008-09-04 | Integrated circuit package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101359644A CN101359644A (en) | 2009-02-04 |
| CN101359644B true CN101359644B (en) | 2010-08-25 |
Family
ID=40332042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810120426 Expired - Fee Related CN101359644B (en) | 2008-09-04 | 2008-09-04 | Integrated circuit package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101359644B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101794761A (en) * | 2010-03-23 | 2010-08-04 | 张轩 | Lead frame for use in IC packaging |
-
2008
- 2008-09-04 CN CN 200810120426 patent/CN101359644B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101359644A (en) | 2009-02-04 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100825 Termination date: 20170904 |
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| CF01 | Termination of patent right due to non-payment of annual fee |