CN101359637B - 带有金属接触层的功率半导体元件及其制造方法 - Google Patents

带有金属接触层的功率半导体元件及其制造方法 Download PDF

Info

Publication number
CN101359637B
CN101359637B CN2008101300718A CN200810130071A CN101359637B CN 101359637 B CN101359637 B CN 101359637B CN 2008101300718 A CN2008101300718 A CN 2008101300718A CN 200810130071 A CN200810130071 A CN 200810130071A CN 101359637 B CN101359637 B CN 101359637B
Authority
CN
China
Prior art keywords
power semiconductor
pressure
layer
metal
pasty state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008101300718A
Other languages
English (en)
Other versions
CN101359637A (zh
Inventor
C·格布尔
P·贝克达尔
海因里希·海尔布隆纳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semikron GmbH and Co KG
Semikron Elektronik GmbH and Co KG
Original Assignee
Semikron Elektronik GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron Elektronik GmbH and Co KG filed Critical Semikron Elektronik GmbH and Co KG
Publication of CN101359637A publication Critical patent/CN101359637A/zh
Application granted granted Critical
Publication of CN101359637B publication Critical patent/CN101359637B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0331—Manufacturing methods by local deposition of the material of the bonding area in liquid form
    • H01L2224/0332—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/035—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/03505—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05564—Only on the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75314—Auxiliary members on the pressing surface
    • H01L2224/75317—Removable auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

本发明涉及一种功率半导体元件，包括基体和至少一个接触面，其中在所述接触面上设置至少一个第一材料的薄的第一金属层。按本发明第二材料的与第一金属层相比较厚的另一金属层借助于所述材料的压力烧结连接设置在其上。所配设的方法具有以下主要步骤：在晶片阵列中制造多个功率半导体元件；将至少一个薄的第一金属层涂覆在各功率半导体元件的至少一个接触面上；将由第二材料和溶剂制成的糊状的层设置在各功率半导体元件的至少其中一个第一金属层上；对糊状的层加载压力；分离各半导体元件。

Description

带有金属接触层的功率半导体元件及其制造方法
技术领域
本发明涉及一种具有至少一个接触金属化层(Kontaktmetallisierung)的功率半导体元件，优选包括单晶的基体及至少一个p-n结。此种类型的功率半导体元件例如是功率二极管、功率晶体管或者功率晶闸管，但是也可以是太阳能电池及电阻元件。
背景技术
接触金属化层用于半导体主体的接触面与外部的连接元件导电地连接。此种类型连接元件例如可被设计为引线连接、焊接技术的连接基片或者压力接触的接线元件。
根据现有技术，多个不同的接触金属化层是常见的。其结构取决于其相应设定的接触副，例如引线连接。因此特别在功率半导体元件范围内已知多层的接触金属化层，其由不同的金属的层顺序构成。在这些层顺序内，相应层的单独的厚度是不同的，但是通常处于十分之几微米到几微米范围内。
对于在压力接触的结构中的使用也是已知的，在接线元件和功率半导体元件之间设置一厚度为毫米数量级的金属薄片。此金属薄片用于减少功率半导体元件及接触金属化层的机械应力。
发明内容
本发明的目的是，在接触金属化层的范围内进一步开发功率半导体元件，从而改善接触特性，并且给出一种方法，通过该方法功率半导体元件可实现简单的制造。
该目的按本发明通过借助于按照权利要求4的方法制造带有权利要求1的特征的功率半导体元件得以实现。优选的实施样式在从属权利要求中描述。
本发明的出发点是功率半导体元件，该功率半导体元件优选地带有一单晶的基体及至少一个p-n结。此功率半导体元件在半导体主体范围内具有至少一个接触面，在此接触面上设置至少一个第一材料的薄的第一金属层。在至少其中一个第一金属层上设置一个第二材料的相对于第一层较厚的金属层。在此优选的是，第二金属材料具有90％的贵金属含量。在此特别优选的是，贵金属为银。
此种结构将借助压力烧结连接构成。压力烧结连接应理解为，材料的层通过以下所述的方法进行设置。
按本发明的用于制造一此种类型的功率半导体元件的方法具有以下主要的步骤：
·在晶片阵列(Waferverbund)中制造多个功率半导体元件；
·将至少一个薄的第一金属层涂覆在各功率半导体元件的至少一个接触面上；
·将由第二材料和溶剂制成的糊状的层设置在各功率半导体元件的至少其中一个第一金属层上；
·对糊状的层加载压力。在此优选的是，在加载压力之前，将大部分的溶剂从糊状的层中排出；
·分离各半导体元件。
优选的是，借助于掩模压印法(Schablonendruckverfahren)涂覆糊状的层。在此一方面在要求的层厚度上可以达到必需的定位精度。另一方面此种方法可成本低廉地实现。
在糊状的层上加载压力的有利的第一实施样式可通过使用一压力机和两个压力柱塞实现。在此优选的是，至少一个压力柱塞设计有在其上设置的产生准静压的压力的硅酮垫。
在糊状的层加载压力的有利的第二实施样式可通过使用合适的液体或气体填充的压力罐实现。在此优选的是，功率半导体元件在晶片阵列中且通过一薄膜优选地聚四氟乙烯膜覆盖地设置在压力罐中，并且接下来从外部用压力加载压力罐中的液体。
附图说明
功率半导体元件及制造方法的特别优选的扩展构成在各实施例的描述中列举。此外，借助于图1到3的实施例进一步阐述此外本发明的解决方案。
图1和2示出了按本发明的第一功率半导体元件的按本发明的制造方法的单个步骤；
图3示出了按本发明的第二功率半导体元件。
具体实施方式
图1和2示出了按本发明的第一功率半导体元件的按本发明的制造方法的单个步骤。在图1中示出了带有功率半导体元件10的后来的边缘12的半导体主体，并且在半导体主体中以示意的方式示出多个在两个主表面102、104上的接触面20、22、24。此外示出第一金属材料36的薄的第一层的制造。在此根据现有技术例如借助于掩模38使用蒸镀法或者也使用溅射法。通过这些早已公知的方法沉积至少一个层厚度为微米数量级的均匀的层。在此可完全优选的是，沉积成包括多个薄的单层的层，所述单层由相应不同金属组成且具有相应不同层厚。
在下一个未明确示出的步骤中，优选地通过掩模压印技术将糊状的层44(图2)设置在第一层34上，如所述糊状的层根据背景技术已知由烧结连接制成。在此对于本发明不重要的是，层34、44是否直接相互叠置，或者糊状的第二层44略微地覆盖第一层34还是不完全地覆盖在第一层34。
糊状的层44(图2)本身由最大尺寸为微米数量级的金属片(Metallflocken)形式的金属材料的混合物及溶剂制成。银特别适合作为金属片的材料，但是同时其他的贵金属或者贵金属含量超过90％的混合物也适合。
图2示出了在糊状的层44上加载压力60，以便构成一相对于第一层较厚的第二金属层。附加地示出了且也优选的是在加载压力60前施加一薄膜50，例如一聚四氟乙烯薄膜。在此优选的是，覆盖全部的晶片阵列。但是在一些结构中可选择地仅用薄膜覆盖相应的糊状的层。
为了在糊状的层44和第一金属层34之间形成足够粘附的连接，优选的是，在加载压力60时引入的最大最终压力相当于至少15MPa.
此外有利的是除了加载压力60，功率半导体元件10及半导体主体加热到超过350K。这有利于把溶剂从糊状的层44上排出，因为制成的金属层应不再包含溶剂。
第二层金属层在加载压力60后具有一在10μm和80μm之间的优选的厚度，其中也可制造在1μm和250μm之间的层且按照应用同样是有意义的。
图3示出了按本发明的第二功率半导体元件10，在此是一功率晶闸管。其半导体主体在其第一主表面102上具有一第一接触面20，在此是阴极；且在其第二主表面104上具有两个另外的接触面22，24，一控制输入端，控制极22及一阳极24。在此构造中按本发明进一步构成所有的接触面。
每个接触面20，22，24具有一由第一的金属材料30，32，34制成的第一层，在此为不同材料的各分层，所述各分层具有一由银制成的最后的分层且总的层厚度为大约5μm。所述第一材料30，32，34被通过压力烧结方法设置的第二金属材料40，42，44(在此同样为带有层厚度为50μm的银)覆盖。
一此种类型设计的功率半导体元件10具有制造简单的优点(参考图1和图2)。另一方面此种类型的功率半导体元件10可以在一压力接触的结构中使用，而无需在未示出的接线元件和功率半导体元件10本身之间设置另一厚度在0.2mm到4mm范围内的金属薄片。此薄片的任务通过所述厚的第二金属层40，42，44承担。
按本发明的功率半导体元件10的优点在与其它连接技术的结合中也是有利的。特别对于制造带有基片的功率半导体元件10的烧结连接必要的是，功率半导体元件10具有用于连接的贵金属表面。此外有利的是，所述贵金属表面具有一超过10μm的层厚。此种类型的层通过所述的方法相对于通过标准方法例如通过蒸镀法或溅射法可明显更简单且成本较低地制造。

Claims (10)

1.功率半导体元件(10)，包括基体和至少一个接触面(20，22，24)，其中在所述接触面(20，22，24)上设置至少一个第一材料(30，32，34)的薄的第一金属层，并且第二材料(40，42，44)的与第一金属层相比较厚的另一金属层通过所述材料的压力烧结连接设置。
2.按权利要求1所述的功率半导体元件，金属的第二材料(40，42，44)具有多于90％的贵金属含量。
3.按权利要求2所述的功率半导体元件，贵金属为银。
4.用于制造按权利要求1所述的功率半导体元件(10)的方法，包括以下主要步骤：
在晶片阵列中制造多个功率半导体元件(10)；
将至少一个薄的第一金属层(30，32，34)涂覆在各功率半导体元件(10)的至少一个接触面(20，22，24)上；
将由第二材料和溶剂制成的糊状的层(40，42，44)设置在各功率半导体元件(10)的至少其中一个第一金属层上；
对糊状的层(40，42，44)加载压力(60)；
分离各半导体元件(10)。
5.按权利要求4所述的方法，其特征在于，所述糊状的层(40，42，44)通过掩模压印法涂覆。
6.按权利要求4所述的方法，其特征在于，借助于一压力机和两个压力柱塞施加所述压力(60)，其中至少一个压力柱塞设计有一在所述压力柱塞上设置的产生准静压的压力的硅酮垫。
7.按权利要求4所述的方法，其特征在于，在一从外部加载压力的且用液体或气体填充的压力罐中形成所述压力(60)，并且功率半导体元件(10)在晶片阵列中完全地布置在压力罐中。
8.按权利要求4所述的方法，其特征在于，在加载压力(60)时，最大的最终压力相当于至少15MPa。
9.按权利要求4所述的方法，其特征在于，在加载压力(60)的过程中，功率半导体元件(10)被加热到超过350K。
10.按权利要求4所述的方法，其特征在于，在加载压力(60)之前，用薄膜(50)覆盖糊状层(40，42，44)的表面或所有的晶片阵列。
CN2008101300718A 2007-07-26 2008-07-24 带有金属接触层的功率半导体元件及其制造方法 Active CN101359637B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007022338A DE102007022338B4 (de) 2007-07-26 2007-07-26 Herstellungsverfahren für ein Leistungshalbleiterbauelement mit Metallkontaktschicht
DE102007022338.4 2007-07-26

Publications (2)

Publication Number Publication Date
CN101359637A CN101359637A (zh) 2009-02-04
CN101359637B true CN101359637B (zh) 2012-08-29

Family

ID=40030257

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101300718A Active CN101359637B (zh) 2007-07-26 2008-07-24 带有金属接触层的功率半导体元件及其制造方法

Country Status (5)

Country Link
US (1) US8110925B2 (zh)
EP (1) EP2019421A3 (zh)
JP (1) JP2009033168A (zh)
CN (1) CN101359637B (zh)
DE (1) DE102007022338B4 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012107482A2 (en) 2011-02-08 2012-08-16 Abb Research Ltd Power semiconductor module
US8586480B1 (en) * 2012-07-31 2013-11-19 Ixys Corporation Power MOSFET having selectively silvered pads for clip and bond wire attach

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903886A (en) * 1988-03-03 1990-02-27 Siemens Aktiengesellschaft Method and apparatus for fastening semiconductor components to substrates
CN1961381A (zh) * 2004-02-18 2007-05-09 弗吉尼亚科技知识产权公司 用于连接的纳米级金属糊及其使用方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3414065A1 (de) * 1984-04-13 1985-12-12 Siemens AG, 1000 Berlin und 8000 München Anordnung bestehend aus mindestens einem auf einem substrat befestigten elektronischen bauelement und verfahren zur herstellung einer derartigen anordnung
EP0460286A3 (en) * 1990-06-06 1992-02-26 Siemens Aktiengesellschaft Method and arrangement for bonding a semiconductor component to a substrate or for finishing a semiconductor/substrate connection by contactless pressing
EP0477600A1 (de) * 1990-09-26 1992-04-01 Siemens Aktiengesellschaft Verfahren zum Befestigen eines mit wenigstens einem Halbleiterbauelement versehenen Halbleiterkörpers auf einem Substrat
DE59209470D1 (de) * 1991-06-24 1998-10-01 Siemens Ag Halbleiterbauelement und Verfahren zu seiner Herstellung
DE4233073A1 (de) 1992-10-01 1994-04-07 Siemens Ag Verfahren zum Herstellen eines Halbleiter-Modulaufbaus
JP4077888B2 (ja) * 1995-07-21 2008-04-23 株式会社東芝 セラミックス回路基板
DE10062108B4 (de) * 2000-12-13 2010-04-15 Infineon Technologies Ag Leistungsmodul mit verbessertem transienten Wärmewiderstand
EP1280196A1 (de) * 2001-07-18 2003-01-29 Abb Research Ltd. Verfahren zum Befestigen von elektronischen Bauelementen auf Substraten
JP2003101184A (ja) * 2001-09-27 2003-04-04 Kyocera Corp セラミック回路基板およびその製造方法
TWI239080B (en) * 2002-12-31 2005-09-01 Advanced Semiconductor Eng Semiconductor chip package and method for the same
DE10349477A1 (de) * 2003-10-21 2005-02-24 Infineon Technologies Ag Halbleiterbauteile mit einem Gehäuse und mit einem Halbleiterchip, sowie Verfahren zur Herstellung desselben
US20070183920A1 (en) * 2005-02-14 2007-08-09 Guo-Quan Lu Nanoscale metal paste for interconnect and method of use
DE102004019567B3 (de) * 2004-04-22 2006-01-12 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Befestigung von elektronischen Bauelementen auf einem Substrat
US20070065984A1 (en) * 2005-09-22 2007-03-22 Lau Daniel K Thermal enhanced package for block mold assembly
DE102005047566C5 (de) * 2005-10-05 2011-06-09 Semikron Elektronik Gmbh & Co. Kg Anordnung mit einem Leistungshalbleiterbauelement und mit einem Gehäuse sowie Herstellungsverfahren hierzu
DE102005058794A1 (de) * 2005-12-09 2007-06-14 Semikron Elektronik Gmbh & Co. Kg Vorrichtung und getaktetes Verfahren zur Drucksinterverbindung
US8067256B2 (en) * 2007-09-28 2011-11-29 Intel Corporation Method of making microelectronic package using integrated heat spreader stiffener panel and microelectronic package formed according to the method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903886A (en) * 1988-03-03 1990-02-27 Siemens Aktiengesellschaft Method and apparatus for fastening semiconductor components to substrates
CN1961381A (zh) * 2004-02-18 2007-05-09 弗吉尼亚科技知识产权公司 用于连接的纳米级金属糊及其使用方法

Also Published As

Publication number Publication date
EP2019421A2 (de) 2009-01-28
JP2009033168A (ja) 2009-02-12
EP2019421A3 (de) 2012-10-31
US20090039516A1 (en) 2009-02-12
DE102007022338A1 (de) 2009-04-09
US8110925B2 (en) 2012-02-07
DE102007022338B4 (de) 2013-12-05
CN101359637A (zh) 2009-02-04

Similar Documents

Publication Publication Date Title
CN1725396B (zh) 薄膜型多层陶瓷电容器及其制造方法
CN100481590C (zh) 柔性燃料电池
EP1798778A3 (en) Integrated thin-film solar cell and method of manufacturing the same
US20140284792A1 (en) Electronic device package
CN107689299B (zh) 薄膜陶瓷电容器
CN102568824A (zh) 层叠陶瓷电子部件
US5687056A (en) Variable voltage, variable capacitance chip capacitor device having lead pins electrically coupled to capacitor subassembly
US20170271298A1 (en) Method for producing a chip assemblage
CN110071050A (zh) 一种芯片互连结构及其制备方法
JP2014532308A (ja) 太径ワイヤ又はストリップに接するための金属成形体を備えたパワー半導体チップ及びその製造方法
CN101359637B (zh) 带有金属接触层的功率半导体元件及其制造方法
CN104576820A (zh) 制造太阳能电池装置背侧触点的方法和太阳能电池装置
US7269897B2 (en) Manufacturing process of a stacked semiconductor device
CN114005930A (zh) 超导量子芯片及倒装焊芯片间距控制方法
CN114041194B (zh) Ntc薄膜热敏电阻和制造ntc薄膜热敏电阻的方法
US8928140B2 (en) Method of manufacturing an electronic system
CN110690131B (zh) 一种具有大键合力的三维异构焊接方法
CN107195769A (zh) 多层压电陶瓷堆叠结构、传感器及其制备方法
CN101329953A (zh) 一种多层固态电解电容器的制造方法
JP5336086B2 (ja) 半導体デバイスの製造方法
JP2013207147A (ja) 基板および半導体装置
CN110506312B (zh) 多层器件和用于制造多层器件的方法
CN112259490A (zh) 具有加热功能的静电吸盘及其制备方法
CN112908695A (zh) 电容器组件结构及其制作方法
US20080081199A1 (en) Ceramic substrate and fabricating method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant