CN101354641B - Access control method and device of external memory - Google Patents
Access control method and device of external memory Download PDFInfo
- Publication number
- CN101354641B CN101354641B CN2008101419727A CN200810141972A CN101354641B CN 101354641 B CN101354641 B CN 101354641B CN 2008101419727 A CN2008101419727 A CN 2008101419727A CN 200810141972 A CN200810141972 A CN 200810141972A CN 101354641 B CN101354641 B CN 101354641B
- Authority
- CN
- China
- Prior art keywords
- data
- access
- director
- reference address
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention applicable to the memory field provides an access control method for an external memory and an access control device thereof. The method comprises the following steps of: receiving a command data access request which comprises a first command data access address; reading all data in a data line corresponding to the first command data access address in the data read in advance; adding a preset step value to the first command data access address to make a second command data access address; reading all data in a data line corresponding to the second command data access address from the external memory for buffer storage. Through reading the command data in advance for buffer storage, the access control method and the access control device of the invention read corresponding command data from the command data which is read in advance for buffer storage before the cache of a process hits, thereby improving the working efficiency of the processor.
Description
Technical field
The invention belongs to memory area, relate in particular to a kind of access control method and access control apparatus of external memory storage.
Background technology
Processor is the core of system works, and it need carry out frequent data interaction with external memory storage and carry out computing or system's control.But, cause processor must wait for that desired data obtains just can proceed computing from external memory storage, thereby reduced the work efficiency of processor because the travelling speed of existing external memory storage is far smaller than the arithmetic speed of processor.
For the influence of the external memory storage that reduces low speed to the processor work efficiency, prior art provides multiple external memory access method, as high-speed cache is set in processor, when processor generation data access request, from high-speed cache, inquire about earlier, if do not have, then the data access address that carries according to the data access request of processor of high-speed cache reads all data of the data line of this data access address correspondence from external memory storage, this external memory access method is very effective for the data of the same address area of processor repeated accesses, if but processor is often visited different address areas, then the hit rate of high-speed cache descends greatly, thereby influences the work efficiency of processor.
Prior art provides another kind of access method based on the external memory storage that reads mechanism in advance, this method is based on the default mechanism that reads in advance, the data that the processor of predicting is needed read in the high-speed cache from external memory storage in advance, when processor need use, directly from high-speed cache, obtain.This method has reduced the time-delay of reading of data, but but because required general split instruction data of data and the operational data of processor, wherein the correlativity of operational data is relevant with concrete application, more complicated, if employing is read mechanism in advance and is read operational data in advance, then read the Mechanism Design complexity in advance, and versatility is bad, is difficult to improve the work efficiency of processor.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of access control method of external memory storage, is intended to solve prior art low problem of access efficiency when the processor access external memory storage.
The embodiment of the invention is achieved in that a kind of access control method of external memory storage, and described method comprises the steps:
Receive data access request, and judge whether described data access request is the director data request of access, and described director data request of access comprises the first director data reference address;
When described data access request is the director data request of access, from the data that read in advance, read all data in the data line corresponding with the described first director data reference address;
The described first director data reference address is added that default step value is as the second director data reference address;
From external memory storage, read all data in the data line that also buffer memory is corresponding with the described second director data reference address.
Further, described method also comprises the steps:
When described data access request is not instruction during data access request, according to described data access request, directly to the external memory storage operation that conducts interviews.
Further, the described first director data reference address is being added that default step value is as the second director data reference address, read from external memory storage after the step of all data in the data line that also buffer memory is corresponding with the described second director data reference address, described method also comprises the steps:
Judge whether to receive non-director data request of access, whether the director data reference address that the director data request of access that perhaps receives is carried is the continuation address behind the described first director data reference address, whether the data that perhaps read have in advance reached default quantity, if finish to read;
If do not receive non-director data request of access, the director data reference address that the director data request of access that receives is carried is the continuation address behind the described first director data reference address, and the data that read in advance do not reach default quantity, then the described second director data reference address is added that default step value is as the 3rd director data reference address, all data in the data line corresponding with described the 3rd director data reference address are read in continuation from external memory storage, circulation is carried out, until receiving non-director data request of access, the director data reference address that the director data request of access that perhaps receives is carried is not the continuation address behind the described first director data reference address, and the data that perhaps read in advance reach default quantity.
Another purpose of the embodiment of the invention is to provide a kind of access control apparatus of external memory storage, and described access control apparatus comprises:
Bus interface is with condition handler, the prefetch data buffer memory that described bus interface is connected respectively, the external memory interface that is connected with described condition handler, prefetch data buffer memory, and the prefetch address buffer memory that is connected with described condition handler respectively;
Described condition handler comprises:
The instruction judging unit is used to judge whether the data access request that described bus interface receives is the director data request of access;
Access control unit is used for when described instruction judging unit judges that described data access request is the director data request of access, control described external memory interface from the outside in advance reading of data to described prefetch data buffer memory.
Further, described access control apparatus also comprises:
Read buffer memory and write buffer memory with described bus interface is connected with external memory interface respectively; At this moment,
When described access control unit judges that at described instruction judging unit described data access request is not the instruction data access request, control described external memory interface reading of data from external memory storage and perhaps the described data of writing in the buffer memory are write external memory storage to the described buffer memory of reading.
Further, described condition handler comprises:
The matching addresses unit is used in the result of described instruction judging unit when being, mate the address that prestores in first director data reference address that described director data request of access is carried and the described prefetch address buffer memory.
In embodiments of the present invention, by the access control apparatus of an external memory storage is set, director data is read buffer memory in advance, thereby when the cache-miss of processor, can from the access control apparatus of external memory storage, read in advance and read the corresponding instruction data in the buffer memory, thereby improve the work efficiency of processor.
Description of drawings
Fig. 1 is the realization flow figure of the external memory access control method that provides of the embodiment of the invention;
Fig. 2 is the structure composition diagram of the access control apparatus of the external memory storage that provides of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In embodiments of the present invention, when receiving the director data request of access, from the data that read in advance, read all data in the corresponding data line of the director data reference address that carries with this director data request of access, simultaneously this director data reference address is added that default step value is as the director data reference address, from external memory storage, read all data of the data line that also buffer memory is corresponding with this director data reference address in advance, thereby before processor uses director data, reading command data have in advance improved the work efficiency of processor.
Fig. 1 shows the realization flow of the external memory access control method that the embodiment of the invention provides, and details are as follows:
In step S101, receive and carry the data access request of data access address, and judge whether this data access request is the director data request of access, if, execution in step S102, otherwise, execution in step S106.
Because the required data of processor generally can be divided into two kinds, a kind of is the instruction data, and another kind is an operational data.Wherein director data is the instruction code of processor, and its correlativity generally is fixing continuity.Operational data is the operand of processor, and its correlativity is relevant with concrete computing application, and more complicated.Therefore, data access request can be instruction data access request or operational data request of access.Because the correlativity of operational data is relevant with concrete computing application, therefore, need read mechanism according to the data in advance of concrete computing Application Design correspondence, is difficult to design a kind of general data in advance and reads mechanism and read operational data in advance.And the correlativity of director data is fixing continuity, and therefore, the embodiment of the invention is primarily aimed at the mechanism that reads in advance that director data designs a kind of director data.So, when receiving data access request, need to judge whether this data access request is the director data request of access.
In embodiments of the present invention, can be by in data access request, adding marking signal, identifying this data access request by this marking signal still is the operational data request of access for the director data request of access.After receiving the data access request of carrying data access address, judge according to the marking signal in this data access request whether this data access request is the director data request of access.If this data access request is the director data request of access, then the data access address that carries of this data access request is the first director data reference address A, if this data access request is the operational data request of access, then the data access address that carries of this data access request is operational data reference address B.
In step S102, first director data reference address A that this director data request of access is carried and the address line that reads in advance mate item by item, if coupling is unsuccessful, and execution in step S103, if the match is successful, while execution in step S104 and step S105.
In step S103, from external memory storage, read all data in the data line corresponding with this first director data reference address A, and with the data transmission that reads to the high speed buffer memory, execution in step S105 again.
In step S104, from the data that read in advance, read with this pairing data line in first director data reference address A address that the match is successful in all data and transfer to high-speed cache, return step S101 again, continue to wait for the request of access that receives bus interface.
For guarantee from the data that read in advance, to read with this pairing data line in first director data reference address A address that the match is successful in all data be valid data, in another embodiment of the present invention, read with this pairing data line in first director data reference address A address that the match is successful in all data before, this method also comprises the steps:
Whether the significance bit of the data in judgement and this pairing data line in first director data reference address A address that the match is successful is effective, if, then read these data and with this data transmission to the high speed buffer memory, if not, then wait for read these data again after significance bit until these data is changed to effectively and with this data transmission to the high speed buffer memory, circulation is carried out, until with this pairing data line in first director data reference address A address that the match is successful in all data all read and finish.
In step S105, this first director data reference address A is added that default step value S is as the second director data reference address C, from external memory storage, read all data in the data line corresponding with this second director data reference address C, and buffer memory second director data reference address C and the data that read.Its detailed process is as described below:
A, this first director data reference address A is added default step value S as the second director data reference address C, and this second director data reference address of buffer memory C.Wherein the length of Yu She step value S is the size of the data line of the high-speed cache that uses of processor, and promptly the data volume that at every turn reads in advance is the data volume of the delegation of the high-speed cache that uses of processor.
B, from external memory storage, read all data and buffer memory in the data line corresponding with this second director data reference address C.
Because when reading the data line corresponding with the second director data reference address C, word for word read, therefore, when whenever reading data in the data line corresponding with the second director data reference address C, the active position that is about to this data correspondence is effective, in order to later on when reading these data, guarantee the validity of these data.
In another embodiment of the present invention, after all data in the data line that has read the second director data reference address C correspondence, if receive the non-director data request of access of bus interface transmission, perhaps receive the director data request of access, but the director data reference address that this director data request of access is carried is not the continuation address of the first director data reference address A back, perhaps the data that read from external memory storage of buffer memory have reached predetermined number, then stop to continue reading of data from external memory storage.If do not receive non-director data request of access, the director data reference address that the director data request of access that receives is carried is the continuation address behind the described first director data reference address A, and the data that read in advance do not reach default quantity, the second director data reference address C is added that default step value S is as the 3rd director data reference address D, all data in the data line corresponding with the 3rd director data reference address D are read in continuation from external memory storage, circulation is carried out, until receiving non-director data request of access, the director data reference address that the director data request of access that perhaps receives is carried is not the continuation address behind the first director data reference address A, the data that perhaps read have in advance reached default quantity, promptly stop reading of data in advance.
In step S106, the data access address that carries according to the data access request that receives to the external memory storage operation that conducts interviews, returns step S101 after one time data access operation is finished, and continues to wait for the request of access of reception bus interface.
In embodiments of the present invention, when the data access request that receives is the write data request of access, this write data request of access is carried the data and the data that need write in the external memory storage and is write the address, at this moment, the needs that this write data request of access the is carried data of carrying with this write data request of access that write that data in the external memory storage write to external memory storage write in the corresponding address of address.When the data access request from the data bus transmission is the read data request of access, this read data request of access is carried data read address, at this moment, from external memory storage, read the corresponding data of data read address of carrying, and transfer to bus interface with this read data request of access.
Fig. 2 shows the structure of the access control apparatus of the external memory storage that the embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with the embodiment of the invention.
Bus interface 1 is connected with high-speed cache (scheming not shown), the condition handler 2 of processor respectively, the data access request of the high-speed cache of processor is transferred to condition handler 2, simultaneously this bus interface 1 respectively with prefetch data buffer memory 3, read buffer memory 5 and write buffer memory 6 to be connected, with the data in the prefetch data buffer memory 3 or read data transmission in the buffer memory 5 to the high-speed cache of processor, perhaps the data with the cache transfers of processor write in the buffer memory 6.
Wherein prefetch data buffer memory 3 is kept in the director datas that read in advance from external memory storage.This prefetch data buffer memory 3 can have at least one data line, the data line of the high-speed cache that the size of data line and processor use big or small consistent.Each data in the data line are provided with a significance bit simultaneously, and whether data corresponding in this this data line of significance bit sign are effective.
The high address that prefetch address buffer memory 4 is stored corresponding to the director data in the prefetch data buffer memory 3, i.e. an address line in the corresponding prefetch address buffer memory 4 of each data line.
External memory interface 7 under the control of condition handler from external memory storage in advance reading of data to prefetch data buffer memory 3 or reading of data to reading in the buffer memory 5, perhaps the data with cache transfers write external memory storage.
Wherein condition handler 2 comprises instruction judging unit 21, matching addresses unit 22, access control unit 23.This instruction judging unit 21 judges whether this data access request is the director data request of access when receiving the data access request of bus interface 1 transmission.In embodiments of the present invention, can be by adding marking signal in the director data request of access, identifying this data access request by this marking signal still is the operational data request of access for the director data request of access.Instruction judging unit 21 can judge according to the marking signal in the data access request whether this data access request is the director data request of access.
If instruction judging unit 21 judges that the data access request of bus interface 1 transmission is the director data request of access, then this director data request of access is carried the first director data reference address A.When this data access request was the director data request of access, mated the address that prestores in first director data reference address A that matching addresses unit 22 carries this director data request of access and the prefetch address buffer memory 4.
Wherein access control unit 23 comprises the access control module 231 of looking ahead, directly reads control module 232 and direct access control module 233.
Wherein look ahead access control module 231 when instruction judging unit 21 judges that the data access request of bus interface 1 transmission is the director data request of access, from prefetch data buffer memory 3, read data in the corresponding data line in address in the prefetch address buffer memory 4 with first director data reference address A coupling to bus interface 1, the first director data reference address A that simultaneously this director data request of access is carried adds that default step value S is as the second director data reference address C, and with this second director data reference address C buffer memory to prefetch address buffer memory 4, control external memory interface 7 simultaneously and read data the data line corresponding in advance to prefetch data buffer memory 3 with this second director data reference address C from external memory storage.
In another embodiment of the present invention, the access control module 231 control external memory interfaces 7 of looking ahead read all data in the data line corresponding with this second director data reference address C in advance from external memory storage after, if receive non-director data request of access from bus interface 1, the director data reference address that the director data request of access that perhaps receives is carried is not the continuation address of the first director data reference address A back, perhaps the data line in the prefetch data buffer memory 3 is full, the access control module 231 control external memory interfaces 7 of then looking ahead stop reading of data in advance, otherwise, the access control module 231 of looking ahead adds default step value S as the 3rd director data reference address D with the second director data reference address C, and continuation control external memory interface 7 reads all data in the data line corresponding with the 3rd director data reference address D in advance and keeps in to prefetch data buffer memory 3 from external memory storage.
Directly read matching addresses that control module 232 prestores in the first director data reference address A and prefetch address buffer memory 4 in matching addresses unit 22 when unsuccessful, control external memory interface 7 directly reads the data in the data line corresponding with the first director data reference address A from external memory storage, and the data that read are temporary to reading in the buffer memory 5, will read data transmission in the buffer memory 5 to the high-speed cache of processor by data-interface 21.
Directly access control module 233 is when instruction judging unit 21 judges that the data access request of bus interface 1 transmission is not the instruction data access request, the data that control external memory interface 7 will be write in the buffer memory 6 according to data access request write external memory storage, perhaps reading of data will be read data transmission in the buffer memory 5 to the high-speed cache of processor by bus data interface 21 again to reading buffer memory 5 from external memory storage.
In embodiments of the present invention, the access control apparatus of external memory storage is when receiving the director data request of access, from the data that prestore, search earlier, the director data reference address that carries according to this director data request of access simultaneously adds default step-length, reading of data in advance from external memory storage, thereby increased the hit rate of high-speed cache, improved the work efficiency of processor.Simultaneously the embodiment of the invention externally is provided with in the access control apparatus of storer and reads buffer memory (comprising prefetch address buffer memory and prefetch data buffer memory) in advance, does not need to revise the high-speed cache of processor, and versatility is better.The embodiment of the invention is by being provided with significance bit for data, thereby do not read fully when finishing at a data line, significance bit that can first reading of data is an active data, do not redo after finishing thereby do not need processor to wait for that the full line data all read, improved the work efficiency of processor.The embodiment of the invention is after the read request of delegation's director data of finishing processor simultaneously, if do not receive other non-director data request of access, and prediction is correct, and the prefetch data buffer memory less than the time, continue to read the next line director data, thereby increased the amount of reading of the valid data of each access external memory, improved the access efficiency of external memory storage.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. the access control method of an external memory storage is characterized in that, described method comprises the steps:
Receive data access request, and judge whether described data access request is the director data request of access, and described director data request of access comprises the first director data reference address;
When described data access request is the director data request of access, from the data that read in advance, read all data in the data line corresponding with the described first director data reference address;
The described first director data reference address is added that default step value is as the second director data reference address;
From external memory storage, read all data in the data line that also buffer memory is corresponding with the described second director data reference address.
2. the method for claim 1 is characterized in that, described method also comprises the steps:
When described data access request is not instruction during data access request, according to described data access request, directly to the external memory storage operation that conducts interviews.
3. the method for claim 1, it is characterized in that, the described first director data reference address is being added that default step value is as the second director data reference address, read from external memory storage after the step of all data in the data line that also buffer memory is corresponding with the described second director data reference address, described method also comprises the steps:
Judge whether to receive non-director data request of access, whether the director data reference address that the director data request of access that perhaps receives is carried is the continuation address behind the described first director data reference address, whether the data that perhaps read have in advance reached default quantity, if finish to read;
If do not receive non-director data request of access, the director data reference address that the director data request of access that receives is carried is the continuation address behind the described first director data reference address, and the data that read in advance do not reach default quantity, then the described second director data reference address is added that default step value is as the 3rd director data reference address, all data in the data line corresponding with described the 3rd director data reference address are read in continuation from external memory storage, circulation is carried out, until receiving non-director data request of access, the director data reference address that the director data request of access that perhaps receives is carried is not the continuation address behind the described first director data reference address, and the data that perhaps read in advance reach default quantity.
4. the method for claim 1 is characterized in that, during all data in read the data line corresponding with described director data reference address in advance from external memory storage, whenever reads data of success, and the active position that is about to described data is for effectively.
5. method as claimed in claim 4, it is characterized in that, read from the data that read in advance before the step of all data in the corresponding data line of the first director data reference address that carries with described director data request of access, described method also comprises the steps:
Whether the significance bit of judging the data in the corresponding data line of the first director data reference address that carries with described director data request of access is effective, if, then read described data, otherwise, wait for after the significance bit of described data is changed to effectively and read described data again.
6. as the described method of the arbitrary claim of claim 1 to 5, it is characterized in that described default step value is the size of the data line of the employed high-speed cache of processor.
7. the access control apparatus of an external memory storage is characterized in that, described access control apparatus comprises:
Bus interface, the condition handler that is connected with described bus interface, prefetch data buffer memory respectively, the external memory interface that is connected with described condition handler, prefetch data buffer memory, and the prefetch address buffer memory that is connected with described condition handler respectively;
Described condition handler comprises:
The instruction judging unit is used to judge whether the data access request that described bus interface receives is the director data request of access;
Access control unit is used for when described instruction judging unit judges that described data access request is the director data request of access, control described external memory interface from the outside in advance reading of data to described prefetch data buffer memory.
8. access control apparatus as claimed in claim 7 is characterized in that, described access control apparatus also comprises:
Read buffer memory and write buffer memory with described bus interface is connected with external memory interface respectively; At this moment,
When described access control unit judges that at described instruction judging unit described data access request is not the instruction data access request, control described external memory interface and fetch data to the described buffer memory of reading, perhaps the described data of writing in the buffer memory are write external memory storage from external read.
9. access control apparatus as claimed in claim 8 is characterized in that, described condition handler comprises:
The matching addresses unit, be used for when described instruction judging unit judges that described data access request is the director data request of access, mate the address that prestores in first director data reference address that described director data request of access is carried and the described prefetch address buffer memory.
10. access control apparatus as claimed in claim 9 is characterized in that, described access control unit comprises:
The access control module of looking ahead, be used in the result of described instruction judging unit when being, from described prefetch data buffer memory, read data in the data line corresponding to described bus interface with the address of described first director data reference address coupling, the first director data reference address that described director data request of access is carried adds that default step value is as the second director data reference address simultaneously, and with the described second director data reference address buffer memory to described prefetch address buffer memory, control described external memory interface simultaneously and read data the data line corresponding in advance from the outside to described prefetch data buffer memory with the described second director data reference address;
Directly read control module, be used in the result of described matching addresses unit for not the time, control described external memory interface and directly read data the data line corresponding with the described first director data reference address from the outside, and the data that read are temporary to described reading in the buffer memory;
Direct access control module, be used in the result of described instruction judging unit for not the time, control described external memory interface and fetch data to the described buffer memory of reading from external read, perhaps the described data of writing in the buffer memory are write external memory storage according to described data access request.
11. access control apparatus as claimed in claim 10; It is characterized in that; Control described external memory interface when the described access control module of looking ahead and read in advance data the data line corresponding with the described second director data reference address from the outside to the described prefetch data buffer memory; If do not receive non-director data access request; The director data reference address that the director data access request that receives is carried is the continuation address behind the described first director data reference address; And when the data that read in advance do not reach default quantity
The described access control module of looking ahead adds that with the described second director data reference address default step value is as the 3rd director data reference address, all data the data line corresponding with described the 3rd director data reference address are read in continuation from the outside, circulation is carried out, until receiving non-director data request of access, the director data reference address that the director data request of access that perhaps receives is carried is not the continuation address behind the described first director data reference address, and the data that perhaps read in advance reach default quantity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101419727A CN101354641B (en) | 2008-08-20 | 2008-08-20 | Access control method and device of external memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101419727A CN101354641B (en) | 2008-08-20 | 2008-08-20 | Access control method and device of external memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101354641A CN101354641A (en) | 2009-01-28 |
| CN101354641B true CN101354641B (en) | 2010-08-11 |
Family
ID=40307463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101419727A Expired - Fee Related CN101354641B (en) | 2008-08-20 | 2008-08-20 | Access control method and device of external memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101354641B (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101907986B (en) * | 2010-08-30 | 2013-11-06 | 威盛电子股份有限公司 | Data processing equipment and data processing method accessing multiple memories |
| US8341382B2 (en) * | 2010-09-30 | 2012-12-25 | Nxp B.V. | Memory accelerator buffer replacement method and system |
| GB2491156B (en) | 2011-05-25 | 2019-08-07 | Advanced Risc Mach Ltd | Processing pipeline control |
| CN102646073B (en) * | 2012-04-28 | 2015-01-07 | 华为技术有限公司 | Data processing method and device |
| CN104657298A (en) * | 2015-02-11 | 2015-05-27 | 昆腾微电子股份有限公司 | Reading control device and method |
| CN106294207B (en) * | 2015-05-22 | 2020-08-04 | 炬芯（珠海）科技有限公司 | Data feedback method, buffer, controller and system |
| CN106326138B (en) * | 2015-07-03 | 2019-11-05 | 比亚迪股份有限公司 | The access control method of flash memory and flash memory internal data |
| WO2017054132A1 (en) * | 2015-09-29 | 2017-04-06 | 华为技术有限公司 | Method for generating address and data processing device |
| CN106846142B (en) * | 2015-12-07 | 2021-02-05 | 腾讯科技（深圳）有限公司 | Information processing method and server |
| WO2017185375A1 (en) * | 2016-04-29 | 2017-11-02 | 华为技术有限公司 | Method for data access and memory controller |
| US10353819B2 (en) * | 2016-06-24 | 2019-07-16 | Qualcomm Incorporated | Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in a processor-based system |
| CN106681939B (en) * | 2017-01-03 | 2019-08-23 | 北京华胜信泰数据技术有限公司 | Reading method and device for disk page |
| CN109284240B (en) * | 2018-10-15 | 2020-06-16 | 上海兆芯集成电路有限公司 | Memory integrated circuit and prefetching method thereof |
| US11113213B2 (en) | 2019-12-30 | 2021-09-07 | Micron Technology, Inc. | Determining write commands for deletion in a host interface |
| CN111459857B (en) * | 2020-03-31 | 2022-04-19 | 西安微电子技术研究所 | TCM controller and data cache reading method |
| CN111541823B (en) * | 2020-04-17 | 2022-04-19 | 展讯通信（上海）有限公司 | Modem and communication device |
| CN111915475B (en) * | 2020-07-10 | 2024-04-05 | 长沙景嘉微电子股份有限公司 | Processing method of drawing command, GPU, host, terminal and medium |
| CN116501388B (en) * | 2023-06-26 | 2023-10-03 | 深流微智能科技(深圳)有限公司 | Instruction processing method, device, storage medium and equipment |
-
2008
- 2008-08-20 CN CN2008101419727A patent/CN101354641B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101354641A (en) | 2009-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101354641B (en) | Access control method and device of external memory | |
| US6138208A (en) | Multiple level cache memory with overlapped L1 and L2 memory access | |
| US6782454B1 (en) | System and method for pre-fetching for pointer linked data structures | |
| US5586295A (en) | Combination prefetch buffer and instruction cache | |
| US4800483A (en) | Method and system for concurrent data transfer disk cache system | |
| JP4486750B2 (en) | Shared cache structure for temporary and non-temporary instructions | |
| US5524220A (en) | Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems | |
| CN100375067C (en) | Local space shared memory method of heterogeneous multi-kernel microprocessor | |
| CN100407169C (en) | Method to provide cache management commands for a DMA controller | |
| US20040215901A1 (en) | Method and mechanism to use a cache to translate from a virtual bus to a physical bus | |
| CN102866879B (en) | Efficient memory hierarchy management | |
| KR100395756B1 (en) | Cache memory and microprocessor using this cache memory | |
| KR100535146B1 (en) | Localized cache block flush instruction | |
| US8954676B2 (en) | Cache with scratch pad memory structure and processor including the cache | |
| CN103729306A (en) | Multi CPU invalidate operation bypass through address range check | |
| US5396604A (en) | System and method for reducing the penalty associated with data cache misses | |
| KR100234647B1 (en) | Data processing system with instruction prefetch | |
| CN101652759B (en) | Programmable data prefetching method and system | |
| US20060149940A1 (en) | Implementation to save and restore processor registers on a context switch | |
| CN116055429A (en) | PCIE-based communication data processing method, PCIE-based communication data processing device, PCIE-based communication data processing equipment and storage medium | |
| US6842822B2 (en) | System and method for cache external writing | |
| US5535360A (en) | Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor | |
| US20060212660A1 (en) | Method and an apparatus to reduce network utilization in a multiprocessor system | |
| CN100520737C (en) | Caching system, method and computer system | |
| CN100524357C (en) | Data pre-fetching system in video processing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170612 Address after: 519085 C District, 1# workshop, No. 1, science and technology No. four road, hi tech Zone, Zhuhai, Guangdong, China Patentee after: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. Address before: 519085 No. 1, unit 15, building 1, 1 Da Ha Road, Tang Wan Town, Guangdong, Zhuhai Patentee before: Juli Integrated Circuit Design Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee after: ACTIONS TECHNOLOGY Co.,Ltd. Address before: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee before: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100811 Termination date: 20200820 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |