CN106294207B - Data feedback method, buffer, controller and system - Google Patents
Data feedback method, buffer, controller and system Download PDFInfo
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- CN106294207B CN106294207B CN201510270316.7A CN201510270316A CN106294207B CN 106294207 B CN106294207 B CN 106294207B CN 201510270316 A CN201510270316 A CN 201510270316A CN 106294207 B CN106294207 B CN 106294207B
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Abstract
The embodiment of the invention discloses a method, a buffer, a controller and a system for feeding back data, which are used for solving the problems that in the prior art, a large number of Code RAMs are required to be designed in the design of a system on chip and used for storing codes of resident memories in different operation scenes, so that the whole chip area of the system on chip is increased, and the integration level of the system on chip is reduced. The method of the invention comprises the following steps: after receiving a first read command sent by a processor through a controller, a buffer judges whether a first data address corresponding to the first read command exists in an address mapping relation; after determining that a first data address corresponding to the first read command exists in the address mapping relation, the buffer determines a second data address corresponding to the first data address according to the address mapping relation; and when the buffer determines that the data corresponding to the second data address is in the buffer, feeding back the data to the processor as the data required to be acquired by the processor. The method of the invention can improve the integration level of the system on chip.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, a buffer, a controller, and a system for feeding back data.
Background
A system-on-chip refers to the integration of a complete system on a single chip, which generally includes: processor, memory, and peripheral circuitry. Typically, software code of the system on chip or the like will be stored on the external memory. As shown in fig. 1, a schematic structural diagram of a system on chip, as can be seen from fig. 1, the system on chip includes: bus Bridge, CPU (Central Processing Unit), Memory Controller, ROM (read only Memory), Data RAM (RAM, Random Access Memory), Code RAM (Code Random Access Memory), SPI Controller (Serial Peripheral interface), AHB (Advanced High performance Bus), AHB Device 0 (system Bus), AHB Device1, AHB Device 2, APB (Advanced Peripheral Bus), APB Device 0 (Peripheral Bus Device 0), APB 1, APB Device 2, DMA, APB Device 3, and Direct Memory Access (Direct Memory Access Controller).
Currently, when a system on chip needs to be switched from one operating scenario to another operating scenario, a Code of a new operating scenario needs to be loaded into a Code RAM in the system on chip from an external memory, and then the Code of the new operating scenario is operated.
To sum up, in the current system-on-chip design, a large number of Code RAMs need to be designed for storing codes of resident memories in different operating scenes, so that the whole chip area of the system-on-chip is increased, and the integration level of the system-on-chip is reduced.
Disclosure of Invention
The embodiment of the invention provides a data feedback method, a buffer, a controller and a system, which are used for solving the problems that in the prior art, a large number of Code RAMs are required to be designed in the design of a system on chip and used for storing codes of resident memories in different operation scenes, so that the whole chip area of the system on chip is increased, and the integration level of the system on chip is reduced.
The embodiment of the invention discloses a method for feeding back data, which comprises the following steps:
after receiving a first read command sent by a processor through a controller, a buffer judges whether a first data address corresponding to the first read command exists in an address mapping relation;
after determining that a first data address corresponding to the first read command exists in the address mapping relationship, the buffer determines a second data address corresponding to the first data address according to the address mapping relationship;
and when the buffer determines that the data corresponding to the second data address is in the buffer, the data is used as the data required to be acquired by the processor and is fed back to the processor.
According to the embodiment of the invention, the buffer determines the second data address corresponding to the first data address after determining that the first data address corresponding to the first read command exists in the address mapping relation according to the received first read command sent by the processor through the controller and the address mapping relation, and feeds back the data to the processor when determining that the data corresponding to the second data address is stored in the buffer.
Preferably, before receiving the first read command sent by the processor through the controller, the buffer further includes:
and the buffer establishes the address mapping relation according to the received first data address and the second data address.
Preferably, after the determining, by the buffer, whether the first data address corresponding to the first read command exists in the address mapping relationship, the method further includes:
and after determining that the first data address corresponding to the first read command does not exist in the address mapping relationship, the buffer processes the first read command according to the type of the first read command.
Preferably, the processing, by the buffer, the first read command according to the type of the first read command includes:
the first read command is a read instruction command, and the buffer informs the processor of exception handling; after receiving a notification of exception handling, the processor updates the address mapping relationship according to the obtained first data address corresponding to the first read command and the obtained second data address corresponding to the first data address; the processor sends a first read command corresponding to the first data address to the buffer through the controller; or
The first read command is a read data command, and the buffer records a first data address corresponding to the first read command and a first data address corresponding to the next first read command when the first read command is a read instruction command.
After the buffer informs the processor to perform exception handling, the processor determines a corresponding second data address according to a first data address corresponding to an obtained first read command, updates an address mapping relation, and sends the first read command corresponding to the first data address to the buffer through the controller, so that the buffer can find the second data address corresponding to the first data address in the address mapping relation; according to the embodiment of the invention, the buffer records the first data address corresponding to the first read command and the first data address corresponding to the next first read command when the first read command is a read command, so that the later debugging and positioning can be conveniently carried out according to the two recorded first data addresses.
Preferably, after the buffer determines the second data address corresponding to the first data address, the method further includes:
when the buffer determines that the data corresponding to the second data address is not in the buffer, sending a second read command to the external memory;
the buffer feeds back data corresponding to the second data address in the data corresponding to the second read command fed back by the external memory to the processor as data required to be acquired by the processor;
and the buffer stores the data corresponding to the second read command fed back by the external memory into the buffer.
In the embodiment of the invention, the buffer sends the second read command to the external memory, acquires the data which are fed back by the external memory and contain the data corresponding to the second data address, and feeds back the data corresponding to the second data address to the processor, so that the processor continues to execute corresponding operations according to the data; according to the embodiment of the invention, the buffer stores the data corresponding to the second read command fed back by the external memory into the buffer, so that the processor can conveniently acquire the data next time.
The embodiment of the invention provides a buffer for feedback data, which comprises:
the first judging module is used for judging whether a first data address corresponding to a first read command exists in an address mapping relation after receiving the first read command sent by a processor through a controller;
a first determining module, configured to determine, after determining that a first data address corresponding to the first read command exists in the address mapping relationship, a second data address corresponding to the first data address according to the address mapping relationship;
and the first feedback module is used for feeding back the data which is used as the data required to be acquired by the processor to the processor when the data corresponding to the second data address is determined to be in the buffer.
Preferably, the first determining module is further configured to:
and establishing the address mapping relation according to the received first data address and the second data address.
Preferably, the first determining module is further configured to:
and processing the first read command according to the type of the first read command after determining that the first data address corresponding to the first read command does not exist in the address mapping relation.
Preferably, the first determining module is specifically configured to:
the first read command is a read instruction command and informs the processor of carrying out exception handling; after receiving the notification of exception handling, the processor updates the address mapping relationship according to the obtained first data address corresponding to the first read command and the obtained second data address corresponding to the first data address, and sends the first read command corresponding to the first data address to the buffer through the controller; or the first read command is a read data command, and a first data address corresponding to the first read command and a first data address corresponding to the next first read command when the first read command is a read instruction command are recorded.
Preferably, the first feedback module is further configured to:
when the data corresponding to the second data address is determined not to be in the buffer, sending a second read command to the external memory; feeding back data corresponding to the second data address in the data corresponding to the second read command fed back by the external memory to the processor; and storing data corresponding to the second read command fed back by the external memory into the buffer.
An embodiment of the present invention provides a system for feeding back data, including,
the first buffer is used for judging whether a first data address corresponding to a first read command exists in an address mapping relation after receiving the first read command sent by a first controller; after determining that a first data address corresponding to the first read command exists in the address mapping relationship, determining a second data address corresponding to the first data address according to the address mapping relationship; when the data corresponding to the second data address is determined to be in the buffer, the data is used as the data required to be acquired by the processor and is fed back to the processor;
the first controller is used for sending the received first read command from the first processor to the first buffer;
a first processor to send the first read command to the first controller.
The embodiment of the invention provides a method for feeding back data, which comprises the following steps:
after receiving a third read command sent by a processor, the controller judges whether a third data address corresponding to the third read command exists in an address mapping relation;
after determining that a third data address corresponding to the third read command exists in the address mapping relationship, the controller determines a fourth data address corresponding to the third data address according to the address mapping relationship;
the controller sends the determined fourth data address to a buffer.
According to the embodiment of the invention, after the controller determines that the address mapping relation has the third data address corresponding to the third read command according to the received third read command sent by the processor and the address mapping relation, the fourth data address corresponding to the third data address is determined, and the determined fourth data address is sent to the buffer, so that the buffer determines whether the data corresponding to the fourth data address is in the buffer according to the fourth data address.
Preferably, before receiving the third read command sent by the processor, the controller further includes:
and the controller establishes the address mapping relation according to the received third data address and the fourth data address.
Preferably, after the controller determines whether a third data address corresponding to the third read command exists in the address mapping relationship, the method further includes:
and after determining that the third data address corresponding to the third read command does not exist in the address mapping relationship, the controller processes the third read command according to the type of the third read command.
Preferably, the processing, by the controller, the third read command according to the type of the third read command includes:
the third read command is a read instruction command, and the controller informs the processor of exception handling; after receiving the notification of exception handling, the processor updates the address mapping relationship according to the obtained third data address corresponding to the third read command and the obtained fourth data address corresponding to the third data address; the processor sends a third read command corresponding to the third data address to the controller; or
The third read command is a read data command, and the controller records a third data address corresponding to the third read command and a third data address corresponding to the next third read command when the third read command is a read instruction command.
After the controller notifies the processor to perform exception handling, the processor determines a corresponding fourth data address according to a third data address corresponding to an obtained third read command, updates an address mapping relation, and sends the third read command corresponding to the third data address to the controller, so that the controller can find the fourth data address corresponding to the third data address in the address mapping relation; according to the embodiment of the invention, the controller records the third data address corresponding to the third read command and the third data address corresponding to the next third read command as the read command, so that the later debugging and positioning can be conveniently carried out according to the two recorded third data addresses.
The embodiment of the invention provides a method for feeding back data, which comprises the following steps:
the buffer receives a fourth data address sent by the controller;
and when the buffer determines that the data corresponding to the fourth data address is in the buffer, the data is used as the data required to be acquired by the processor and is fed back to the processor.
According to the embodiment of the invention, when the buffer determines that the data corresponding to the fourth data address is stored in the buffer according to the received fourth data address sent by the controller, the data is fed back to the processor, so that the system on chip can run in different running scenes only by designing the buffer with smaller storage capacity without designing a large amount of Code RAMs, and the integration level of the system on chip is improved.
Preferably, after the buffer receives the fourth data address sent by the controller, the method further includes:
when the buffer determines that the data corresponding to the fourth data address is not in the buffer, the buffer sends a fourth read command to an external memory;
the buffer feeds back data corresponding to the fourth data address in the data corresponding to the fourth read command fed back by the external memory to the processor;
and the buffer stores the data corresponding to the fourth read command fed back by the external memory into the buffer.
In the embodiment of the invention, the buffer sends the fourth read command to the external memory, acquires the data which are fed back by the external memory and contain the data corresponding to the fourth data address, and feeds back the data corresponding to the fourth data address to the processor, so that the processor continues to execute corresponding operations according to the data; according to the embodiment of the invention, the buffer stores the data corresponding to the fourth read command fed back by the external memory into the buffer, so that the processor can conveniently acquire the data next time.
An embodiment of the present invention provides a controller for feeding back data, including:
the second judging module is used for judging whether a third data address corresponding to a third read command exists in an address mapping relation after receiving the third read command sent by the processor;
a second determining module, configured to determine, after determining that a third data address corresponding to the third read command exists in the address mapping relationship, a fourth data address corresponding to the third data address according to the address mapping relationship;
and the sending module is used for sending the determined fourth data address to a buffer.
Preferably, the second determining module is further configured to:
and establishing the address mapping relation according to the received third data address and the fourth data address.
Preferably, the second determining module is further configured to:
and processing the third read command according to the type of the third read command after determining that the third data address corresponding to the third read command does not exist in the address mapping relation.
Preferably, the second determining module is further configured to:
the third read command is a read instruction command and informs the processor of carrying out exception handling; after receiving the notification of performing exception handling, the processor updates the address mapping relationship according to the obtained third data address corresponding to the third read command and the obtained fourth data address corresponding to the third data address, and sends a third read command corresponding to the third data address to the controller; or the third read command is a read data command, and a third data address corresponding to the third read command and a third data address corresponding to the next third read command when the third read command is a read instruction command are recorded.
The embodiment of the invention provides a buffer for feedback data, which comprises:
the receiving module is used for receiving a fourth data address sent by the controller;
and the second feedback module is used for feeding back the data which is used as the data required to be acquired by the processor to the processor when the data corresponding to the fourth data address is determined to be in the buffer.
Preferably, the second feedback module is further configured to:
when the data corresponding to the fourth data address is determined not to be in the buffer, sending a fourth read command to an external memory; feeding back data corresponding to the fourth data address in the data corresponding to the fourth read command fed back by the external memory to the processor; and storing data corresponding to the fourth read command fed back by the external memory into the buffer.
The embodiment of the invention provides a system for feeding back data, which comprises:
the second buffer is used for receiving a fourth data address sent by the controller; when the data corresponding to the fourth data address is determined to be in the buffer, the data is used as data required to be acquired by the processor and fed back to the processor;
the second controller is used for judging whether a third data address corresponding to a third read command exists in an address mapping relation after receiving the third read command sent by the processor; after determining that a third data address corresponding to the third read command exists in the address mapping relationship, determining a fourth data address corresponding to the third data address according to the address mapping relationship; sending the determined fourth data address to a buffer;
a second processor for sending a third read command to the controller; and receiving the data fed back by the buffer.
Drawings
FIG. 1 is a diagram illustrating a system-on-chip architecture in the prior art;
fig. 2a is a schematic flowchart of a method for feeding back data according to an embodiment of the present invention;
fig. 2b is a schematic diagram illustrating an address mapping relationship between a first data address and a second data address according to an embodiment of the present invention;
fig. 2c is a schematic diagram illustrating an address mapping relationship between a first data address and a second data address according to another embodiment of the present invention;
FIG. 3 is a block diagram of a system on a chip according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of another method for feeding back data according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a buffer for feeding back data according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a system for feeding back data according to an embodiment of the present invention;
FIG. 7 is a flow chart illustrating another method for feeding back data according to an embodiment of the present invention;
FIG. 8 is a flow chart illustrating another method for feeding back data according to an embodiment of the present invention;
fig. 9 is a schematic flowchart of another method for feeding back data according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a controller for feeding back data according to an embodiment of the present invention;
FIG. 11 is a diagram illustrating another exemplary buffer structure for feedback data according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of another system for feeding back data according to an embodiment of the present invention.
Detailed Description
After receiving a first read command sent by a processor through a controller, a buffer judges whether a first data address corresponding to the first read command exists in an address mapping relation; after determining that a first data address corresponding to the first read command exists in the address mapping relationship, the buffer determines a second data address corresponding to the first data address according to the address mapping relationship; and when the buffer determines that the data corresponding to the second data address is in the buffer, the data is used as the data required to be acquired by the processor and is fed back to the processor. According to the embodiment of the invention, the buffer determines the second data address corresponding to the first data address after determining that the first data address corresponding to the first read command exists in the address mapping relation according to the received first read command sent by the processor through the controller and the address mapping relation, and feeds back the data to the processor when determining that the data corresponding to the second data address is stored in the buffer.
The embodiments of the present invention will be described in further detail with reference to the drawings attached hereto.
As shown in fig. 2a, a method for feeding back data according to an embodiment of the present invention includes:
According to the embodiment of the invention, part of data on the external memory is stored on the buffer, so that the processor can conveniently acquire the data on the buffer.
The buffer of the embodiment of the invention can establish the address mapping relation by the following method:
optionally, before receiving the first read command sent by the processor through the controller, the buffer further includes:
and the buffer establishes the address mapping relation according to the received first data address and the second data address.
In the embodiment of the present invention, the address space to which the first data address belongs may be a larger virtual address space requested by the processor, the second data address may be a physical address space of the external memory, and the address mapping relationship between the first data address and the second data address may be shown in fig. 2 b.
As shown in fig. 2b, an address mapping relationship between a first data address and a second data address provided in the embodiment of the present invention is schematically illustrated. As can be seen from fig. 2b, the page size of the first data address is 1M Bytes, the size of the address space to which the first data address belongs is 4G Bytes, and the size of the address space to which the second data address belongs is 5M Bytes; the first data address of the 1 st 1M Bytes is mapped to the second data address of the 2 nd 1M Bytes, the first data address of the 2 nd 1M Bytes is mapped to the second data address of the 1 st 1M Bytes, the first data address of the 3 rd 1M Bytes is mapped to the second data address of the 5 th 1M Bytes, the first data address of the 1537 th 1M Bytes is mapped to the second data address of the 3 rd 1M Bytes, and the first data address of the 1538 th 1M Bytes is mapped to the second data address of the 4 th 1M Bytes.
In fig. 2b, if only 0.5M Bytes of data are stored in the second data address of the 1 st 1M Bytes, in order to more reasonably utilize the external storage space, the subsequent data may be stored from the space of the second data address of the 1 st 1M Bytes where no data is stored, and after the storage location of the data is changed, the address mapping relationship between the first data address and the second data address is also changed, which may be specifically shown in fig. 2 c.
As shown in fig. 2c, an address mapping relationship between a first data address and a second data address is further provided in the embodiment of the present invention. As can be seen from fig. 2c, the page size of the first data address is 1M Bytes, the size of the address space to which the first data address belongs is 4G Bytes, and the size of the address space to which the second data address belongs is 5M Bytes; the first data address of the 1 st 1M Bytes is mapped to the second data address of the 1 st 1M Bytes and the second data address of the 2 nd 1M Bytes of the portion, the first data address of the 2 nd 1M Bytes is mapped to the second data address of the 1 st 1M Bytes of the portion, the first data address of the 3 rd 1M Bytes is mapped to the second data address of the 4 th 1M Bytes and the second data address of the 5 th 1M Bytes of the portion, the first data address of the 1537 th 1M Bytes is mapped to the second data address of the 2 nd 1M Bytes and the second data address of the 3 rd 1M Bytes of the portion, and the first data address of the 1538 th 1M Bytes is mapped to the second data address of the 3 rd 1M Bytes and the second data address of the 4 th 1M Bytes of the portion.
In the address mapping relationship of the embodiment of the present invention, there may be a first data address corresponding to the first read command, and there may also be no first data address corresponding to the first read command, and when there is no first data address corresponding to the first read command, corresponding processing is performed, and a specific implementation manner is:
optionally, after the determining, by the buffer, whether a first data address corresponding to the first read command exists in an address mapping relationship, the method further includes:
and after determining that the first data address corresponding to the first read command does not exist in the address mapping relationship, the buffer processes the first read command according to the type of the first read command.
The embodiment of the invention can perform corresponding processing according to the type of the first read command, and the specific processing mode is as follows:
the first method is as follows:
the first read command is a read instruction command, and the buffer informs the processor of exception handling;
after receiving a notification of exception handling, the processor updates the address mapping relationship according to the obtained first data address corresponding to the first read command and the obtained second data address corresponding to the first data address;
and the processor sends a first read command corresponding to the first data address to the buffer through the controller.
In the embodiment of the present invention, when the address mapping relationship does not have the first data address corresponding to the first read command, and the first read command is a read command, the buffer notifies the processor to perform exception handling, and the specific notification manner is as follows: the buffer sends an abnormal instruction to the processor, and the processor performs corresponding abnormal processing according to the abnormal instruction; after receiving the abnormal instruction, the processor stores a first data address corresponding to the current first read command in the specific register, and in the process of exception handling, searches the first data address and a second data address corresponding to the first data address from an integrated address mapping relation table in the memory according to the first data address stored in the specific register, then updates the address mapping relation, so that the first data address exists in the updated address mapping relation, and finally sends the first read command corresponding to the first data address to the buffer through the controller, and at this time, the buffer can search the second data address corresponding to the first data address in the address mapping relation.
When the processor updates the address mapping relationship, the processor of the embodiment of the invention can replace the original mapping relationship and can also add a new mapping relationship.
The second method comprises the following steps:
the first read command is a read data command, and the buffer records a first data address corresponding to the first read command and a first data address corresponding to the next first read command when the first read command is a read instruction command.
In the embodiment of the present invention, when the address mapping relationship does not have the first data address corresponding to the first read command, and the first read command is a read data command, the buffer records the first data address and the first data address corresponding to the next first read command when the first read command is a read command, so as to perform the later-stage debugging and positioning according to the recorded first data addresses corresponding to the two first read commands at two different times.
In the embodiment of the present invention, the data corresponding to the second address may be stored in the buffer, or may not be stored in the buffer, and when the data corresponding to the second address is not stored in the buffer, the buffer performs the following processing:
optionally, after the buffer determines a second data address corresponding to the first data address, the method further includes:
when the buffer determines that the data corresponding to the second data address is not in the buffer, sending a second read command to the external memory;
and the buffer feeds back data corresponding to the second data address in the data corresponding to the second read command fed back by the external memory to the processor as data required to be acquired by the processor.
After receiving the data corresponding to the second read command fed back by the external memory, the buffer in the embodiment of the present invention may only feed back the data corresponding to the second data address in the data corresponding to the second read command to the processor, or may feed back the data corresponding to the second data address in the data corresponding to the second read command to the processor, and store the data corresponding to the second read command, where the specific implementation manner is:
optionally, after the buffer feeds back, as data that needs to be acquired by the processor, data corresponding to the second data address in the data corresponding to the second read command that is fed back by the external memory to the processor, the method further includes:
and the buffer stores the data corresponding to the second read command fed back by the external memory into the buffer.
The buffer in the embodiment of the invention can feed back the data corresponding to the second data address in the data corresponding to the second read command to the processor, and simultaneously store the data corresponding to the second read command in the buffer; or after feeding back the data corresponding to the second data address in the data corresponding to the second read command to the processor, storing the data corresponding to the second read command in the buffer.
In the embodiment of the invention, after the data corresponding to the second read command is stored in the buffer, the processor can conveniently acquire the data.
As shown in fig. 3, a schematic structural diagram of a system on chip according to an embodiment of the present invention is shown in fig. 3, where the system on chip includes: bus Bridge, CPU, Memory Controller, ROM, Data RAM, SPI Cache (Serial peripheral Interface), SPI Controller, AHB Device 0, AHB Device1, AHB Device 2, APB Device 0, APB Device1, APB Device 2, APB Device 3 and DMA Controller.
In fig. 3, when data needs to be acquired, the CPU sends a read command to the SPI Cache through the Memory Controller; the SPI Cache judges whether a first data address corresponding to a received read command exists in an address mapping relation, determines a second data address corresponding to the first data address (the second data address is a physical address of an external memory) according to the address mapping relation when the first data address exists, then determines whether data corresponding to the second data address are stored in the SPI Cache, and feeds the data back to the CPU when the data corresponding to the second data address are determined to be stored in the SPICache; and after receiving the data, the CPU executes corresponding processing according to the data.
As shown in fig. 4, another method for feeding back data according to an embodiment of the present invention includes:
in step 400, the processor sends a first read command to the buffer via the controller.
In step 401, before the buffer receives a first read command sent by the processor through the controller, an address mapping relationship is established according to the received first data address and the second data address.
And step 404, the buffer feeds back the data corresponding to the second data address to the processor.
And step 405, ending the process.
In step 409, in the system on chip as shown in fig. 3, the buffer needs to send a second read command to the external memory through the SPI Controller.
And step 410, the external memory sends data corresponding to the second read command to the buffer.
In step 411, the buffer feeds back data corresponding to the second data address in the data corresponding to the second read command fed back from the external memory to the processor, and step 405 is executed.
In step 411, after feeding back the data to the processor, the buffer may store the data corresponding to the second read command in the buffer; or the data corresponding to the second read command can be stored in the buffer while the data is fed back to the processor.
Based on the same inventive concept, embodiments of the present invention further provide a buffer for feeding back data and a system for feeding back data, because the method corresponding to the buffer for feeding back data in fig. 5 is a method for feeding back data in embodiments of the present invention, and because the method corresponding to the system for feeding back data in fig. 6 is a method for feeding back data in embodiments of the present invention, the implementation of the buffer and the system in embodiments of the present invention may refer to the implementation of the method, and repeated parts are not described again.
As shown in fig. 5, a buffer for feedback data according to an embodiment of the present invention includes:
a first determining module 500, configured to determine whether a first data address corresponding to a first read command exists in an address mapping relationship after receiving the first read command sent by a controller through a processor;
a first determining module 501, configured to determine, after determining that a first data address corresponding to the first read command exists in the address mapping relationship, a second data address corresponding to the first data address according to the address mapping relationship;
a first feedback module 502, configured to, when it is determined that the data corresponding to the second data address is in the buffer, feed back the data to the processor as the data that needs to be obtained by the processor.
Preferably, the first determining module 500 is further configured to:
and establishing the address mapping relation according to the received first data address and the second data address.
Preferably, the first determining module 500 is further configured to:
and processing the first read command according to the type of the first read command after determining that the first data address corresponding to the first read command does not exist in the address mapping relation.
Preferably, the first determining module 500 is specifically configured to:
the first read command is a read instruction command and informs the processor of carrying out exception handling; after receiving the notification of exception handling, the processor updates the address mapping relationship according to the obtained first data address corresponding to the first read command and the obtained second data address corresponding to the first data address, and sends the first read command corresponding to the first data address to the buffer through the controller; or the first read command is a read data command, and a first data address corresponding to the first read command and a first data address corresponding to the next first read command when the first read command is a read instruction command are recorded.
Preferably, the first feedback module 502 is further configured to:
when the data corresponding to the second data address is determined not to be in the buffer, sending a second read command to the external memory; feeding back data corresponding to the second data address in the data corresponding to the second read command fed back by the external memory to the processor; and storing data corresponding to the second read command fed back by the external memory into the buffer.
As shown in fig. 6, a system for feeding back data according to an embodiment of the present invention includes:
a first buffer 600, configured to determine, after receiving a first read command sent by a first controller, whether a first data address corresponding to the first read command exists in an address mapping relationship; after determining that a first data address corresponding to the first read command exists in the address mapping relationship, determining a second data address corresponding to the first data address according to the address mapping relationship; when the data corresponding to the second data address is determined to be in the buffer, the data is used as the data required to be acquired by the processor and is fed back to the processor;
a first controller 601, configured to send the first read command received from the first processor to the first buffer;
a first processor 602, configured to send the first read command to the first controller.
In summary, in the embodiment of the present invention, after determining that the first data address corresponding to the first read command exists in the address mapping relationship according to the received first read command sent by the processor through the controller and the address mapping relationship, the buffer determines the second data address corresponding to the first data address, and when determining that the data corresponding to the second data address is stored in the buffer, the data is fed back to the processor.
As shown in fig. 7, another method for feeding back data according to an embodiment of the present invention includes:
The controller of the embodiment of the invention can establish the address mapping relation by the following method:
optionally, before receiving the third read command sent by the processor, the controller further includes:
and the controller establishes the address mapping relation according to the received third data address and the fourth data address.
In the embodiment of the present invention, the address space to which the third data address belongs may be a larger virtual address space requested by the processor, the fourth data address may be a physical address space of the external memory, and the address mapping relationship between the third data address and the fourth data address may be as shown in fig. 2b, where the third data address is equivalent to the first data address in fig. 2b, and the fourth data address is equivalent to the second data address in fig. 2 b.
In the address mapping relationship of the embodiment of the present invention, there may be a third data address corresponding to the third read command, and there may also be no third data address corresponding to the third read command, and when there is no third data address corresponding to the third read command, corresponding processing is performed, and a specific implementation manner is:
optionally, after the controller determines whether a third data address corresponding to the third read command exists in the address mapping relationship, the method further includes:
and after determining that the third data address corresponding to the third read command does not exist in the address mapping relationship, the controller processes the third read command according to the type of the third read command.
The embodiment of the present invention performs corresponding processing according to the type of the third read command, and the specific processing manner is as follows:
the first method is as follows:
the third read command is a read instruction command, and the controller informs the processor of exception handling;
after receiving the notification of exception handling, the processor updates the address mapping relationship according to the obtained third data address corresponding to the third read command and the obtained fourth data address corresponding to the third data address;
and the processor sends a third read command corresponding to the third data address to the controller.
In the embodiment of the present invention, when the address mapping relationship does not have the third data address corresponding to the third read command, and the third read command is a read command, the controller may notify the processor of exception handling, where the specific notification manner is: the controller sends an abnormal instruction to the processor so that the processor performs corresponding abnormal processing according to the abnormal instruction; after receiving the exception instruction, the processor stores a third data address corresponding to a current third read command in the specific register, and during exception handling, searches for the third data address and a fourth data address corresponding to the third data address from an integrated address mapping relation table in the memory according to the third data address stored in the specific register, then updates the address mapping relation, so that the third data address exists in the updated address mapping relation, and finally sends the third read command corresponding to the third data address to the controller, and at this time, the controller can search for the fourth data address corresponding to the third data address in the address mapping relation.
When the processor updates the address mapping relationship, the processor of the embodiment of the invention can replace the original mapping relationship and can also add a new mapping relationship.
The second method comprises the following steps:
the third read command is a read data command, and the controller records a third data address corresponding to the third read command and a third data address corresponding to the next third read command when the third read command is a read instruction command.
In the embodiment of the present invention, when the address mapping relationship does not have the third data address corresponding to the third read command, and the third read command is a read data command, the controller records the third data address and the third data address corresponding to the next third read command when the third read command is a read command, so as to perform the later-stage debugging and positioning according to the recorded third data addresses corresponding to the two third read commands at two different times.
As shown in fig. 8, another method for feeding back data according to an embodiment of the present invention includes:
and 801, when determining that the data corresponding to the fourth data address is in the buffer, feeding back the data to the processor as the data required to be acquired by the processor by using the buffer.
In the embodiment of the present invention, the data corresponding to the fourth address may be stored in the buffer, or may not be stored in the buffer, and when the data corresponding to the fourth address is not stored in the buffer, the buffer performs the following processing:
optionally, after the buffer receives the fourth data address sent by the controller, the method further includes:
when the buffer determines that the data corresponding to the fourth data address is not in the buffer, the buffer sends a fourth read command to an external memory;
and the buffer feeds back data corresponding to the fourth data address in the data corresponding to the fourth read command fed back by the external memory to the processor.
After receiving the data corresponding to the fourth read command fed back by the external memory, the buffer in the embodiment of the present invention may only feed back the data corresponding to the fourth data address in the data corresponding to the fourth read command to the processor, or may feed back the data corresponding to the fourth data address in the data corresponding to the fourth read command to the processor, and store the data corresponding to the fourth read command, where the specific implementation manner is:
optionally, after feeding back, by the buffer, data corresponding to the fourth data address in the data corresponding to the fourth read command fed back by the external memory to the processor, the method further includes:
and the buffer stores the data corresponding to the fourth read command fed back by the external memory into the buffer.
The buffer of the embodiment of the invention can feed back the data corresponding to the fourth data address in the data corresponding to the fourth read command to the processor, and simultaneously store the data corresponding to the fourth read command in the buffer; or after feeding back the data corresponding to the fourth data address in the data corresponding to the fourth read command to the processor, storing the data corresponding to the fourth read command in the cache.
In fig. 3, when data needs to be acquired, the CPU sends a read command to the Memory Controller; the memory controller judges whether a third data address corresponding to the received read command exists in the address mapping relation, determines a fourth data address corresponding to the third data address (the fourth data address is a physical address of an external memory) according to the address mapping relation when the third data address exists, and then sends the fourth data address to the SPI Cache; the SPI Cache determines whether data corresponding to the fourth data address are stored in the SPI Cache according to the received fourth data address, and feeds the data back to the CPU when the data corresponding to the fourth data address are determined to be stored in the SPI Cache; and after receiving the data, the CPU executes corresponding processing according to the data.
As shown in fig. 9, another method for feeding back data according to an embodiment of the present invention includes:
In step 901, before receiving a third read command sent by the processor, the controller establishes an address mapping relationship according to the received third data address and the fourth data address.
And step 902, the controller determines a fourth data address corresponding to the third data address according to the address mapping relationship.
And step 906, the process is finished.
In step 909, the controller records the third data address corresponding to the third read command and the third data address corresponding to the next third read command as the read command, and executes step 906.
In step 910, in the system on chip as shown in FIG. 3, the buffer needs to send a fourth read command to the external memory through the SPI Controller.
And 911, sending the data corresponding to the fourth read command to the buffer by the external memory.
In step 912, after feeding back the data to the processor, the buffer may store the data corresponding to the fourth read command in the buffer; or the data corresponding to the fourth read command may be stored in the buffer while the data is fed back to the processor.
Based on the same inventive concept, embodiments of the present invention further provide a controller, a buffer and a system for feeding back data, where a method corresponding to the controller for feeding back data in fig. 10 is a method for feeding back data in an embodiment of the present invention, a method corresponding to the buffer for feeding back data in fig. 11 is a method for feeding back data in an embodiment of the present invention, and a method corresponding to the system for feeding back data in fig. 12 is a method for feeding back data in an embodiment of the present invention, so that reference may be made to the implementation of the method for implementing the controller, the buffer and the system in an embodiment of the present invention, and repeated details are omitted.
As shown in fig. 10, a controller for feeding back data according to an embodiment of the present invention includes:
a second determining module 1000, configured to determine, after receiving a third read command sent by the processor, whether a third data address corresponding to the third read command exists in an address mapping relationship;
a second determining module 1001, configured to determine, after determining that a third data address corresponding to the third read command exists in the address mapping relationship, a fourth data address corresponding to the third data address according to the address mapping relationship;
a sending module 1002, configured to send the determined fourth data address to a buffer.
Preferably, the second determining module 1000 is further configured to:
and establishing the address mapping relation according to the received third data address and the fourth data address.
Preferably, the second determining module 1000 is further configured to:
and processing the third read command according to the type of the third read command after determining that the third data address corresponding to the third read command does not exist in the address mapping relation.
Preferably, the second determining module 1000 is further configured to:
the third read command is a read instruction command and informs the processor of carrying out exception handling; after receiving the notification of performing exception handling, the processor updates the address mapping relationship according to the obtained third data address corresponding to the third read command and the obtained fourth data address corresponding to the third data address, and sends a third read command corresponding to the third data address to the controller; or the third read command is a read data command, and a third data address corresponding to the third read command and a third data address corresponding to the next third read command when the third read command is a read instruction command are recorded.
As shown in fig. 11, another buffer for feedback data according to an embodiment of the present invention includes:
a receiving module 1100, configured to receive a fourth data address sent by the controller;
the second feedback module 1101 is configured to, when it is determined that the data corresponding to the fourth data address is in the buffer, feed back the data to the processor as data that needs to be acquired by the processor.
Preferably, the second feedback module 1101 is further configured to:
when the data corresponding to the fourth data address is determined not to be in the buffer, sending a fourth read command to an external memory; feeding back data corresponding to the fourth data address in the data corresponding to the fourth read command fed back by the external memory to the processor; and storing data corresponding to the fourth read command fed back by the external memory into the buffer.
As shown in fig. 12, another system for feeding back data according to an embodiment of the present invention includes:
a second buffer 1200, configured to receive a fourth data address sent by the controller; when the data corresponding to the fourth data address is determined to be in the buffer, the data is used as data required to be acquired by the processor and fed back to the processor;
the second controller 1201 is configured to, after receiving a third read command sent by the processor, determine whether a third data address corresponding to the third read command exists in an address mapping relationship; after determining that a third data address corresponding to the third read command exists in the address mapping relationship, determining a fourth data address corresponding to the third data address according to the address mapping relationship; sending the determined fourth data address to a buffer;
a second processor 1202 for sending a third read command to the controller; and receiving the data fed back by the buffer.
In summary, in the embodiment of the present invention, when the buffer determines that the data corresponding to the fourth data address is stored in the buffer according to the received fourth data address sent by the controller, the data is fed back to the processor, and the system on chip only needs to design a buffer with a smaller storage capacity, and does not need to design a large amount of Code RAMs, so that the operation of different operation scenarios can be realized, and the integration level of the system on chip is improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method of feeding back data, the method comprising:
after receiving a first read command sent by a processor through a controller, a buffer judges whether a first data address corresponding to the first read command exists in an address mapping relation;
after determining that the first data address corresponding to the first read command does not exist in the address mapping relationship, the buffer processes the first read command according to the type of the first read command;
wherein, the buffer processes the first read command according to the type of the first read command, including:
the first read command is a read instruction command, the buffer informs the processor of exception handling, so that after receiving the notification of exception handling, the processor updates the address mapping relationship according to a first data address corresponding to the first read command and a second data address corresponding to the first data address, and sends the first read command corresponding to the first data address to the buffer through the controller;
the first read command is a read data command, and the buffer records a first data address corresponding to the first read command and a first data address corresponding to the next first read command when the first read command is a read instruction command.
2. The method of claim 1, wherein the buffer, prior to receiving a first read command sent by the processor through the controller, further comprises:
and the buffer establishes the address mapping relation according to the received first data address and the second data address.
3. A buffer for feedback data, the buffer comprising:
the first judging module is used for judging whether a first data address corresponding to a first read command exists in an address mapping relation after receiving the first read command sent by a processor through a controller;
a first determining module, configured to process the first read command according to a type of the first read command after determining that the first data address corresponding to the first read command does not exist in the address mapping relationship;
after determining that the first data address corresponding to the first read command does not exist in the address mapping relationship, if the first read command is a read instruction command, specifically, notifying the processor of exception handling, so that after receiving the notification of exception handling, the processor updates the address mapping relationship according to the obtained first data address corresponding to the first read command and the obtained second data address corresponding to the first data address, and sends the first read command corresponding to the first data address to the buffer through the controller; the first read command is a read data command, and is specifically configured to record a first data address corresponding to the first read command and a first data address corresponding to a next first read command when the first read command is a read instruction command.
4. The cache of claim 3, wherein the first determination module is further to:
and establishing the address mapping relation according to the received first data address and the second data address.
5. A system for feeding back data, the system comprising:
the first buffer is used for judging whether a first data address corresponding to a first read command exists in an address mapping relation after receiving the first read command sent by a first controller;
after determining that a first data address corresponding to the first read command does not exist in the address mapping relationship, processing the first read command according to the type of the first read command;
after determining that the first data address corresponding to the first read command does not exist in the address mapping relationship, the first cache is specifically configured to:
if the first read command is a read instruction command, notifying a first processor to perform exception handling, so that after receiving the notification of performing exception handling, the first processor updates the address mapping relationship according to an obtained first data address corresponding to the first read command and an obtained second data address corresponding to the first data address; sending a first read command corresponding to the first data address to the first buffer through the first controller; if the first read command is a read data command, recording a first data address corresponding to the first read command and a first data address corresponding to the next first read command when the first read command is a read instruction command;
the first controller is used for sending the received first read command from the first processor to the first buffer;
a first processor to send the first read command to the first controller.
6. A method of feeding back data, the method comprising:
after receiving a third read command sent by a processor, the controller judges whether a third data address corresponding to the third read command exists in an address mapping relation;
after determining that a third data address corresponding to the third read command does not exist in the address mapping relationship, the controller processes the third read command according to the type of the third read command;
wherein the controller processes the third read command according to the type of the third read command, including:
the third read command is a read instruction command, and the controller notifies the processor of exception handling, so that after receiving the notification of exception handling, the processor updates the address mapping relationship according to an obtained third data address corresponding to the third read command and a fourth data address corresponding to the third data address, and sends a third read command corresponding to the third data address to the controller;
the third read command is a read data command, and the controller records a third data address corresponding to the third read command and a third data address corresponding to the next third read command when the third read command is a read instruction command.
7. The method of claim 6, wherein the controller, prior to receiving a third read command sent by the processor, further comprises:
and the controller establishes the address mapping relation according to the received third data address and the fourth data address.
8. A controller for feeding back data, the controller comprising:
the second judging module is used for judging whether a third data address corresponding to a third read command exists in an address mapping relation after receiving the third read command sent by the processor;
a second determining module, configured to, after determining that a third data address corresponding to the third read command does not exist in the address mapping relationship, process the third read command according to a type of the third read command;
after determining that a third data address corresponding to the third read command does not exist in the address mapping relationship, the third read command is a read instruction command, and the second determining module is specifically configured to notify the processor of performing exception handling, so that after receiving the notification of performing exception handling, the processor updates the address mapping relationship according to the obtained third data address corresponding to the third read command and a fourth data address corresponding to the third data address, and sends a third read command corresponding to the third data address to the controller; the second determining module is specifically configured to record a third data address corresponding to the third read command and a third data address corresponding to a next third read command when the third read command is a read command.
9. The controller of claim 8, wherein the second determining module is further configured to:
and establishing the address mapping relation according to the received third data address and the fourth data address.
10. A system for feeding back data, the system comprising:
the second controller is used for judging whether a third data address corresponding to a third read command exists in an address mapping relation after receiving the third read command sent by the second processor; processing the third read command according to the type of the third read command after determining that the third data address corresponding to the third read command does not exist in the address mapping relation; after determining that a third data address corresponding to the third read command does not exist in the address mapping relationship, the third read command is a read instruction command, and the second controller is specifically configured to notify the second processor of exception handling; after receiving the notification of performing exception handling, the second processor updates the address mapping relationship according to the obtained third data address corresponding to the third read command and the obtained fourth data address corresponding to the third data address, and sends a third read command corresponding to the third data address to the second controller; the second controller is specifically configured to record a third data address corresponding to the third read command and a third data address corresponding to a next third read command when the third read command is a read command;
the second processor is configured to send a third read command to the second controller.
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