WO2017054132A1

WO2017054132A1 - Method for generating address and data processing device

Info

Publication number: WO2017054132A1
Application number: PCT/CN2015/091079
Authority: WO
Inventors: 汪涛; 张广飞; 宋风龙
Original assignee: 华为技术有限公司
Priority date: 2015-09-29
Filing date: 2015-09-29
Publication date: 2017-04-06
Also published as: CN107580700A; CN107580700B

Abstract

A method for generating an address and a data processing device, related to the technical field of storage and used to solve the current technical problem that an access and storage instruction occupies a large amount of storage space. A memory comprises a first recirculation region and a second recirculation region. When a first operation instruction regarding the second recirculation region is received, an initial address of the first recirculation region can be modified by means of a second step value corresponding to the second recirculation region, in addition to executing the first operation instruction. When the next clock period arrives, an address corresponding to the operation instruction received this time can be obtained; that is, when the operation instruction regarding the first recirculation region or the second recirculation region is received again next time, an operation can be performed directly according to the address obtained last time, without the need of carrying a destination address in the operation instruction. Consequently, the quantity of codes of the instruction is reduced, it is not necessary to consume a large amount of storage space to store the codes, and at the same time, the programming burden of programming personnel is also reduced.

Description

Method for generating address and data processing device

Technical field

The present invention relates to the field of storage technologies, and in particular, to a method for generating an address and a data processing device.

Background technique

Today's applications are capable of performing increasingly powerful functions, processing more and more data, for example, data-intensive applications are now appearing. The so-called data-intensive refers to the storage and calculation of massive data, and its corresponding applications are widely used in many fields such as the World Wide Web, scientific computing and artificial intelligence. Especially after entering the 21st century, with the rapid development of mobile Internet, cloud computing and Internet of Things, the global information volume has grown exponentially, and data-intensive application storms are taking shape.

Data-intensive applications are frequently accessed, and the access rules are not obvious, not a simple linear growth. In the existing memory access system, each instruction needs to explicitly indicate the destination address of the memory access operation, which makes the memory access instruction occupy a large amount of storage space. At the same time, when programmers are programming, each instruction needs to take care of the memory address, which also increases the burden on the programmer.

Summary of the invention

The embodiment of the invention provides a method for generating an address and a data processing device, which are used to solve the technical problem that the current memory access instruction occupies a large amount of storage space.

In a first aspect, a method for generating an address is provided, including:

Receiving a first operational instruction for a second recirculation region in the memory;

Executing the first operation instruction, and modifying a start address of the first recirculation area in the memory by using a second step value corresponding to the second recirculation area, to obtain an operation instruction corresponding to the next reception An address; wherein the first recirculation region cyclically moves in the second recirculation region according to the second step value.

With reference to the first aspect, in a first possible implementation, the first operation instruction is executed, and the first re-circulation in the memory is modified by a second step value corresponding to the second re-circulation area The starting address of the ring area to get the address corresponding to the next received operation command, including:

Executing the first operation instruction, modifying a start address of the first recirculation area in the memory by using a second step value corresponding to the second recirculation area, and corresponding to the first recirculation area The first step value modifies an internal offset address of the first recirculation region to obtain an address corresponding to an operation instruction received next time.

In conjunction with the first possible implementation of the first aspect, in a second possible implementation of the first aspect,

Modifying a starting address of the first re-circulation area in the memory by using a second step value corresponding to the second re-circulation area, including:

Modifying, by the second step value corresponding to the second recirculation region, an address pointed by the second pointer corresponding to the second recirculation region;

Modifying an internal offset address of the first re-circulation area by using a first step value corresponding to the first re-circulation area, including:

And modifying, by the first step value corresponding to the first recirculation region, an address pointed by the first pointer corresponding to the first recirculation region.

With reference to the second possible implementation of the first aspect, in a third possible implementation manner of the first aspect, the address corresponding to the next received operation instruction is obtained, including:

Adding a first pointer to an address pointed by the first step value to perform a modulo operation with a length of the first recirculation region, and adding the second pointer to the second step value Performing a modulo operation on the address pointed to and the length of the second recirculation region;

Adding the obtained results of the two modulo, and performing a modulo operation on the added result and the length of the second recirculation region;

The result obtained by modulating the length of the second recirculation area is added to the initialization address of the cyclic storage area to obtain an address corresponding to the next received operation instruction.

With reference to the first aspect or the first possible implementation of the first aspect to any one of the third possible implementation manners, in a fourth possible implementation manner of the first aspect, The method also includes:

Receiving a second operation instruction for the first recirculation region;

Executing the second operation instruction, and modifying an internal offset address of the first re-circulation area by using a first step value corresponding to the first re-circulation area to obtain an address corresponding to an operation instruction received next time.

With reference to the first aspect or the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, The internal offset address of a recirculating area to obtain the address corresponding to the next received operation instruction, including:

The address pointed by the first pointer corresponding to the first re-circulation area is modified by the first step value corresponding to the first re-circulation area to obtain an address corresponding to the next received operation instruction.

With reference to the first aspect or the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the address corresponding to the next received operation instruction is obtained, including:

Adding the first pointer to an address pointed by the first step value and performing a modulo operation on the length of the first recirculation region, and adding the obtained result to the address pointed by the second pointer, And performing a modulo operation on the added result and the length of the second recirculation region;

With reference to the first aspect or the first possible implementation manner of the first aspect to the sixth possible implementation manner, in the seventh possible implementation manner of the first aspect, Before the first operation instruction, it also includes:

And performing, by using a dedicated instruction, a length of the first recirculation area, a length of the second recirculation area, a first step value corresponding to the first recirculation area, and a corresponding corresponding to the second recirculation area The second step value and the start address of the cyclic storage area are initialized.

In a second aspect, a data processing device is provided, including:

a memory including a first recirculation area and a second recirculation area;

a control unit, coupled to the memory, for receiving a first operation instruction for a second recirculation region in the memory; executing the first operation instruction, and passing the second recirculation region pair The second step value should modify the start address of the first re-circulation area in the memory to obtain an address corresponding to the next received operation instruction; wherein the first re-circulation area is according to the second step The value is cyclically moved in the second recirculation region.

In conjunction with the second aspect, in a first possible implementation of the second aspect, the control unit is configured to:

In conjunction with the first possible implementation of the second aspect, in a second possible implementation of the second aspect, the control unit is configured to:

Modifying, by the second step value corresponding to the second recirculation region, an address pointed by the second pointer corresponding to the second recirculation region; and

In conjunction with the second possible implementation of the second aspect, in a third possible implementation of the second aspect, the control unit is configured to:

With reference to the second aspect, or the first possible implementation of the second aspect, to any one of the third possible implementation manners, in a fourth possible implementation manner of the second aspect, The control unit is also used to:

Receiving a second operation instruction for the first recirculation region;

In conjunction with the fourth possible implementation of the second aspect, in a fifth possible implementation of the second aspect, the control unit is configured to:

In conjunction with the fifth possible implementation of the second aspect, in a sixth possible implementation of the second aspect, the control unit is configured to:

With reference to the second aspect or the first possible implementation manner of the second aspect, the possible implementation manner of the sixth possible implementation manner, in the seventh possible implementation manner of the second aspect, The device further includes a control register, configured to store a length of the first recirculation region, a length of the second recirculation region, a first step value corresponding to the first recirculation region, and the second recirculation a second step value corresponding to the area, and a start address of the cyclic storage area; the control unit is configured to:

The length of the first recirculation region, the length of the second recirculation region, the first step value, the second step value, and the stored in the control register by executing a dedicated instruction The start address of the cyclic storage area is initialized.

In the embodiment of the present invention, the memory includes a first re-circulation area and a second re-circulation area. When receiving an operation instruction (referred to as a first operation instruction) for the second re-circulation area, in addition to executing the first operation instruction, The first re-routing can also be modified by the second step value corresponding to the second recirculation region The start address of the ring region can obtain the address corresponding to the received operation command when the next clock cycle arrives, that is, the next time the operation command for the first recirculation region or the second recirculation region is received again, Directly according to the last obtained address, there is no need to carry the destination address in the operation instruction, which reduces the code amount of the instruction, does not require a large amount of storage space for storing the code, and also reduces the programming burden of the programmer.

The embodiment of the present invention provides a double loop area (ie, a first recirculation area and a second recirculation area), and the first recirculation area can be cyclically moved in the second recirculation area, so that automatic loop addressing can be realized and stored. The use of the area is more flexible and can also improve the utilization of the storage area.

DRAWINGS

1 is a schematic structural diagram of a data processing device according to an embodiment of the present invention;

2 is a schematic structural diagram of an RCU according to an embodiment of the present invention;

3 is a schematic diagram of an addressing area of a storage space according to an embodiment of the present invention;

FIG. 4 is a flowchart of a method for generating an address according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

First, the application scenario and hardware architecture of the present invention are introduced.

Referring to FIG. 1, an embodiment of the present invention provides a data processing device, which can be used to perform a method for generating an address in an embodiment of the present invention. The data processing device may for example be a processor, such as may be a CPU (Central Processing Unit), or may be, for example, a sub-module in a processor, or the like. The data processing device can include a memory 101 and a control unit.

A memory (or storage entity) 101 may be a storage medium such as an RF (Register File) or an SRAM (Static Random Access Memory). Implementation, in Figure 1, take RF as an example. The memory 101 is used to store data. In the embodiment of the present invention, the storage area of the memory 101 may include a first re-circulation area and a second re-circulation area, where the first re-circulation area may include at least one sub-storage space, and the length of the second re-circulation area is greater than or equal to The length of the first recirculation region, if the first recirculation region is regarded as a whole, the first recirculation region may be cyclically moved as a whole in the second recirculation region.

For example, the memory 101 is composed of RF, and each register can correspond to a number. For example, the length of the first re-circulation area is 9, and the register 1-register 15 is the second re-circulation area. Then, the register 1-register 9 in the memory 101 can be used as the first re-circulation area, when the first re-circulation area is overall When moving in the second recirculation region, for example, the step value of the overall movement of the first recirculation region (ie, the step value corresponding to the second recirculation region, for example, referred to as the second step value) is 1, then, register 2 The register 10 can be used as the first recirculation area after the first recirculation area is moved, and the register 3-register 11 can be used as the first re-circulation area after the first re-circulation area is moved again, and so on, that is, the first weight The starting address of the loop area is variable.

If the storage space corresponding to the second re-circulation area is all the storage space in the available storage space in the memory 101, the start address of the second re-circulation area may be considered to be fixed. Alternatively, even if the storage space corresponding to the second re-circulation area is a partial storage space in the available storage space in the memory 101, since the storage space corresponding to the second re-circulation area is fixed, the second weight can also be considered The starting address of the loop area is fixed.

The control unit may also be referred to as a cyclic read/write control circuit, and may include an RCU (Read Control Unit) 1021 and a WCU (Write Control Unit) 1022. The control unit is used to generate index numbers for cyclic reads and cyclic writes in the memory 101, respectively. The RCU 1021 and the WCU 1022 may be located in the same functional module. If the RCU 1021 and the WCU 1022 are located in the same functional module, the functional module may also be referred to as a CU (Control Unit), and the RCU 1021 and the WCU 1022 may be considered as two of the CUs. The sub-modules, or the RCU 1021 and the WCU 1022, may also be located in different functional modules. If the RCU 1021 and the WCU 1022 are located in different functional modules, the hardware structures of the RCU 1021 and the WCU 1022 may be the same, except that the DEC may control the RCU 1021 and the WCU 1022 through different control commands. , in Figure 1, can understand For example, the RCU 1021 and the WCU 1022 are located in the CU.

Optionally, please continue to refer to FIG. 1. In another embodiment of the present invention, the data processing device may further include a decoding circuit 103 and a control register 104, wherein the decoding circuit 103 is connected to the control unit, and the control register 104 respectively It is connected to the control unit and decoding circuit 103.

The control register 104 is configured to store the length of the first recirculation region, the length of the second recirculation region, the first step value, the second step value, and the start address of the cyclic storage region. The meaning of these parameters will be described later.

The decoding circuit 103 is configured to: store the length of the first recirculation region, the length of the second recirculation region, the first step value, the second step value, and the cyclic storage stored in the control register 104 by executing a dedicated instruction. The start address of the area is initialized. Wherein, after initializing the start address of the cyclic storage area, the obtained address may be referred to as an initialization address of the cyclic storage area.

Optionally, please continue to refer to FIG. 1. In another embodiment of the present invention, the data processing device may further include an IB (Instruction Buffer) 105 for receiving and temporarily buffering read commands for the data processing device. , write instructions, and control instructions and other types of instructions. In the embodiment of the present invention, the instruction and the operation instruction may be the same concept and are interchangeable.

The decoding circuit 103 is, for example, a DEC (Decode), which can decode the instructions buffered in the IB 105, generate corresponding control signals, and send the control signals to other modules of the data processing device.

The control register 104 is, for example, a CR (Control Register), which can be used to store configuration information for the data processing device. The CR can be configured by a dedicated instruction to complete the configuration, that is, the initialization is completed.

For example, before executing a read command, a write command, or other control command, the CR can be first written by a dedicated configuration command, that is, a dedicated instruction, such as a SetCR Src (representing setting CR with data Src) instruction. For example, the CR includes five bit fields, respectively corresponding to the length of the first recirculation region, the length of the second recirculation region, the first step value, the second step value, and the cycle storage area. The starting address, for example, the length of the first recirculation area is represented by WinLen, the length of the second recirculation area is represented by CirLen, the first step value is represented by Inc, and the second step is represented by Stirde. Value, use Start to indicate the starting address of the cyclic storage area. As shown in Table 1, the parameters corresponding to these bit fields can be initialized by writing to the CR through a dedicated configuration command.

Table 1

Start

CirLen

WinLen

Inc

Stride

In Table 1, the relative positions of the respective bit fields are only for the examples, and may be arranged in any order in the actual case.

In addition, in FIG. 1 , it can be understood that the RCU 1021 and the WCU 1022 are located in different functional modules as an example, or can be understood as being separated from the CU, that is, the RCU 1021 and the WCU 1022 in FIG. 1 are actually Two functional modules in the CU.

In addition, in FIG. 1, the memory 101 may include two interfaces for reading data and two interfaces for writing data. In FIG. 1, the interface for reading data may be represented, for example, as an R interface, and an interface for writing data, for example. It can be represented as a W interface, in which one interface for reading data is cyclically read data in accordance with a method to be described later in the embodiment of the present invention, and another interface for reading data is directed to a method of performing acyclic read data, that is, a method to be described later. The manner of the normal immediate index type, similarly, one of the interfaces for writing data is for the manner of cyclically writing data according to the method to be described later in the embodiment of the present invention, and the other interface for writing data is for the manner of writing data acyclically.

As can be seen from Fig. 1, the two commands Imm Wr and Imm Rd belong to the operation instruction of the ordinary immediate index type. This operation instruction will be described later, and the destination address can be carried in the operation instruction, which can be directly based on this The operation instructions read data or write data in the memory 101.

The two types of instructions, Cyc Wr and Cyc Rd, belong to the instruction of the internal loop index type of the window, or the type of the loop index that belongs to the overall movement of the window, which will be described later. The instruction may not carry the destination address, and may be provided according to the embodiment of the present invention. The loop mode is to read data or write data.

1 is a structure of a possible data processing device. Other possible structures are also within the scope of the present invention, as long as the data processing device can implement the method for generating an address provided in the embodiment of the present invention.

Referring to FIG. 2, based on the same inventive concept and the above embodiments, the embodiment of the present invention The RCU 1021 is an example of a possible internal implementation of the RCU 1021. The hardware structure of the WCU 1022 can be the same as that of the RCU 1021. Alternatively, FIG. 2 can also be understood as the structure of the CU, which is not limited in the present invention.

As shown in FIG. 2, the RCU 1021 is used to generate a read operation instruction to the memory 101, which is commonly controlled by the CR and the operation instructions from the IB 105. RCU1021 is mainly composed of comparator A, comparator B, comparator C, adder D, adder E, adder F, adder G, selector H, selector J, selector K, register I and register S. . The DEC in FIG. 2 is the DEC in FIG. 1, that is, another functional module that does not belong to the RCU 1021. For example, one possible working process of the RCU 1021 in FIG. 2 is as follows.

1. System initialization. For example, when the system starts to work, the values of register I and register S are initialized to 0, respectively. For example, the process may be performed by a CU (or RCU 1021 and WCU 1022), for example, the CU may initialize the values of register I and register S to zero, respectively, upon receiving signaling (or referred to as a control signal) transmitted by the DEC.

2. Set the initial value of each parameter in the CR, that is, initialize each parameter in the CR by a dedicated instruction, such as the SetCR Src instruction. For example, after receiving the SetCR Src command, the DEC generates a control signal, and the CU can initialize each parameter in the CR when receiving the control signal sent by the DEC.

3. When the system receives the loop type instruction, the value of the register I is self-added, and the self-addition result is modulo-operated with the length of the first re-circulation area, and the value of the register S is self-added. The result is modulo operation with the length of the second recirculation region, after which the results of the two modulo operations are added, and the added result is compared with CirLen by the comparator C, and if the two are equal, the operation is obtained. The address of the instruction Addr=Start. If the two are not equal, the address of the operation instruction Addr=S+I+Start is obtained.

Among them, RCU1021 supports two types of loop instructions:

1) The window internal index loop instruction is valid, that is, the operation instruction for the first recirculation area is received. At this time, the adder D corresponding to Inc performs an addition operation, X=I+Inc, and the generated new value X is compared with WinLen through the comparator A. Selector H outputs 0 when X is equal to WinLen, No selector H outputs X. When the register I receives the control signal generated by the DEC, the value of the register I is updated according to the result of the output of the comparator A, that is, if X=I+Inc=WinLen, the update I=0, otherwise the update I=I+ Inc.

2) The window overall index loop instruction is valid, that is, the operation instruction for the second recirculation area is received. Stride's adder B performs the addition operation, Y=S+Stride, and the new value Y generated is compared with CirLen through comparator B. When J is equal to CirLen, selector J outputs 0, and selector J outputs Y. When the register S receives the control signal generated by the DEC, the value of the register S is updated according to the result of the output of the comparator B, that is, if Y=S+Stride=CirLen, the update S=0, otherwise the update S=S+ Stride, and, when the register I receives the control signal generated by the DEC, updates the value of the register I according to the result of the output of the comparator A, that is, if X=I+Inc=WinLen, the update I=0, otherwise update I=I+Inc.

After the operation instruction enters the DEC, the DEC performs decoding to generate a corresponding control signal, and the control signal can control the update of the register S and/or the register I.

FIG. 2 is only one possible example of the structure of the RCU 1021. Other possible configurations of the RCU 1021 are also within the scope of the present invention.

Some of the concepts used in the embodiments of the present invention under the architecture of Figures 1 and 2 are described below.

In the embodiment of the present invention, the addressing area in the storage space is included in the cyclic access area, and the cyclically accessed area may include multiple loops.

Taking the 3-loop index as an example, a method similar to the two-loop is used. In the 3-cycle, the loop index is composed of three loop bodies (ie, three loop regions), which are:

The first re-circulation (external re-circulation): In the cyclic access mode, the length of the loop body is represented by CirLen, for example.

The second heavy loop (intermediate heavy loop): adopts the cyclic access mode. If the second heavy loop body is regarded as a whole, the second heavy loop body can be cyclically moved inside the first heavy loop, and the length of the loop body is used, for example. MidWinLen said that among them, MidWinLen<=CirLen.

The third heavy loop (the innermost heavy loop): adopts the cyclic access method. If the third heavy loop body is regarded as a whole, the third heavy loop body can be cyclically moved inside the second heavy loop body, and the loop body The length is represented, for example, by InnWinLen, where InnWinLen<=MidWinLen.

The entire 3 loops can be represented by the following 7 data structures, which can also be stored in the CR. For example, the seven data structures are:

Start: The starting address of the outermost heavy loop body.

CirLen: The length of the outermost heavy loop body, where CirLen<=Size, Size represents the entire addressing area in the memory 101.

MidWinLen: The length of the intermediate heavy loop body, where MidWinLen<=CirLen.

InnWinLen: The length of the innermost heavy loop body, where InnWinLen<=MidWinLen.

Inc: The address growth step value inside the innermost loop body.

Stirde: The address growth step value when the innermost heavy loop body moves in the middle heavy loop body as a whole.

Step: The address growth step value when the intermediate heavy loop body moves in the outermost heavy loop body as a whole.

Each loop body works in the same way as a double loop, that is, it is configured first and then controlled. That is, the initialization of each data structure stored in the CR is completed by a dedicated instruction, and then the following three indexing modes are respectively implemented according to specific application scenarios: the innermost index is looped inside the innermost heavy loop body, and the innermost heavy loop body is heavy in the middle. The inner internal movement index and the intermediate heavy loop body move the index as a whole inside the outermost heavy loop.

Then, if extended to an N-repetition (N is an integer greater than 3), the entire N-recycle can be represented by 2N+1 data structures, which can also be stored in the CR. For example, these data structures are:

The starting address of the outermost heavy loop body;

The length of each of the N loop bodies, for example, the length of the outermost heavy loop body is L ₁ , ..., the length of the innermost heavy loop body is L _N , then L ₁ >= L ₂ ...>=L _N.

Similarly, the N _i +1 re-circulation can be cyclically moved as a whole in the N _i re-circulation, wherein the moving step values corresponding to each of the N loop bodies are represented as S ₁ -S _{N , respectively.} .

Similarly, for the entire loop area of the N-cycle, it is also configured first.

The following is an example of a double cycle, which is well known to those skilled in the art, according to the present invention. The idea of a clear cycle, as described above, is also within the scope of the invention.

If the area of the loop access includes a double loop, the following parameters may be involved:

In the embodiment of the present invention, the corresponding storage area is referred to as a first re-circulation area, and the first re-circulation area may adopt a cyclic access mode, and the length of the loop body is the first weight. The length of the loop area, for example as described above, can be expressed as WinLen, where WinLen<=CirLen. The first re-circulation area includes at least one sub-storage space, and each sub-storage space corresponds to one address.

In the embodiment of the present invention, the corresponding storage area is referred to as a second re-circulation area, and the second re-circulation area may adopt a cyclic access mode, and the length of the loop body (ie, the length of the second re-circulation area) is, for example, As introduced before, it can be expressed as CirLen. Where CirLen<=Size, Size represents the entire addressing area in the memory space of the memory 101.

As described above, the internal small loop can be moved in the outer major loop, and the moved address growth step value can be expressed as Stride. In the embodiment of the present invention, the step value is referred to as the second step value. The address offset of the inner heavy small loop in the outer major loop is S=S+Stirde, and S can be initialized to 0, for example. At the same time, the inner-weight small loop can also perform the loop index. In the inner-heavy loop, the address growth step value between the two sub-memory spaces can be represented as Inc. For example, in the embodiment of the present invention, the step value is called The first step value. The offset of the sub-memory space in the inner-heavy loop relative to the start address of the inner-heavy loop is I=I+Inc, and I can be initialized to 0, for example. That is, the address pointed to by I can be called the internal offset address of the inner heavy small loop, and the address pointed to by S can be called the internal offset address of the outer major loop.

It can be considered that if the cyclically accessed area includes two loops, the entire loop body can include five data structures, that is, information stored in five bit fields as described in Table 1, respectively:

Start: The external major loop start address, that is, the start address of the second re-circulation area. After it is initialized, it can also be called the initialization address of the cyclic storage area.

CirLen: The length of the outer major cycle, ie the length of the second recirculation zone.

WinLen: The length of the inner heavy loop, that is, the length of the first recirculation region.

Inc: The address growth step value inside the inner small loop, which is the first step value.

Stirde: The moving address growth step value of the inner heavy small loop window as a whole in the outer major loop, that is, the second step value.

In the embodiment of the present invention, the first re-circulation area corresponds to a pointer, which may be referred to as a first pointer (which may be denoted as I), and the increasing step value of the first pointer is Inc, that is, the address pointed to by the first pointer. After adding Inc based on the base, the first pointer points to the next address in the first recirculation area. The second re-circulation area corresponds to a pointer, which may be referred to as a second pointer (which may be denoted as S), and the growth step of the second pointer is Stirde, that is, after adding Stirde based on the address pointed by the second pointer, The second pointer points to the next address in the second recirculation region. Wherein, adding Stirde based on the address pointed by the second pointer can be considered as moving the first re-circulation as a whole in the second re-circle by a second step value.

FIG. 3 is a schematic diagram of a possible loop area in an embodiment of the present invention.

At any time, the access address of the loop body, that is, the operation instruction (in the embodiment of the present invention, the operation instruction may be an instruction to read data or an instruction to write data), may be expressed by a mathematical expression as:

Addr=Start+(S+I)%CirLen (1)

In the formula (1), % represents the modulo operation, S = (S + Stride)% CirLen, S can be initialized to 0, I = (I + Inc) % WinLen, I can be initialized to 0.

In the embodiment of the present invention, if an instruction to read data or an instruction to write data is executed to a position pointed to by a continuous physical address or a continuous logical address in a round robin manner, the instruction may not need to carry the destination address, and may be addressed by a cyclic manner. If the instruction to read data or the instruction to write data is executed in an acyclic manner, the instruction may carry the destination address and directly read and write according to the destination address. Therefore, the types of operation instructions in the embodiments of the present invention may be different, and are briefly described below.

The normal immediate index type, that is, the type of instruction that needs to explicitly indicate the location of the data storage in the operation instruction, that is, the destination address needs to be carried in the operation instruction. Instructions of this type of read data may be represented, for example, as Rd Dest Ri, and instructions of this type of write data may be represented, for example, as Wr Ri Src. Where Ri is used to indicate the address where the data to be read is located, Dest is the destination address to which the read data needs to be written, and Src is the data to be written.

The internal loop index type of the window is an operation instruction for the first re-circulation area. The operation instruction does not need to indicate the location of the data storage, that is, the destination address is not required to be carried in the operation instruction, and the system automatically addresses and operates in the operation. After the execution of the instruction is completed, the address pointed to by the first pointer corresponding to the first recirculation area automatically increases Inc at the next clock cycle. In the embodiment of the present invention, each time the address pointed by the pointer is updated, the system can calculate by using formula (1) to obtain the address corresponding to the next operation instruction. Instructions of this type of read data may be represented, for example, as RdI Dest, and instructions of this type of write data may be represented, for example, as WrI Src.

The loop index type of the overall movement of the window is an operation instruction for the second re-circulation area, and there is no need to specify the location of the data storage in the operation instruction, that is, the destination address is not required to be carried in the operation instruction, and the system automatically addresses, and After the execution of the class operation instruction is completed, the address pointed to by the second pointer corresponding to the second re-circulation area automatically increases Stirde, and the address pointed to by the first pointer corresponding to the first re-circulation area also automatically increases Inc. In the embodiment of the present invention, the address pointed by the pointer is updated when the next clock cycle arrives, and the system can perform calculation by the formula (1) to obtain the address corresponding to the next operation instruction. Instructions of this type of read data may be represented, for example, as RdS Dest, and instructions of this type of write data may be represented, for example, as WrS Src.

After receiving the operation instruction, the system can determine the type of the operation instruction according to the structure of the operation instruction, etc., thereby adopting different execution modes for different types of operation instructions.

The naming of the various data structures and the various types of operation instructions is only one possible representation provided by the embodiment of the present invention. In practical applications, it can be named differently according to different requirements.

The meanings of the above various types of instructions are explained below.

Wr Ri Src writes the data Src to the storage area pointed to by the address Ri. For example, Ri may be a register number, or may be other information for indicating an address;

Rd Dest Ri, reading data in the location pointed to by the address Ri in the memory 101 to the position pointed by the address Dest;

WrI Src, the data Src is written to the position pointed to by the self-indexing address in the first re-circulation area, where the self-indexing address is the instruction that last executed the loop type (the inner loop index type of the window or After the loop index type of the overall movement of the window), according to the address obtained by the formula (1) in the current clock cycle, the self-index pointer I=(I+Inc)%WinLen is simultaneously updated;

WrS Src, write Src to the position pointed to by the self-indexing address in the second recirculation area, where the self-indexing address is the address obtained according to formula (1) in the current clock cycle after the last execution of the loop type instruction. , at the same time update the self-index pointer S = (S + Stride)% CirLen, and update the self-index pointer I = (I + Inc)% WinLen;

RdI Dest, reads the data in the position pointed by the self-indexing address in the first re-circulation area to the position pointed by the address Dest, where the self-indexing address is the last clock cycle after the last execution of the loop type instruction According to the address obtained by the formula (1), the self-index pointer I=(I+Inc)%WinLen is updated at the same time; Dest is used to indicate a storage area;

RdS Dest, reads the data in the position pointed by the self-indexing address in the second recirculation area to the position pointed by the address Dest, where the self-indexing address is the last clock cycle after the last execution of the loop type instruction. According to the address obtained by the formula (1), the self-index pointer S=(S+Stride)%CirLen is updated at the same time, and the self-index pointer I=(I+Inc)%WinLen is updated.

Of course, the structure, function, and the like of the above various types of operation instructions are only an example given, as long as the operation instructions conforming to the idea of the present invention are within the protection scope of the present invention.

Additionally, the terms "system" and "network" are used interchangeably herein. The term "and/or" in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations. In addition, the character "/" in this article, unless otherwise specified, generally indicates that the contextual object is an "or" relationship.

The embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

Referring to FIG. 4, an embodiment of the present invention provides a method for generating an address, which may be completed by a control unit. (If the control unit is a CU, the method may be completed by the CU. If the control unit includes the WCU 1022 and the RCU 1021, then The operation instruction is an instruction to read data, and the method can be completed by the WCU 1022. If the operation instruction is an instruction to write data, the method can be completed by the RCU 1021. The flow of the method is described below.

Step 401: Receive a first operation instruction for a second recirculation area in the memory 101;

Step 402: The first operation instruction is executed, and the start address of the first re-circulation area in the memory 101 is modified by the second step value corresponding to the second re-circulation area to obtain an address corresponding to the next received operation instruction; The first recirculation region is cyclically moved in the second recirculation region according to the second step value.

First, the control unit can receive an operation instruction, which is referred to as a first operation instruction in the embodiment of the present invention. The first operational instruction may be an instruction to read data, or may be an instruction to write data.

In the embodiment of the present invention, the operation command may carry the destination address, or may not carry the destination address. In the embodiment of the present invention, the first operation instruction does not carry the destination address, that is, the first operation instruction is a cyclic type instruction for the second re-circulation area.

In addition, if the first operation instruction is an instruction to read data, the first operation instruction may further carry an address to which the data is directed, that is, indicate where the read data is to be stored, and if the first operation instruction is an instruction to write data, Then, the first operation instruction can also carry the address of the data source, that is, indicate where the data to be written comes from. Of course, the above are just some possible examples, and the present invention is not limited thereto.

As described above, the system in the embodiment of the present invention can execute a loop type instruction or a non-loop type instruction, so the operation instruction can be divided into different types, and different execution modes are used for different types of operation instructions. . Then, after receiving the operation instruction, the control unit may first determine the type information of the operation instruction, that is, determine what type of operation instruction is.

After determining the type of operational command, the control unit can determine the manner of execution corresponding to this type of operational command.

In the embodiment of the present invention, the first operation instruction may be a loop type instruction, and the type of the first operation instruction may be a loop index type of the overall movement of the window, that is, a type of the operation instruction for the second recirculation area, then the first operation instruction The execution mode is to execute the external large loop for the second recirculation region. For example, the first operational instruction may be RdS Dest or may be WrS Src.

After determining that the first operation instruction is an operation instruction for the second re-circulation area, the first operation instruction may be executed, for example, if the first operation instruction is an instruction to read data, the first address may be The pointed location writes data, or for example, if the first operational instruction is an instruction to write data, the data can be read from the location pointed to by the first address.

For example, the address corresponding to the first operation instruction is the first address. Wherein, if the first operation instruction is the first operation instruction received by the control unit after the system initializes each parameter involved in the cyclic class instruction, the first address is an initialization address of the cyclic storage area, that is, Start as described above. If the first operation instruction is not the first operation instruction received by the control unit after the system initializes the parameters involved in the cyclic class instruction, that is, before the first operation instruction, the control unit executes other instructions for reading data. Or the instruction to write data, the first address is the address obtained by the system in the current clock cycle after the last execution of the operation instruction, and the last executed operation instruction may be an operation instruction for the first recirculation area, or It may be an operation instruction for the second re-circulation area, and may be an instruction to read data or an instruction to write data.

Wherein, after each execution of the operation instruction, the internal offset address of the new first recirculation region (ie, the new I value) and the internal offset address of the new second recirculation region (ie, the new S) may be obtained. Value), when the next clock cycle comes, the corresponding register value can be updated according to the internal offset address of the new first recirculation region obtained last time and the internal offset address of the new second recirculation region, and according to The value of the updated register gets the address corresponding to this operation. That is to say, after each execution of the operation instruction is completed, the system only obtains the new I value and the new S value, but does not update the value of the corresponding register according to the new value, when the next clock cycle arrives (for example, the next time When receiving the operation instruction of the loop type, the system updates the corresponding register according to the new I value and the new S value obtained last time, and then obtains the address corresponding to the current operation by calculation.

After executing the first operation instruction, the internal offset address of the new second recirculation area can be obtained, and when the next clock cycle arrives (generally, when the operation instruction of the next cycle type is received), the second recirculation can be passed. The second step value corresponding to the region modifies the start address of the first re-circulation region, and obtains an address corresponding to the operation instruction for the first re-circulation region or the second re-circulation region. In this way, the next time the loop-type operation instruction is received, the control unit can automatically address it without having to carry the destination address in the operation instruction.

That is, in the embodiment of the present invention, when the first operation instruction is received, the first place can be directly calculated. Addressing, and performing data operations from the location pointed by the first address. In the embodiment of the present invention, performing data operations on a location pointed to by an address may refer to reading data from a location pointed to by the address, or may be pointing to the address. Write the data to the location pointed to. That is, the first operation instruction does not need to carry the destination address, and the system can operate according to the previously obtained address (ie, the first address). Similarly, after the current operation is completed, the next received area for the first recirculation area or The address corresponding to the operation instruction of the second recirculation area (here, the corresponding value is obtained, and the address needs to be calculated when the next clock cycle comes), so that the address obtained this time can be directly obtained when the operation instruction is received next time. Point to the location for data manipulation. In this way, the operation instruction does not need to carry the destination address, which reduces the code amount of the program to a large extent, does not need to consume too much storage space when storing the code, and also reduces the programming burden of the programmer.

Optionally, in another embodiment of the present invention, the first operation instruction is executed, and the start address of the first recirculation area in the memory 101 is modified by the second step value corresponding to the second recirculation area to obtain The address corresponding to the next received operation command, including:

Executing a first operation instruction, modifying a start address of the first recirculation region in the memory 101 by using a second step value corresponding to the second recirculation region, and modifying the first step value corresponding to the first recirculation region The internal offset address of a loop region is obtained to obtain the address corresponding to the next received operation command.

The first re-circulation area may include at least one sub-storage space, and each operation is directed to one of the sub-storage spaces, that is, the first pointer points to only one of the sub-storage spaces at a time, then the first re-circulation The internal offset address of the area may refer to the address of the sub-memory space to which the first pointer currently points.

Optionally, in another embodiment of the present invention,

Modifying the start address of the first recirculation region in the memory 101 by using the second step value corresponding to the second recirculation region, including:

Modifying the internal offset of the first recirculation region by the first step value corresponding to the first recirculation region Address, including:

The address pointed by the first pointer corresponding to the first re-circulation area is modified by the first step value corresponding to the first re-circulation area.

Optionally, in another embodiment of the present invention, obtaining an address corresponding to the next received operation instruction, including:

Adding a first pointer to a first step value to point to an address and performing a modulo operation on the length of the first recirculation region, and adding the second pointer to a second step value to point to the address and the second recirculation region The length of the modulo operation;

The result obtained by modulo the length of the second recirculation area is added to the initialization address of the cyclic storage area, and the address corresponding to the next received operation instruction is obtained.

In this embodiment, after the first operation instruction is executed, a new I value and a new S value can be obtained. When the next clock cycle arrives, the system can update the values of the register I and the register S according to the new I value and the new S value obtained after executing the first operation instruction, and can obtain the current value according to the updated register value. The address corresponding to the operation instruction, obviously, the address corresponding to the operation instruction is actually determined after the last execution of the operation instruction. For example, when the system obtains the address corresponding to this operation instruction, it can be calculated according to formula (1).

Optionally, in another embodiment of the present invention, the method further includes:

Receiving a second operation instruction for the first recirculation region;

The second operation instruction is executed, and the internal offset address of the first recirculation area is modified by the first step value corresponding to the first recirculation area to obtain an address corresponding to the next received operation instruction.

That is, in the embodiment of the present invention, the data processing device can execute various types of operation instructions.

In the embodiment of the present invention, the first operation instruction is an instruction for the second re-circulation area, and the second operation instruction is an instruction for the first re-circulation area, that is, the first operation instruction and the second operation instruction are both cyclic type instructions. It's just for different storage spaces.

The second operation instruction may be an instruction for reading data, such as RdI Dest, or a second operation The instruction may also be an instruction for writing data, such as WrI Src.

For example, the address corresponding to the second operation instruction is the second address. Wherein, if the second operation instruction is the first operation instruction received by the control unit after the system initializes each parameter involved in the cyclic class instruction, the second address is an initialization address of the cyclic storage area, that is, Start as described above. If the second operation instruction is not the first operation instruction received by the control unit after the system initializes the parameters involved in the cyclic class instruction, that is, before the second operation instruction, the control unit executes other instructions for reading data. Or the instruction to write data, the second address is the address obtained by the system in the current clock cycle after the last execution of the operation instruction, and the last executed operation instruction may be an operation instruction for the first recirculation area, or It may be an operation instruction for the second re-circulation area, and may be an instruction to read data or an instruction to write data.

In the embodiment of the present invention, when receiving the second operation instruction, the corresponding register may be directly updated according to the corresponding I value and S value obtained after the last execution of the operation instruction, and stored according to the value of the updated register and the cyclic storage. The parameter of the initialization address of the area is calculated to obtain the second address, and the data is operated from the location pointed by the second address. In the embodiment of the present invention, the data operation is performed on the location pointed to by the address, which may be read from the location pointed to by the address. Take data, or you can write data to the location pointed to by the address. That is, the second operation instruction does not need to carry the destination address, and the system can operate according to the previously obtained address (ie, the second address). Similarly, after the current operation is completed, the next received area for the first recirculation area or The address corresponding to the operation instruction of the second recirculation area (here, the corresponding value is obtained, and the address needs to be calculated when the next clock cycle comes), so that the address obtained this time can be directly obtained when the operation instruction is received next time. Point to the location for data manipulation. In this way, the operation instruction does not need to carry the destination address, which reduces the code amount of the program to a large extent, does not need to consume too much storage space when storing the code, and also reduces the programming burden of the programmer.

Optionally, in another embodiment of the present invention, the internal offset address of the first re-circulation area is modified by the first step value corresponding to the first re-circulation area, to obtain an address corresponding to the next received operation instruction, include:

Modifying the first corresponding to the first recirculation area by the first step value corresponding to the first recirculation area The address pointed to by the pointer to get the address corresponding to the next received operation instruction.

The first re-circulation area includes at least one sub-storage area. For example, when the second operation instruction is executed, the first pointer points to the address of the first sub-memory area in the first re-circulation area, and then is executed in the second operation instruction. After the completion, the control unit may add the first step value to the first pointer, and when the next clock cycle arrives, the first pointer points to the address of the second sub-storage area in the first re-circulation area, thus realizing Movement within the first recirculation zone.

Moreover, the address in the embodiment of the present invention is a result after modulo. An example is as follows.

If the first re-circulation area includes four sub-memory spaces, at the first moment, the read data instruction 1 for the first re-circulation area is received, and the read of the I value and the S-value obtained after the execution of the last operation instruction is completed. The address corresponding to the data instruction 1 is the address of the fourth sub-memory space in the first first re-circulation area, and the data is to be read from the fourth sub-memory space in the first first re-circulation area. After the data is read, the value of the first pointer is incremented by Inc, and the value of the second pointer is determined to be unchanged. When the next clock cycle arrives, the value of the register I is updated according to the value after the first pointer is incremented by Inc. The value of the register S may be unchanged, and the received second recirculation region or the second recirculation region may be obtained. The address corresponding to the operation instruction is the address of the first sub-memory space in the first first re-circulation area, and then the next time the operation instruction for the first re-circulation area or the second re-circulation area is received, The data that needs to be processed is the data in the first sub-storage space in the first first re-circulation region. It can be seen that if the first re-circulation area is regarded as a window, and each of the sub-storage spaces is regarded as a small window, the loop operation in the window of the first re-circulation area can be realized by performing a modulo operation on the address.

Similarly, the same is true for the second recirculation area, and it is also a process that can implement a cyclic operation.

It can be seen that if the loop operation is not required in a first recirculation region, when the first pointer points to the last sub-memory space in the first re-circulation region, the instruction sent is preferably for the second re-circulation region. The instruction, in this way, naturally executes the instruction in the second recirculation region, and moves to the next first recirculation region to implement sequential execution. Therefore, this also has certain requirements for the sender of the instruction (for example, a programmer). If the sequence execution is to be performed, the sender of the instruction needs to know the address pointed to by the first pointer after each execution. position.

Adding a first pointer to an address pointed to by the first step value and performing a modulo operation on the length of the first recirculation region, adding the obtained result to the address pointed by the second pointer, and adding the result to the first pointer The length of the second recirculation zone is subjected to a modulo operation;

In this embodiment, after the second operation instruction is executed, a new I value and a new S value can be obtained. When the next clock cycle arrives, the system can update the values of the register I and the register S according to the new I value and the new S value obtained after executing the second operation instruction, and can obtain the current value according to the updated register value. The address corresponding to the operation instruction, obviously, the address corresponding to the operation instruction is actually determined after the last execution of the operation instruction. For example, when the system obtains the address corresponding to this operation instruction, it can be calculated according to formula (1).

In the embodiment of the present invention, the process of receiving and executing the second operation instruction may occur before the process of receiving and executing the first operation instruction, or the process of receiving and executing the second operation instruction may also occur in the process. After the process of receiving and executing the first operational instruction.

For example, if the process of receiving and executing the second operation instruction occurs before the process of receiving and executing the first operation instruction, and the system executes the first operation instruction after the execution of the second operation instruction, then for the first In the case of an operation instruction, the second operation instruction is the last execution operation instruction, and the address corresponding to the next received operation instruction obtained after the execution of the second operation instruction may be the same address. Of course, if the process of receiving and executing the second operation instruction occurs before the process of receiving and executing the first operation instruction, and after the execution of the second operation instruction, the system executes other operation instructions, and then executes the first An operation instruction, the first address is not the same address as the address corresponding to the next received operation instruction obtained after executing the second operation instruction.

For example, if the process of receiving and executing the second operation instruction occurs after the process of receiving and executing the first operation instruction, and the system executes the second after the execution of the first operation instruction The operation instruction, then, for the second operation instruction, the first operation instruction is the last execution operation instruction, and the address corresponding to the next received operation instruction obtained after the execution of the first operation instruction may be the same as the second address address. Of course, if the process of receiving and executing the second operation instruction occurs after the process of receiving and executing the first operation instruction, and after the execution of the first operation instruction, the system executes other operation instructions, and then executes the first The second operation instruction is that the address corresponding to the next received operation instruction obtained after the execution of the first operation instruction is not the same address as the second address.

The following describes an example in which the process of receiving and executing the second operation instruction occurs before the process of receiving and executing the first operation instruction, and after the execution of the second operation instruction, the system executes the first operation instruction, that is, In the case of the first operational command, the second operational command is the most recently executed operational command.

For example, the second operation instruction is an instruction for reading data, for example, the second operation instruction is RdI Src for the first recirculation area, the first pointer is I, and the first step value is Inc. When receiving the second operation instruction, the corresponding address is an address of a location where the first sub-memory space in the first first re-circulation area is located, and the first re-circulation area includes, for example, four sub-storage spaces.

After receiving the second operation instruction, executing the second operation instruction, reading data from the position of the first sub-memory space in the first first re-circulation area, and after adding, increasing I to Inc, then under When a clock cycle arrives (for example, when receiving the first operation instruction), I points to the location of the second sub-memory space in the first first re-circulation area, and S does not change, according to I+Inc, S, and Start. The address corresponding to the next received operation instruction is obtained by the formula (1), for example, called address 1, and the address 1 is the address of the second sub-memory space in the first first re-circulation area.

For example, the first operation instruction is an instruction for reading data, for example, the first operation instruction is RdS Src for the second re-circulation area, the second pointer is S, and the second step value is Stride.

After receiving the first operation instruction, updating the value of the register I according to the new I value obtained after executing the second operation instruction, and obtaining the address corresponding to the first operation instruction, that is, the second sub of the first first recirculation region The address of the storage space. Executing the first operation instruction, reading data from the position of the second sub-memory space in the first first re-circulation area, and after adding, increasing S to Stride, and Adding Inc to I, when the next clock cycle comes, according to I+Inc, S+Stride, and Start, the address corresponding to the operation instruction can be obtained by formula (1), for example, called address 2.

Optionally, in another embodiment of the present invention, before receiving the first operation instruction, the method further includes:

The length of the first recirculation region, the length of the second recirculation region, the first step value, the second step value, and the start address of the cyclic storage region are initialized by executing a dedicated instruction. Wherein, after initializing the start address of the cyclic storage area, the obtained address is the initialization address of the cyclic storage area.

That is, parameters such as Start, CirLen, WinLen, Inc, and Stride can be initialized before the operation instruction is executed.

The dedicated instruction in this embodiment may be, for example, a dedicated configuration instruction, such as SetCR Src as described above, which is not limited by the present invention.

The following examples are presented.

Assume that the values of the parameters in the CR after initialization are:

Start=0;

CirLen=7;

WinLen=4;

Inc=1;

Stride=1.

Suppose you need to execute a series of instructions to read data. The IDs of the registers that need to be accessed during execution are:

{0,1,2,3}, {0,1,2,3},{1,2,3,4},{2,3,4,5},{3,4,5,6}, {4,5,6,0}, {5,6,0,1},......

Assuming that the range of the second recirculation region is {0, 1, 2, 3, 4, 5, 6, 7}, the ranges of the first four first recirculation regions are {0, 1, 2, 3}, respectively. 1,2,3,4},{2,3,4,5},{3,4,5,6}, the range of the next first recirculation region is {4,5,6,0}, Such a push, that is, the range of the first first recirculation region is {5, 6, 0, 1}, {6, 0, 1, 2}, and so on.

Then, refer to Table 1. A series of instructions for reading data can be executed in the manner shown in Table 1.

Table 1

It can be seen from Table 1 that when the value of I is 3 for the first time, if the next received operation instruction is still for the instruction of the first recirculation area, for example, the RdI Src instruction, the address pointed by I increases Inc, According to the formula (1), the address of the register 0 is obtained again, and the register 0 is accessed again next time, and the loop operation is realized.

When the value of I is 3 for the second time, the next received instruction is an instruction for the second recirculation area. For example, for RdS Src, the address pointed to by S increases Stride, from 0 to 1, and the address pointed to by I also increases Inc, from 3 to 0. According to formula (1), it jumps from the first first recirculation region. Go to the second second heavy loop area. The other contents of Table 1 are deduced by analogy and will not be repeated.

Optionally, in another embodiment of the present invention, the method may further include:

Receiving a third operation instruction;

The third operation instruction is executed, and the data operation is performed on the position pointed by the destination address carried by the third operation instruction.

In the embodiment of the present invention, the third operation instruction may be an acyclic type instruction (a normal immediate index type instruction), and the third operation instruction may be an instruction to read data, for example, may be a Rd Dest Src as described above, or The third operational instruction may be an instruction to write data, such as Wr Ri Src as previously described. The third operation instruction may carry the destination address, and the system may directly perform data operation on the location pointed by the destination address carried by the third operation instruction, which may be a read operation or a write operation.

In the embodiment of the present invention, the memory 101 includes a first re-circulation area and a second re-circulation area. When receiving an operation instruction (referred to as a first operation instruction) for the second re-circulation area, in addition to executing the first operation instruction, The start address of the first recirculation area may be modified by the second step value corresponding to the second recirculation area, and the address corresponding to the operation instruction received by the time may be automatically obtained when the next clock cycle arrives, that is, the next time When receiving an operation instruction for the first re-circulation area or the second re-circulation area, the operation can be directly performed according to the last obtained address, without carrying the destination address in the operation instruction, thereby reducing the code amount of the instruction, and does not need to consume a large amount. The storage space is used to store code while also reducing the programming burden on the programmer.

It will be clearly understood by those skilled in the art that for the convenience and brevity of the description, only the division of each functional unit described above is exemplified. In practical applications, the above function assignment can be completed by different functional units as needed. The internal structure of the device is divided into different functional units to perform all or part of the functions described above. The specifics of the systems, devices and units described above For the working process, refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit or unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application, in essence or the contribution to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

The above embodiments are only used to describe the technical solutions of the present application in detail, but the description of the above embodiments is only for helping to understand the method and the core idea of the present invention, and should not be construed as limiting the present invention. Those skilled in the art can be within the technical scope of the present disclosure. Changes or substitutions that are conceivable are intended to be included within the scope of the invention.

Claims

A method for generating an address, comprising:

Receiving a first operational instruction for a second recirculation region in the memory;

Executing the first operation instruction, and modifying a start address of the first recirculation area in the memory by using a second step value corresponding to the second recirculation area, to obtain an operation instruction corresponding to the next reception An address; wherein the first recirculation region cyclically moves in the second recirculation region according to the second step value.
The method of claim 1 wherein said first operational command is executed and said first recirculation region in said memory is modified by a second step value corresponding to said second recirculation region Start address to get the address corresponding to the next received operation command, including:

Executing the first operation instruction, modifying a start address of the first recirculation area in the memory by using a second step value corresponding to the second recirculation area, and corresponding to the first recirculation area The first step value modifies an internal offset address of the first recirculation region to obtain an address corresponding to an operation instruction received next time.
The method of claim 2 wherein

Modifying a starting address of the first re-circulation area in the memory by using a second step value corresponding to the second re-circulation area, including:

Modifying, by the second step value corresponding to the second recirculation region, an address pointed by the second pointer corresponding to the second recirculation region;

Modifying an internal offset address of the first re-circulation area by using a first step value corresponding to the first re-circulation area, including:

And modifying, by the first step value corresponding to the first recirculation region, an address pointed by the first pointer corresponding to the first recirculation region.
The method of claim 3, wherein obtaining an address corresponding to the next received operation instruction comprises:

Adding the first pointer to an address pointed by the first step value and the first re-circulation The length of the ring region is subjected to a modulo operation, and the modulo operation is performed by adding an address pointed by the second pointer to the second step value and a length of the second recirculation region;

Adding the obtained results of the two modulo, and performing a modulo operation on the added result and the length of the second recirculation region;

The result obtained by modulating the length of the second recirculation area is added to the initialization address of the cyclic storage area to obtain an address corresponding to the next received operation instruction.
The method of any of claims 1-4, wherein the method further comprises:

Receiving a second operation instruction for the first recirculation region;

Executing the second operation instruction, and modifying an internal offset address of the first re-circulation area by using a first step value corresponding to the first re-circulation area to obtain an address corresponding to an operation instruction received next time.
The method according to claim 5, wherein the internal offset address of the first recirculation region is modified by a first step value corresponding to the first recirculation region to obtain an operation instruction received next time The corresponding address, including:

The address pointed by the first pointer corresponding to the first re-circulation area is modified by the first step value corresponding to the first re-circulation area to obtain an address corresponding to the next received operation instruction.
The method according to claim 6, wherein the address corresponding to the next received operation instruction is obtained, including:

Adding the first pointer to an address pointed by the first step value and performing a modulo operation on the length of the first recirculation region, and adding the obtained result to the address pointed by the second pointer, And performing a modulo operation on the added result and the length of the second recirculation region;

The result obtained by modulating the length of the second recirculation area is added to the initialization address of the cyclic storage area to obtain an address corresponding to the next received operation instruction.
The method according to any one of claims 1-7, further comprising: before receiving the first operation instruction, further comprising:

The length of the first recirculation region, the length of the second recirculation region, the first step value corresponding to the first recirculation region, and the second recirculation region pair are performed by executing a dedicated instruction The second step value and the start address of the cyclic storage area are initialized.
A data processing device, comprising:

a memory including a first recirculation area and a second recirculation area;

a control unit, coupled to the memory, for receiving a first operation instruction for a second re-circulation area in the memory; executing the first operation instruction, and passing the second step corresponding to the second re-circulation area The value modifies a start address of the first re-circulation area in the memory to obtain an address corresponding to an operation instruction received next time; wherein the first re-circulation area is in the first step according to the second step value The cyclic movement in the double loop area.
The device of claim 9 wherein said control unit is operative to:

Executing the first operation instruction, modifying a start address of the first recirculation area in the memory by using a second step value corresponding to the second recirculation area, and corresponding to the first recirculation area The first step value modifies an internal offset address of the first recirculation region to obtain an address corresponding to an operation instruction received next time.
The device according to claim 10, wherein said control unit is configured to:

Modifying, by the second step value corresponding to the second recirculation region, an address pointed by the second pointer corresponding to the second recirculation region; and

And modifying, by the first step value corresponding to the first recirculation region, an address pointed by the first pointer corresponding to the first recirculation region.
The device according to claim 11, wherein said control unit is configured to:

Adding a first pointer to an address pointed by the first step value to perform a modulo operation with a length of the first recirculation region, and adding the second pointer to the second step value Performing a modulo operation on the address pointed to and the length of the second recirculation region;

Adding the obtained results of the two modulo, and performing a modulo operation on the added result and the length of the second recirculation region;

The result obtained by modulating the length of the second recirculation area is added to the initialization address of the cyclic storage area to obtain an address corresponding to the next received operation instruction.
Apparatus according to any of claims 9-12, wherein said control unit is further to:

Receiving a second operation instruction for the first recirculation region;

Executing the second operation instruction, and modifying an internal offset address of the first re-circulation area by using a first step value corresponding to the first re-circulation area to obtain an address corresponding to an operation instruction received next time.
The device of claim 13 wherein said control unit is operative to:

The address pointed by the first pointer corresponding to the first re-circulation area is modified by the first step value corresponding to the first re-circulation area to obtain an address corresponding to the next received operation instruction.
The device according to claim 14, wherein said control unit is adapted to:

Adding the first pointer to an address pointed by the first step value and performing a modulo operation on the length of the first recirculation region, and adding the obtained result to the address pointed by the second pointer, And performing a modulo operation on the added result and the length of the second recirculation region;

The result obtained by modulating the length of the second recirculation area is added to the initialization address of the cyclic storage area to obtain an address corresponding to the next received operation instruction.
The device according to any one of claims 9-15, wherein the device further comprises a control register for storing a length of the first recirculation region, a length of the second recirculation region, the a first step value corresponding to the first recirculation region, a second step value corresponding to the second recirculation region, and a start address of the cyclic storage region; the control unit is configured to:

The length of the first recirculation region, the length of the second recirculation region, the first step value, the second step value, and the stored in the control register by executing a dedicated instruction The start address of the cyclic storage area is initialized.