CN104657298A - Reading control device and method - Google Patents
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- CN104657298A CN104657298A CN201510073330.8A CN201510073330A CN104657298A CN 104657298 A CN104657298 A CN 104657298A CN 201510073330 A CN201510073330 A CN 201510073330A CN 104657298 A CN104657298 A CN 104657298A
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Abstract
The invention relates to a reading control device. The device is arranged between a system bus and a storage, and comprises a cache module and a control module, wherein the control module is used for executing acquiring operation according to the state of the system bus; the acquiring operation is specifically reading operation or prefetching operation; the acquiring operation comprises the following steps: checking whether or not content to be acquired is cached in the cache module; if the content to be acquired is cached in the cache module, loading the content to be acquired onto the system bus; when the content to be acquired is not cached in the cache module, acquiring the content to be acquired from the storage, saving the content in the cache module, and loading the content onto the system bus. The device and the method are used for realizing prefetching; for a system without branch prediction, the reading time is saved, and the performance of the system is enhanced.
Description
Technical field
The present invention relates to processor and memory area, particularly relate to one and read control device and method.
Background technology
At present, a lot of Embedded Application uses 8051 or 80251 these microprocessors of 8 as core processing unit, and in general, these processors can meet general demand from power consumption, performance and area.
In the embedded system that some are more advanced, in order to improve the performance of system further, have employed the method for looking ahead, particularly, be exactly increase a control module between storer and system bus, when system bus is idle, control module first obtains the content that system bus will be accessed from storer, when system bus access storer, the content of looking ahead directly is put on system bus by control module, such system bus need not wait for the content that acquisition will be accessed from storer again, thus save total reading time, improve the performance of system.But, this method is not suitable for the system not having branch prediction function, such as: some loop programs among a small circle, this is because do not predict the function that will jump to which address or call which address due to system, so when system bus is idle looking ahead of carrying out of control module for be were it not for situation when redirect occurring or calls, and in fact system there occurs redirect or calls, therefore the content with regard to causing system bus will read when reading be not before the control module content of looking ahead, thus system bus still needs to continue to wait for the content obtaining from storer and will read, extend the reading time, reduce the performance of system.
Summary of the invention
The invention provides one and read control device and method, in order to realize looking ahead, and for there is no the system of branch prediction, saving the reading time, improve the performance of system.
The invention provides one and read control device, described Plant arrangement is between system bus and storer, and described device comprises cache module and control module, wherein:
Described control module is used for the state according to described system bus, performs and obtains operation, and wherein, described acquisition operation is specially read operation or prefetch operation, and described acquisition operation comprises:
The content whether being cached with and will obtaining is searched in described cache module;
When being cached with the described content that will obtain in described cache module, the described content that will obtain is put on described system bus;
When the content not having in described cache module will obtain described in buffer memory, the content that will obtain described in obtaining from described storer to be saved in described cache module and to be put on described system bus.
The present invention also provides one to read control method, increases and read control device between system bus and storer, described in read control device and comprise cache module and control module, described method comprises:
Described control module, according to the state of described system bus, performs and obtains operation, and wherein, described acquisition operation is specially read operation or prefetch operation, and described acquisition operation comprises:
The content whether being cached with and will obtaining is searched in described cache module;
When being cached with the described content that will obtain in described cache module, the described content that will obtain is put on described system bus;
When the content not having in described cache module will obtain described in buffer memory, the content that will obtain described in obtaining from described storer to be saved in described cache module and to be put on described system bus.
The present invention also provides a kind of disposal system, comprise and aforesaidly read control device, processor, storer, described reading is communicated by system bus between control device with described processor, described in read to be communicated by internal bus between control device with described storer.
In the present invention, adopting and read the control module in control device and perform according to the state of system bus and obtain operation, realizing pre-fetch function by carrying out prefetch operation, access time that can be total in saving system, improve system performance; Cache module is set, whether be cached with the content that will obtain carry out different operations according to searching in cache module, and in system generation redirect or when calling the unknown, due to control module by the content caching of looking ahead or read in cache module, if so system generation redirect or call, when system bus reads, control module still may obtain the content that system bus will read in cache module, like this, make do not have the system of branch prediction function can save the time of reading equally, improve the performance of system.
Accompanying drawing explanation
Fig. 1 is the structural representation that the present invention reads control device embodiment;
Fig. 2 is the specific works procedure chart that the present invention reads control device embodiment;
Fig. 3 is the specific works procedure chart that the present invention reads an example of control device embodiment;
Fig. 4 is the example that the present invention reads large small end relation in control device;
Fig. 5 is the example schematic that the present invention reads to splice and combine in control device module 14 1 kinds of processing procedures;
Fig. 6 is the structural representation of disposal system embodiment of the present invention.
Embodiment
Below in conjunction with specification drawings and specific embodiments, the invention will be further described.
As shown in Figure 1, for the present invention reads the structural representation of control device embodiment, this Plant arrangement is between system bus and storer, specifically can comprise: cache module 11, control module 12, wherein, control module 12 is connected with cache module 11, and control module 12 is connected by internal bus 13 with between storer.
In the present embodiment, control module 12, for the state according to system bus, performs and obtains operation, wherein, acquisition operation is specifically as follows read operation or prefetch operation, and acquisition operation can comprise: in cache module 11, search the content whether being cached with and will obtaining; When being cached with the content that will obtain in cache module 11, the content that will obtain is put on system bus; The content that will obtain when not having buffer memory in cache module 11, obtains the content that will obtain and to be saved in cache module 11 and to be put on system bus from storer.
Particularly, when the state that control module 12 inquires system bus is reading state, control module 12 carries out read operation, searches the content whether being cached with and will reading in cache module 11; If be cached with the content that will read in cache module 11, then control module 12 content that directly acquisition will be read from cache module 11 is put on system bus; If do not have the content that buffer memory will read in cache module 11, then control module 12 obtains the content that will read and to be saved in cache module 11 and to be put on system bus from storer; When the state that control module 12 inquires system bus is idle condition, control module 12 carries out prefetch operation, searches the content whether being cached with and will looking ahead in cache module 11; The content will looked ahead when not having buffer memory in cache module 11, then control module 12 obtains the content that will look ahead and is saved in cache module 11 from storer, if be cached with the content that will look ahead in cache module 11, then control module 12 does not need to carry out follow-up prefetch operation, returns and continues inquiry system bus state.
The specific works process of this embodiment is as follows: control module 12 is according to the state of system bus, perform and obtain operation, wherein, acquisition operation is specifically as follows read operation or prefetch operation, and acquisition operation can comprise: in cache module 11, search the content whether being cached with and will obtaining; When being cached with the content that will obtain in cache module 11, the content that will obtain is put on system bus; The content that will obtain when not having buffer memory in cache module 11, obtains the content that will obtain and to be saved in cache module 11 and to be put on system bus from storer.
Particularly, as shown in Figure 2, be the specific works procedure chart that the present invention reads control device embodiment, can comprise the steps:
The state of step 21, control module 12 inquiry system bus, if system bus is reading state, carry out step 22, otherwise carry out step 25;
Step 22, control module 12 carry out read operation, search the content whether being cached with and will reading in cache module 11, if then perform step 23, otherwise perform step 24;
Step 23, control module 12 directly obtain the content that will read and are put on system bus from cache module 11;
Step 24, control module 12 obtain the content that will read and to be saved in cache module 11 and to be put on system bus from storer;
Step 25, control module 12 carry out prefetch operation, search the content whether being cached with and will looking ahead in cache module 11, if then return step 21, otherwise perform step 26;
Step 26, control module 12 obtain the content that will look ahead and are saved in cache module 11 from storer.
In the present embodiment, control module 12 specifically performs the acquisition operation being specially read operation or prefetch operation according to the state of system bus, realize pre-fetch function by carrying out prefetch operation, access time that can be total in saving system, improves system performance; Whether control module 12 is cached with the content that will obtain carries out follow-up different operation by searching in cache module 11, and in system generation redirect or when calling the unknown, due to control module 12 by the content caching of looking ahead or read in cache module 11, if so system generation redirect or call, when system bus reads, control module 13 still may obtain the content that system bus will read in cache module 11, like this, make do not have the system of branch prediction function also can save the time of reading, improve the performance of system.
Alternatively, in the present embodiment, the right of priority of read operation is higher than prefetch operation.Control module 12 is also in the process performing prefetch operation, the state of inquiry system bus, if system bus is idle condition, then continue the state of inquiry system bus, when the state of system bus is reading state, whether the read operation that judgement will perform clashes with the prefetch operation performed, when the read operation judging to perform clashes with the prefetch operation performed, interrupt the prefetch operation performed, the read operation that execution will perform, when no conflict occurred for the read operation judging to perform and the prefetch operation performed, continue to perform the prefetch operation performed, and continue to perform the read operation that will perform.
Particularly, control module 12 is also in the process performing prefetch operation, the state of inquiry system bus, if system bus is idle condition, then continue the state of inquiry system bus, when the state of system bus is reading state, in cache module 11, search the content whether being cached with and will reading; When there is the content that will read in cache module 11, control module 12 directly obtains the content that will read and is put on system bus from cache module 11, and prefetch operation is unaffected in the process, still can proceed, when not having the content that will read in cache module 11, control module 12 judges that whether the content that will read is consistent with the content of looking ahead; When the content that will read is consistent with the content of looking ahead, continue to perform current prefetch operation, bus is now in waiting status, when control module 12 completes prefetch operation, the content that control module 12 will read to be saved in cache module 11 and to be put on system bus, when the content that will read and the content of looking ahead are inconsistent, interrupt the prefetch operation performed, perform the read operation that will perform.That is, when the content read not in cache module 11 and inconsistent with current content of looking ahead time, control module 12 will abandon prefetch operation in time, ensures to return with the fastest speed to read new content, can reduce the performance loss of system.
As shown in Figure 3, the specific works procedure chart of an example of control device embodiment is read for the present invention, storer specifically can comprise Memory Controller and storage unit, in this example, storage unit is specially NVM, and Memory Controller is NVM controller, information transmission is carried out by NVM controller between control module 12 and NVM, wherein, NVM controller is used for according to concrete operations signal or timing requirements transmission of information between control module 12 and NVM, completes the read operation at storer; In addition, in this example, the content of prefetch operation or read operation is instruction, specifically can comprise the steps:
Step 301, control module 12 inquiry system bus, with or without read operation, if having, perform step 302, otherwise perform step 307;
Step 302, control module 12 search the address that whether there is the instruction that will read in cache module 11, if do not exist, perform step 303, otherwise perform step 306;
The address that step 303, control module 12 send the instruction that will read to NVM controller and reading signal, then wait for;
Whether step 304, control module 12 receive the reading settling signal that NVM controller returns, if then perform step 305, otherwise continue to perform step 304;
Step 305, control module 12 select signal to be put on system bus by the instruction of reading according to the figure place of system processor, simultaneously according to nearest least referenced (Least Recently Used, be called for short: LRU) instruction of reading is saved in cache module 11 by principle, then returns step 301;
Instruction corresponding for the address of the instruction will read in cache module 11 is put on system bus and reads by step 306, control module 12, then returns step 301;
Step 307, look ahead the preparatory stage, control module 12 searches the address that whether there is the instruction that will look ahead in cache module 11, if do not exist, performs step 308, otherwise performs step 301;
Step 308, control module 12 send address and the pre-fetch sig of the instruction that will look ahead to NVM controller;
Step 309, control module 12 judge whether to continue current prefetch operation, if then perform step 310, otherwise perform step 412;
Particularly, in this step, whether control module 12 continues detection system bus has read operation, if system bus has read operation and there is the address tag of the instruction that will read in cache module 11, then instruction corresponding for the address of the instruction that will read in cache module 11 is directly sent on system bus and reads by control module 12, and prefetch operation is unaffected in the process, still can proceed; If there is not the address tag of the instruction that will read in cache module 11, but the address tag of current instruction of looking ahead is consistent with the address tag of the instruction that system bus will read, then continue current prefetch operation, now system bus is in waiting status;
Whether step 310, control module 12 receive the settling signal of looking ahead that NVM controller returns, if then perform step 311, otherwise return step 309;
Step 311, control module 12 select signal to be put on system bus by the instruction of looking ahead according to the figure place of system processor, the instruction of looking ahead be saved in cache module 11 simultaneously, then return step 301 according to LRU principle;
Step 312, control module 12 send the signal abandoned of looking ahead to NVM controller, return step 303;
In this step, the address tag of the instruction of reading is neither in cache module 11, also inconsistent with the address of current instruction of looking ahead, then control module 12 sends the signal interruption prefetch operation abandoned of looking ahead to NVM controller, at this moment, return step 303, the address that control module 12 sends the new instruction that will read to NVM controller and reading signal, continue the read operation of system bus.
Alternatively, in this example, control module 12 will to read or the instruction of looking ahead can also for according to random algorithm (Random algorithm stored in the principle in cache module 11, be called for short: RAND) by the optional position of instruction buffer to cache module 11, or can also according to first in first out (FirstInput First Output, abbreviation: FIFO) principle is by the principle of instruction stored in cache module 11.
Alternatively, schematic diagram shown in Figure 1 again, read control device can also comprise and splice and combine module 14, splice and combine module 14 to be connected with cache module 11, splice and combine module 14 to go back and instruction and be connected with data bus 15, the instruction and data of transmission system bus read operation in instruction and data bus 15.Splice and combine module 14 for splicing and combining the content be put on system bus, the bit wide of the content be put on system bus is mated with the bit wide required by system bus.On the sheet of some processors in program storage block, generally can select EFLASH or band EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read-Only Memory, EEPROM) be called for short: nonvolatile memory (the Nonvolatile Memory such as, be called for short: NVM), and the access speed of these storeies is usually less 5 ~ 10 times than the clock frequency of system bus, but the bit wide of these storeies is but far away higher than the bit wide of system bus.Like this, by splicing and combining module 14, the content be put on system bus being spliced and combined, solving the unmatched problem of bit wide between system bus and storer.Further, in the present embodiment, the bit wide of system bus can be arbitrary, and the bit wide of storer also can be arbitrary, but can realize mating of bit wide between system bus with both storeies by splicing and combining module 14.
Alternatively, then schematic diagram shown in Figure 1, read control device and can also comprise address pretreatment module 16, address pretreatment module 16 be input as address bus 17, this address pretreatment module 16 and control module 12, splice and combine module 14 and be connected.Address pretreatment module 16 is for carrying out pre-service to the address of input, make the form of pretreated address consistent with the form of required address, particularly, address pretreatment module 16 carries out pre-service to the address on the address bus 17 of input, it is required address pattern in cache module 11 and storer by the address process on address bus 17, and result is reached control module 12, such as: the address in address bus 17 is the form of byte, address pattern in cache module 11 and storer is the form of word, then the byte address on address bus 17 carries out processing the form obtaining word address by address pretreatment module 16, and pass to control module 12.Pre-service carried out in address on address bus 17 and is used for cache module 11 and storer, can ensure in each operation, the address information that transmission form is consistent.Alternatively, address pretreatment module 16 can also by the address process on address bus 17 for splicing and combining the required byte address of module 14, and result reached and splice and combine module 14.Alternatively, splicing and combining module 14 can according to the large small end relation of the byte address of the pretreated each byte of address pretreatment module 16 and storer, the content read from cache module 11 or storer is selected, simultaneously according to the large little endian mode required for system bus, the content be put on system bus is spliced and combined, the bit wide of the content be put on system bus is mated with the bit wide required by system bus, and large little endian mode is consistent simultaneously.In addition, large small end is large end pattern and little endian mode, and large end pattern is exactly make the high byte of data in system bus leave low address in, and little endian mode is exactly make the high byte of data in system bus leave high address in.As shown in Figure 4, for the present invention reads an example of large little endian mode in control device, this example comprises address column 41, large end pattern 42 and little endian mode 43, suppose to deposit 4 byte b0b1b2b3, represent a high position for address column 41 with d0, represent the low level of address column 41 with d3, then for address d0, d1, d2, d3, byte order under corresponding large end pattern 42 is: b3, b2, b1, b0, and the byte order under corresponding little endian mode 43 is: b0, b1, b2, b3.
As shown in Figure 5, for the present invention reads the example schematic of a kind of processing procedure splicing and combining module 14 in control device, in this example, suppose that word address corresponding to data in cache module 11 or storer is 0x40, correspondingly, byte address corresponding to the data in cache module 11 or storer is followed successively by 0x100, 0x101, 0x102 and 0x103, under little endian mode, corresponding byte address 0x100 in cache module 11 or storer, 0x101, the data of 0x102 and 0x103 are followed successively by D0, D1, D2 and D3, if what system bus needed is large end pattern, then for splicing and composite module 14, as the part in the dotted line frame in Fig. 5, splicing and composite module 14 are according to address pretreatment module 16 pretreated byte address 0x100 and 0x101, select the data D0 in cache module 11 corresponding to byte address 0x100 and 0x101 or storer and D1, and splice and combine by large end pattern, obtain the required bit wide of system bus and large little endian mode, namely the data D0 in cache module 11 or storer under little endian mode and D1 and splicing with under large end pattern in composite module 14 to be put into data D1 on system bus and D0 corresponding, and the address that the data D1 be put on system bus and D0 is corresponding is 0x101 and 0x100.
Alternatively, in the present embodiment, cache module 11 can adopt complete association structure, can also adopt set associative structure or direct mirror-image structure.The content that cache module 11 adopts different structures all can realize cache read control module 12 will to obtain.
Alternatively, in the present embodiment, in cache module 11, the degree of depth of the content of buffer memory or bit wide can be arbitrary, can carry out different settings according to demand in practical application.Alternatively, in the present embodiment, the aforesaid content obtaining operation can be specifically data, also can be instruction.
Alternatively, in the present embodiment, when control module 12 carries out prefetch operation, a prefetch operation can be carried out, also sequentially can carry out repeatedly prefetch operation.
As shown in Figure 6, for the structural representation of disposal system embodiment of the present invention, this disposal system can comprise processor 61, reads control device 62, storer 63, system bus 64 and internal bus 13, read control device 62 between processor 61 and storer 63, particularly, read to be communicated by system bus 64 between control device 62 with processor 61, read to be communicated by internal bus 13 between control device 62 with storer 63.Wherein, system bus comprises the aforementioned instruction and data bus 15 read in control device embodiment, address bus 17; Read control device 62 can comprise and aforementionedly read arbitrary module in control device embodiment and step, do not repeat them here; Processor 61 is for completing reading to instruction, decoding, transmitting and some executable operations, and the operation such as the reading of complete paired data and process.Read the situation that control device 62 may be used for existing between any system bus 64 and storer 63 differences such as reading time, access speed or bit wide.
In the present embodiment, by reading the difference that control device 62 can exist between resolution system bus 64 and storer 63, such as: the unmatched problem of bit wide between system bus 64 and storer 63, owing to reading the pre-fetch function of control device 62, improve the performance of system, farthest decrease the stand-by period of bus, and read to there is cache module 11 in control device 62, like this in unknown system redirect or when calling, read control module 12 in control device 62 by the content caching of looking ahead or read in cache module 11, by searching the content of buffer memory in cache module 11, the content that system bus will read may be obtained, thus in the system not having branch prediction function, the time of reading can be saved equally, the performance of raising system.
Alternatively, in the present embodiment, processor 61 be specifically as follows microcontroller (Micro ControlUnit, be called for short: MCU), can also be direct memory access device (Direct Memory Access, abbreviation: DMA).
Alternatively, in the present embodiment, can also have other processing modules between the processor 61 of disposal system and storer 63, such as: Encryption Decryption module etc., reading control device 62 can any position between processor 61 and storer 63.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (10)
1. read a control device, it is characterized in that, described Plant arrangement is between system bus and storer, and described device comprises cache module and control module, wherein:
Described control module is used for the state according to described system bus, performs and obtains operation, and wherein, described acquisition operation is specially read operation or prefetch operation, and described acquisition operation comprises:
The content whether being cached with and will obtaining is searched in described cache module;
When being cached with the described content that will obtain in described cache module, the described content that will obtain is put on described system bus;
When the content not having in described cache module will obtain described in buffer memory, the content that will obtain described in obtaining from described storer to be saved in described cache module and to be put on described system bus.
2. device according to claim 1, it is characterized in that, described control module is also in the process performing described prefetch operation, inquire about the state of described system bus, when the state of described system bus is reading state, whether the read operation that judgement will perform clashes with the prefetch operation performed, when the read operation that will perform described in judging and the described prefetch operation performed clash, the prefetch operation performed described in interruption, the read operation that will perform described in performing.
3. device according to claim 1, it is characterized in that, described control module is also in the process performing described prefetch operation, inquire about the state of described system bus, when the state of described system bus is reading state, the content whether being cached with and will reading is searched in described cache module, when there is no the content that will read in described cache module, whether the content that will read described in judging is consistent with described content of looking ahead, when the described content that will read and described content of looking ahead inconsistent time, the prefetch operation performed described in interruption, the read operation that execution will perform.
4. device according to claim 1, is characterized in that, also comprises:
Address pretreatment module, for carrying out pre-service to the address of input, makes the form of pretreated address consistent with the form of required address.
5. device according to claim 1, is characterized in that, also comprises:
Splicing and combining module, for splicing and combining the content be put on described system bus, the bit wide of the content be put on described system bus being mated with the bit wide required by described system bus.
6. a disposal system, comprise and read control device, processor, storer described in claim 1-5, described reading is communicated by system bus between control device with described processor, described in read to be communicated by internal bus between control device with described storer.
7. read a control method, it is characterized in that, increase between system bus and storer and read control device, described in read control device and comprise cache module and control module, described method comprises:
Described control module, according to the state of described system bus, performs and obtains operation, and wherein, described acquisition operation is specially read operation or prefetch operation, and described acquisition operation comprises:
The content whether being cached with and will obtaining is searched in described cache module;
When being cached with the described content that will obtain in described cache module, the described content that will obtain is put on described system bus;
When the content not having in described cache module will obtain described in buffer memory, the content that will obtain described in obtaining from described storer to be saved in described cache module and to be put on described system bus.
8. method according to claim 7, it is characterized in that, described control module is also in the process performing described prefetch operation, inquire about the state of described system bus, when the state of described system bus is reading state, whether the read operation that judgement will perform clashes with the prefetch operation performed, when the read operation that will perform described in judging and the described prefetch operation performed clash, the prefetch operation performed described in interruption, the read operation that will perform described in performing.
9. method according to claim 7, it is characterized in that, described control module is also in the process performing described prefetch operation, inquire about the state of described system bus, when the state of described system bus is reading state, the content whether being cached with and will reading is searched in described cache module, when there is no the content that will read in described cache module, whether the content that will read described in judging is consistent with described content of looking ahead, when the described content that will read and described content of looking ahead inconsistent time, the prefetch operation performed described in interruption, the read operation that execution will perform.
10., according to the method that claim 7 is stated, it is characterized in that, described in read control device and also comprise and splice and combine module, described method also comprises:
The described module that splices and combines splices and combines the content be put on described system bus, and the bit wide of the content be put on described system bus is mated with the bit wide required by described system bus.
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| CN118244997A (en) * | 2024-05-28 | 2024-06-25 | 山东云海国创云计算装备产业创新中心有限公司 | Solid state disk data processing method and device, electronic equipment and storage medium |
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