CN101351082A - Method for manufacturing inner layer hole-to-line ultra-capability plate - Google Patents
Method for manufacturing inner layer hole-to-line ultra-capability plate Download PDFInfo
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- CN101351082A CN101351082A CNA200810142378XA CN200810142378A CN101351082A CN 101351082 A CN101351082 A CN 101351082A CN A200810142378X A CNA200810142378X A CN A200810142378XA CN 200810142378 A CN200810142378 A CN 200810142378A CN 101351082 A CN101351082 A CN 101351082A
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Abstract
The invention relates to a method for manufacturing an inner layer hole line-arrival ultra-ability board, which includes the following steps: step one: a core plate with the deformation amount of Z-CTE which is less than or equal to 50ppm/DEG C is provided; step two: an inner layer graph is designed and holes are drilled by a drilling cutter with the diameter which is less than or equal to Psi0.25mm and the line compensation quantity which is less than or equal to 0.5mil; step three: the inner layer graph is manufactured, and exposure is made by an automatic exposure machine, and holes are punched by a PE puncher, and the fiering deformation amount of the inner layer is controlled in the ranges of plus or minus 1.2mil, and the fiering coincidence degree is controlled in the ranges of plus or minus 1.5mil, and the core plate coincidence degree is controlled in the ranges of plus or minus 2.0mil and the punching repeatability is controlled in the ranges of plus or minus 1.0mil; step four: the core plate is pressed and the coincidence degree is monitored before the lamination and plate distribution and the interlayer contraposition is adjusted; step five: holes are drilled mechanically and are manufactured by a drilling cutter with the diameter being less than or equal to Psi 0.25mm and the spot test and monitoring are carried out to the inner layer. By carrying out special precision control for insufficient key control points of the printed circuit board in the prior art, the manufacturing method of the inner layer line-arrival ultra-ability board improves the graphic design method and increases the quality monitoring, which then effectively promotes the line-arrival ability of inner layer holes, reduces the rejection rate of related defects and ensures the rate of good product.
Description
Technical field
The present invention relates to printed circuit board and make the field, relate in particular to a kind of manufacture method of inner layer hole-to-line ultra-capability plate.
Background technology
Along with electronic product to become more meticulous, high-density development, the printed circuit board (pcb) market demand more and more tends to the figure precise treatment at present, inner layer hole-to-line/Clearance (at interval) ability that requires PCB to make is more and more higher, yet, prior art more and more has been difficult to satisfy the demand in market, and deviation appears in precision control etc. in graphical design method, the manufacturing process, and the related defects scrappage is higher, and and then have influence on production time of product, influence delivery.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of inner layer hole-to-line ultra-capability plate, by controlling to existing not enough CCP to do special precision in the prior art, can improve graphical design method, increase character surveillance, thereby effectively promote the inner layer hole-to-line ability.
For achieving the above object, the invention provides a kind of manufacture method of inner layer hole-to-line ultra-capability plate, comprise the steps:
Step 1: provide central layer, the deflection Z-CTE＜=50ppm/ of central layer ℃;
Step 2: layer pattern in the design, adopt the brill cutter of cutter footpath＜=￠ 0.25mm to hole line build-out amount＜=0.5mil;
Step 3: layer pattern in making, exposure adopts automatic exposure machine to make, punching adopts the PE perforating press to make, internal layer film deflection is controlled at ± the 1.2mil scope in, film registration is controlled at ± the 1.5mil scope in, the central layer registration is controlled at ± the 2.0mil scope in, the punching repeatable accuracy is controlled at ± the 1.0mil scope in;
Step 4: the pressing central layer, monitoring registration before the lamination row plate is adjusted interlayer alignment;
Step 5: machine drilling, adopt the brill cutter of cutter footpath＜=￠ 0.25mm to make, and take a sample test monitoring internal layer situation.
Beneficial effect of the present invention: by the CCP that has not enough printed circuit board in the prior art being done special precision control, improve graphical design method, increase character surveillance, thereby effectively promote the inner layer hole-to-line ability, reduce the scrappage of related defects, guarantee yields, deliver goods on schedule with support.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet appended graphic only provide with reference to and the explanation usefulness, be not to be used for the present invention is limited.
Description of drawings
Below in conjunction with accompanying drawing,, will make technical scheme of the present invention and other beneficial effects apparent by the specific embodiment of the present invention is described in detail.
In the accompanying drawing,
Fig. 1 is the flow chart of the manufacture method of inner layer hole-to-line ultra-capability plate of the present invention.
Embodiment
Describe the present invention below in conjunction with accompanying drawing.
As shown in Figure 1, the manufacture method of inner layer hole-to-line ultra-capability plate of the present invention comprises the steps:
Step 1: central layer is provided, selects the little sheet material of deflection for use, promptly deflection Z-CTE (thickness direction coefficient of linear thermal expansion)＜=50ppm/ ℃, strict control feeds intake batch, and guarantees effective running of T/CFA, to reduce the central layer deflection.
Step 2: layer pattern in the design, adopt the brill cutter in pocket knife footpath, cutter footpath＜=￠ 0.25mm suitably reduces the line build-out amount, compensation rate＜=0.5mil, the relative spacing of increase inner layer hole-to-line.
Step 3: layer pattern in making, internal layer film deflection is controlled at ± the 1.2mil scope in, film registration is controlled at ± the 1.5mil scope in, exposure adopts automatic exposure machine to make, the central layer registration is controlled at ± the 2.0mil scope in, punching adopts the PE perforating press to make, the punching repeatable accuracy is controlled at ± the 1.0mil scope in.
Step 4: the pressing central layer, the monitoring registration is adjusted interlayer alignment before the lamination row plate, adopts pin-lam mode pressing plate, and promptly pressing plate adopts " four slotted eyes location " mode to locate, the positioning accuracy height, and with the pressing of 3# press;
Step 5: machine drilling, adopt the brill cutter in pocket knife footpath to make, cutter footpath＜=￠ 0.25mm, and take a sample test monitoring internal layer situation, taking a sample test frequency is that 30P takes out 1P, promptly inspects 1 by random samples for 30.
According to above-mentioned flow process special precision control is done in the CCP of printed circuit board, can effectively be promoted the inner layer hole-to-line ability of printed circuit board, the spacing of the inner layer hole-to-line of the inner layer hole-to-line ultra-capability plate of made is 0.5～1.0mil.
The manufacture method of inner layer hole-to-line ultra-capability plate of the present invention is by doing special precision control to the CCP that has not enough printed circuit board in the prior art, improve graphical design method, increase character surveillance, thereby effectively promote the inner layer hole-to-line ability, reduce the scrappage of related defects, guarantee yields, deliver goods on schedule with support.
The above; for the person of ordinary skill of the art; can make other various corresponding changes and distortion according to technical scheme of the present invention and technical conceive, and all these changes and distortion all should belong to the protection range of accompanying Claim of the present invention.
Claims (4)
1, a kind of manufacture method of inner layer hole-to-line ultra-capability plate is characterized in that, comprises the steps:
Step 1: provide central layer, the deflection Z-CTE＜=50ppm/ of central layer ℃;
Step 2: layer pattern in the design, adopt the brill cutter of cutter footpath＜=￠ 0.25mm to hole line build-out amount＜=0.5mil;
Step 3: layer pattern in making, exposure adopts automatic exposure machine to make, punching adopts the PE perforating press to make, internal layer film deflection is controlled at ± the 1.2mil scope in, film registration is controlled at ± the 1.5mil scope in, the central layer registration is controlled at ± the 2.0mil scope in, the punching repeatable accuracy is controlled at ± the 1.0mil scope in;
Step 4: the pressing central layer, monitoring registration before the lamination row plate is adjusted interlayer alignment;
Step 5: machine drilling, adopt the brill cutter of cutter footpath＜=￠ 0.25mm to make, and take a sample test monitoring internal layer situation.
2, the manufacture method of inner layer hole-to-line ultra-capability plate as claimed in claim 1 is characterized in that, pin-lam mode pressing plate, the pressing of 3# press are adopted in the central layer pressing in the step 4.
3, the manufacture method of inner layer hole-to-line ultra-capability plate as claimed in claim 1 is characterized in that, taking a sample test frequency in the step 5 is that 30P takes out 1P.
4, the manufacture method of inner layer hole-to-line ultra-capability plate as claimed in claim 1 is characterized in that, the spacing of the inner layer hole-to-line of the inner layer hole-to-line ultra-capability plate of manufacturing is 0.5～1.0mil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810142378 CN101351082B (en) | 2008-08-15 | 2008-08-15 | Method for manufacturing inner layer hole-to-line ultra-capability plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810142378 CN101351082B (en) | 2008-08-15 | 2008-08-15 | Method for manufacturing inner layer hole-to-line ultra-capability plate |
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| Publication Number | Publication Date |
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| CN101351082A true CN101351082A (en) | 2009-01-21 |
| CN101351082B CN101351082B (en) | 2011-09-07 |
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| CN 200810142378 Active CN101351082B (en) | 2008-08-15 | 2008-08-15 | Method for manufacturing inner layer hole-to-line ultra-capability plate |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101697001B (en) * | 2009-01-22 | 2011-07-13 | 依利安达(广州)电子有限公司 | Method for detecting positional deviation among layers of multilayer printed circuit board |
| CN103079354A (en) * | 2012-11-08 | 2013-05-01 | 东莞生益电子有限公司 | Method for improving accuracy of resistance value of buried resistance printed circuit board |
| CN103200792A (en) * | 2013-03-14 | 2013-07-10 | 洛阳伟信电子科技有限公司 | Machining method of multilayer non-intersection blind buried hole circuit board |
| CN103533760A (en) * | 2013-10-23 | 2014-01-22 | 广东生益科技股份有限公司 | Fabrication method of non-via holes in inner layer of multilayer PCB |
-
2008
- 2008-08-15 CN CN 200810142378 patent/CN101351082B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101697001B (en) * | 2009-01-22 | 2011-07-13 | 依利安达(广州)电子有限公司 | Method for detecting positional deviation among layers of multilayer printed circuit board |
| CN103079354A (en) * | 2012-11-08 | 2013-05-01 | 东莞生益电子有限公司 | Method for improving accuracy of resistance value of buried resistance printed circuit board |
| CN103200792A (en) * | 2013-03-14 | 2013-07-10 | 洛阳伟信电子科技有限公司 | Machining method of multilayer non-intersection blind buried hole circuit board |
| CN103533760A (en) * | 2013-10-23 | 2014-01-22 | 广东生益科技股份有限公司 | Fabrication method of non-via holes in inner layer of multilayer PCB |
| CN103533760B (en) * | 2013-10-23 | 2016-08-17 | 广东生益科技股份有限公司 | Multi-layer PCB board internal layer is not turned on the preparation method in hole |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101351082B (en) | 2011-09-07 |
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Address after: 523127 Dongcheng District City, Guangdong province (with sand) science and Technology Industrial Park Road, No. 33 vibration with the number of Patentee after: Shengyi electronic Limited by Share Ltd Address before: 523000 Dongcheng District (Dongguan) science and Technology Industrial Park, Guangdong, China Patentee before: Dongguan Shengyi Electronics Ltd. |