CN101345026B - Frame data buffering apparatus and related frame data acquisition method - Google Patents
Frame data buffering apparatus and related frame data acquisition method Download PDFInfo
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- CN101345026B CN101345026B CN2007101283718A CN200710128371A CN101345026B CN 101345026 B CN101345026 B CN 101345026B CN 2007101283718 A CN2007101283718 A CN 2007101283718A CN 200710128371 A CN200710128371 A CN 200710128371A CN 101345026 B CN101345026 B CN 101345026B
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Abstract
The invention discloses a frame data damping device, comprising a retaining display which is used for displaying and keeping the frame data of a previous frame, and a data reading module which is used for reading the frame data of the previous frame, which is kept in the retaining display. The invention also discloses a data driving circuit which comprises a video data input terminal which is used for receiving video data, a driving voltage output terminal which is used for outputting a driving voltage to the display panel of the retaining display, a sampling and retaining unit which is used for sampling according to a sampling signal and keeping the voltage at the driving voltage output terminal so as to generate a sampling voltage, and a driving voltage generation unit which is used for carrying out signal processing to the video data according to a plurality of reference voltages, a polarity selection signal and the sampling voltage so as to output the driving voltage.
Description
Technical field
The present invention relates to a kind of frame data buffering apparatus with and related frame data acquisition method, be particularly related to a kind of pixel voltage of the display panel by retaking of a year or grade freeze mode display, with the display panel of freeze mode display directly as the device and method of one frame buffer.
Prior art
Compared to traditional crt display pulsed＜Impulse Type〉type of drive, freeze mode＜Hold Type〉display, for example: LCD＜Liquid Crystal Display, LCD 〉, in general the too slow problem of speed that all can respond makes shown dynamic image can produce the phenomenon of motion blur (Motion Blur).In order to accelerate liquid crystal speed and to make the image of demonstration have better picture quality, some image processing techniquess, for example: overdrive＜Over-Driving 〉, deinterleave＜De-interlacing, motion compensation＜Motion Compensation and frame transfer rate conversion＜Frame Rate Conversion etc., be used in widely on the product now.Yet aforesaid image processing method often needs to store the data of at least one picture, to carry out computing and to produce the video data of next display frame.Therefore, in the prior art, the freeze mode display all must use storer usually, as: dynamic RAM＜Dynamic Random Access Memory, DRAM〉or static RAM＜Static Random Access Memory, SRAM〉etc., as one frame buffer＜Frame Buffer 〉, to carry out the work of storage frame data.
Please refer to Fig. 1, Fig. 1 is the synoptic diagram of the video data processor 10 in the existing freeze mode display.Video data processor 10 is coupled to a source video sequence＜be not shown among the figure〉and a display system 130 between, it includes a storer 100, a memory control unit 110 and a data processing unit 120.Storer 100 is used as one frame buffer, with the picture data before the storage, memory control unit 110 is used for the access of control store 100, data processing unit 120 then can be used to according to 100 stored picture data of storer and the present video data that receives, overdrive, computing such as deinterleave, motion compensation or the conversion of frame transfer rate, with the video data of exporting next picture to display system 130.Therefore, the video data that display system 130 can be exported according to video data processor 10, outputting drive voltage is to show corresponding image.
Please continue with reference to figure 2, Fig. 2 is the synoptic diagram of the display system 130 in the existing freeze mode display.Display system 130 includes one display panel＜Display Panel〉131, one control circuit 132, a data drive circuit 133 and scan driving circuit 134.Control circuit 132 is used for according to one horizontal-drive signal＜Horizontal Synchronization〉135 and one vertical synchronizing signal＜Vertical Synchronization 136, produce corresponding control signal, input to data drive circuit 133 and scan drive circuit 134 respectively.The control signal that is produced according to control circuit 132, but each bar sweep trace on the scan drive circuit 134 sequential start display panels 131, the video data 137 that data drive circuit 133 is then produced according to above-mentioned video data processor 10 in addition, the driving voltage of output correspondence is to display panel 131, to control the brightness＜Brightness of corresponding pixel〉state, and then show corresponding image.
Therefore, in the prior art since the freeze mode display must use extra storer as frame buffer with storage associated video data, thereby cause production cost effectively to reduce.
Summary of the invention
Therefore, fundamental purpose of the present invention promptly is to provide a kind of data drive circuit and method that is used for the freeze mode display.
The present invention discloses a kind of data drive circuit that is used for a freeze mode display, includes a video data input end and is used for receiving a video data; One driving voltage output terminal is used for exporting a driving voltage to this freeze mode display; One sampling is coupled to this driving voltage output terminal with holding unit, is used for according to a sampled signal, and sampling and the voltage that keeps this driving voltage output terminal are to produce a sampling voltage; And one the driving voltage generation unit be coupled to this video data input end, this driving voltage output terminal and this sample-and-hold circuit unit, be used for according to a plurality of reference voltages, a polarity selection signal and this sampling voltage, this video data is carried out signal Processing, to export this driving voltage.
The present invention discloses a kind of driving method that is used for a freeze mode display in addition, includes to receive a video data; According to a sampled signal, sampling and the voltage that keeps a driving voltage output terminal are to produce a sampling voltage; According to a plurality of reference voltages, a polarity selection signal and this sampling voltage, this video data is carried out signal Processing, to export a driving voltage; And export this driving voltage to this freeze mode display.
The present invention discloses a kind of adquisitiones of frame data in addition, includes the frame data that utilize a freeze mode display to show a previous frame; And certainly among this freeze mode display, read the frame data of this previous frame that remains on this freeze mode display.
The present invention discloses a kind of frame data buffering apparatus in addition, and it includes a freeze mode display, is used for showing and the frame data that keep a previous frame; And one data read module be coupled to this freeze mode display, be used for reading the frame data of this previous frame that remains on this freeze mode display.
Description of drawings
Fig. 1 is the synoptic diagram of the video data processor in the existing freeze mode display.
Fig. 2 is the synoptic diagram of the display system in the existing freeze mode display.
Fig. 3 is used for the functional block diagram of a data drive circuit of freeze mode display for the present invention.
Fig. 4 is the synoptic diagram that is used for a flow process of data drive circuit of the present invention.
Fig. 5 is an embodiment synoptic diagram of data drive circuit of the present invention.
Fig. 6 is another embodiment synoptic diagram of data drive circuit of the present invention.
Fig. 7 is for using one embodiment of the invention synoptic diagram.
Fig. 8 be a gamma curve synoptic diagram.
The reference numeral explanation
10 video data processor
130 display systems
100 storeies
110 memory control units
120 data processing units
131 display panels
132 control circuits
133,30 data drive circuits
134 scan drive circuits
135 horizontal-drive signals
136 vertical synchronizing signals
137, D1 video data
310 video data input ends
320 driving voltage output terminals
330 sampling and holding units
340 driving voltage generation units
341,343 signal processing modules
342,344 computing units
The VOUT driving voltage
The SMP sampled signal
The V1 sampling voltage
V2 second voltage
The V3 tertiary voltage
V1 ' voltage
The D3 numerical data
The D4 signal processing results
REF1～REFn reference voltage
The POL polarity selection signal
40 flow processs
400,410,420,430,440,450 steps
DAC1, DAC2 D/A
AMP1, AMP2 voltage operational amplifier
The ADC2 A/D converter.
Embodiment
Please refer to Fig. 3, Fig. 3 is used for freeze mode＜Hold Type for the present invention〉functional block diagram of a data drive circuit 30 of display.Data drive circuit 30 includes a video data input end 310, a driving voltage output terminal 320, a sampling and a holding unit 330 and a driving voltage generation unit 340.Video data input end 310 is used for receiving a video data D1.Driving voltage output terminal 320 is used for exporting the display panel＜Display Panel of a driving voltage VOUT to the freeze mode display 〉.Sampling is coupled to driving voltage output terminal 320 with holding unit 330, is used for according to a sampled signal SMP sampling and maintenance＜Sample and Hold〉voltage of driving voltage output terminal 320, to produce a sampling voltage V1.Driving voltage generation unit 340 is coupled to video data input end 310, driving voltage output terminal 320 and sample-and-hold circuit unit 330, be used for according to reference voltage REF1～REFn, a polarity selection signal POL and sampling voltage V1, video data D1 is carried out signal Processing, to export corresponding driving voltage VOUT.
Please note at this, because the frame data of former frame are at next frame＜be present frame〉show before, still can be stored in the freeze mode display＜for example: with LCD, the data of former frame can be stored in the mode of voltage in the internal capacitance of display panel of LCD 〉, so the present invention utilizes sampling and holding unit 330 will be stored in the freeze mode display earlier before present frame shows frame data to read out.Therefore, the present invention utilizes the freeze mode display can keep the characteristic of last picture data, by sampling and the voltage that keeps driving voltage output terminal 320, just can learn the data of former frame, the display panel that such mechanism can be equivalent to the freeze mode display directly is used as one frame buffer＜FrameBuffer 〉, need the extra problem of using storer to store previous picture data to improve prior art.Thus, the demand of storer can reduce significantly, and then saves cost effectively.
About the mode of operation of data drive circuit 30, please continue with reference to figure 4, Fig. 4 is the synoptic diagram that is used for a flow process 40 of data drive circuit 30 of the present invention.Flow process 40 includes the following step:
Step 400: beginning.
Step 410: by video data input end 310, receiving video data D1.
Step 420: according to sampled signal SMP, by sampling and holding unit 330 samplings and the voltage that keeps driving voltage output terminal 320, to produce sampling voltage V1.
Step 430: according to reference voltage REF1～REFn, polarity selection signal POL and sampling voltage V1,340 couples of video data D1 carry out signal Processing by the driving voltage generation unit, to export corresponding driving voltage VOUT.
Step 440: by driving voltage output terminal 320, outputting drive voltage VOUT is to the display panel of freeze mode display.
Step 450: finish.
Therefore, according to flow process 40, the present invention at first passes through video data input end 310, receiving video data D1.Then, sampling can be according to sampled signal SMP with holding unit 330, sampling and the voltage that keeps driving voltage output terminal 320, to produce sampling voltage V1, make that driving voltage generation unit 340 can be according to sampling voltage V1, reference voltage REF1～REFn and polarity selection signal POL, to video data D1 overdrive, signal Processing such as deinterleave, motion compensation or the conversion of frame transfer rate, to export corresponding driving voltage VOUT to display panel.
It should be noted that for display panel directly as frame buffer, data drive circuit 30 must be before the new driving voltage VOUT of output, reads the pixel voltage of present display panel＜be the voltage of driving voltage output terminal 320 〉.For instance, the present invention can be when sampled signal SMP be in a high logic level, sampling＜Sample〉pixel voltage of display panel, driving voltage generation unit 340 stops outputting drive voltage VOUT at this moment, and sampling then changes along with the pixel voltage of display panel with the sampling voltage V1 that holding unit 330 is exported.On the contrary, when sampled signal SMP switches to a low logic level, sampling and 330 maintenances＜Hold of holding unit〉voltage that is sampled at present, and export and become sampling voltage V1.Therefore, driving voltage generation unit 340 can be according to sampling voltage V1, reference voltage REF1～REFn and polarity selection signal POL, and the signal Processing that present video data D1 is correlated with is to export corresponding driving voltage VOUT.And such mechanism knows usually that for this field tool the knowledgeable should not embarrass, for instance, it is two stage＜Phase that circuit designers can be ordered each driving time of gate drive signal 〉, first stage is used for making sampling keeping unit 330 information of former frame of taking a sample from display panel, second stage then is to be used for allowing driving voltage generation unit 340 to carry out signal Processing according to the information of former frame and present frame, drives screen to export corresponding driving voltage VOUT.And in real system, sampled signal SMP and polarity selection signal POL can not shown by a control circuit＜figure of freeze mode display 〉, as time schedule controller＜Timing Controller〉generation, reference voltage REF1～REFn then can be according to one gamma curve＜Gamma Curve as shown in Figure 8〉produce.
In addition, utilize driving voltage generation unit 340 to carry out the operation of signal Processing, have for this field and know that usually the knowledgeable is also not awkward.For instance, the present invention can compare the sampling voltage V1 of the video data of former frame and present video data D1, and utilize a computing unit of driving voltage generation unit 340＜be not shown in Fig. 3〉calculate the required overdrive voltage information of present frame, to export corresponding driving voltage VOUT.
Please refer to Fig. 5, Fig. 5 is an embodiment synoptic diagram of data drive circuit 30 of the present invention.As shown in Figure 5, driving voltage generation unit 340 includes a D/A DAC1 and a signal processing module 341.D/A DAC1 is coupled to video data input end 310, can be used to according to reference voltage REF1～REFn, video data D1 is converted to the second voltage V2 of an analog form.Signal processing module 341 is coupled to D/A switch cells D AC1, sampling and holding unit 330 and driving voltage output terminal 320, and it can include a computing unit 342 and a voltage operational amplifier AMP1.Computing unit 342 can be used to the sampling voltage V1 that produced according to polarity selection signal POL and sampling and holding unit 330, and the second voltage V2 is carried out signal Processing; Voltage operational amplifier AMP1 then is used for cushioning and amplifies the result of calculation that computing unit 342 is exported, to produce corresponding driving voltage VOUT.Usually know known to the knowledgeable as this area tool, the similar of embodiment of the invention driving voltage generation unit 340 is in prior art constructions, different places is signal processing module 341 except changing the polarity of the outputting drive voltage VOUT of institute according to polarity selection signal POL, the sampling voltage V1 that can be exported according to sampling and holding unit 330 in addition, to the second voltage V2 overdrive, signal Processing such as deinterleave, motion compensation or the conversion of frame transfer rate.Preferably, computing unit 342 can be used in addition according to polarity selection signal POL, with the polar switching of sampling voltage V1 to the corresponding polarity of the second voltage V2.
For instance, computing unit 342 can be earlier according to polarity selection signal POL, and sampling voltage V1 is converted to a voltage V1 ' with the second voltage V2 tool identical polar.Thus, voltage amplifier AMP1 can carry out coherent signal to the second voltage V2 and handle, to export corresponding driving voltage VOUT by voltage operational amplifier AMP1 according to voltage V1 '.For example: when overdriving, computing unit 342 can be according to following formula: VOUT=V2+K (V2-V1 '), by the corresponding driving voltage VOUT of voltage operational amplifier AMP1 output.Wherein, K can be that a default value or can be with the change value of voltage V1 ' and second voltage V2 variation.
On the other hand, for the deinterleave operation, because computing unit 342 can receive the information of former frame＜be voltage V1 or aforesaid voltage V1 '〉and the information of present frame＜be voltage V2, therefore, in the release of an interleave process, computing unit 342 also can design and be used for carrying out interpolation operation＜Interpolation〉or the like, so corresponding variation also belongs to category of the present invention.
In addition, please refer to Fig. 6, Fig. 6 is another embodiment synoptic diagram of data drive circuit 30 of the present invention.Data drive circuit 30 can comprise an A/D converter ADC2 in addition, be coupled between sampling and holding unit 330 and the driving voltage generation unit 340, be used for according to reference voltage REF1～REFn, the sampling voltage V1 that takes a sample and holding unit 330 is exported be converted to the numerical data D3 of a digital form.Preferably, A/D converter ADC1 in addition can be according to polarity selection signal POL, with the polar switching of numerical data D3 to the corresponding polarity of video data D1.Therefore, one signal processing module 343 of driving voltage generation unit 340 can be according to numerical data D3, to video data D1 overdrive, signal Processing such as deinterleave, motion compensation or the conversion of frame transfer rate, and, change the tertiary voltage V3 of signal processing results D4 to an analog form according to reference voltage REF1～REFn.Preferably, signal processing module 343 can be made up of a computing unit 344 and a D/A DAC2, as shown in Figure 6.At last, a voltage amplifier AMP2 of driving voltage generation unit 340 can be according to polarity selection signal POL, and buffering is amplified tertiary voltage V3, to export corresponding driving voltage VOUT.
For instance, when overdriving, computing unit 344 can produce corresponding signal processing results D4 according to following formula: D4=D1+K (D1-D3).Wherein, K can be that a default value or can be with the change value of video data D1 and numerical data D3 variation.Carry out signal Processing compared to Fig. 5 embodiment with analog form, present embodiment is with digital form video data D1 to be carried out signal Processing, because digital signal is more prone to be used for carry out signal Processing, therefore except having, also can obtain more accurate signal processing results than flexible implementation of tool and the various algorithm.
Please note at this, though in the foregoing embodiments, the frame data of former frame＜be the data that sample-and-hold circuit is exported〉offer the usefulness of data drive circuit 30 as the compensation of drive signal, yet, such practice only is embodiments of the invention, but not restriction of the present invention.In actual applications, the frame number of the previous frame that sample-and-hold circuit is exported can be applicable in the data processing circuit miscellaneous factually, and carrying out Flame Image Process, its embodiment can be as shown in Figure 7, and do not exceed with aforesaid data drive circuit 30.
In Fig. 7, the sampling voltage V1 that sampling and holding unit 330 are exported represents the frame data of former frame, and therefore, the digital signal D3 that is produced by sampling voltage V1 process digitizing also represents the information of former frame.In the present embodiment, digital signal D3 inputs to the graphics processing unit 350 of an outside, thus, graphics processing unit 350 just can be according to the information of former frame＜be digital signal D3〉and the present frame information that received＜be digital signal D1, carry out corresponding Flame Image Process.Therefore, the digital signal D4 that the data drive circuit of an existing structure just can directly be exported according to graphics processing unit 350 produces corresponding driving voltage VOUT, carrying out the driving of display panel, and then shows corresponding image.
In sum, the present invention is by the pixel voltage of the display panel of retaking of a year or grade freeze mode display, can be with the display panel of freeze mode display directly as one frame buffer, with improve prior art need extra use storer store before the problem of picture data.Thus, the use of the required storer of system can reduce significantly, and then saves cost effectively.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (19)
1. data drive circuit that is used for a freeze mode display includes:
One video data input end is used for receiving a video data;
One driving voltage output terminal is used for exporting a driving voltage to this freeze mode display;
One sampling and holding unit is coupled to this driving voltage output terminal, is used for according to a sampled signal, and sampling and the voltage that keeps this driving voltage output terminal are to produce a sampling voltage; And
One driving voltage generation unit, be coupled to this video data input end, this driving voltage output terminal and this sampling and holding unit, be used for this video data being carried out signal Processing, to export this driving voltage according to a plurality of reference voltages, a polarity selection signal and this sampling voltage.
2. data drive circuit as claimed in claim 1, wherein, this driving voltage generation unit includes:
One D/A switch unit is coupled to this video data input end, is used for this video data being converted to second voltage of an analog form according to these a plurality of reference voltages; And
One signal processing unit is coupled to this D/A switch unit, this sampling and holding unit and this driving voltage output terminal, is used for according to this polarity selection signal and this sampling voltage this second voltage being carried out signal Processing, to produce this driving voltage.
3. data drive circuit as claimed in claim 2, wherein, this signal processing unit is used in addition according to this polarity selection signal, with the polar switching of this sampling voltage to the corresponding polarity of this second voltage.
4. data drive circuit as claimed in claim 2, wherein, this signal processing unit comprises a voltage operational amplifier.
5. data drive circuit as claimed in claim 1, it includes an A/D converter in addition, is coupled between this sampling and holding unit and this driving voltage generation unit, is used for this sampling voltage is converted to first numerical data of a digital form.
6. data drive circuit as claimed in claim 1, wherein, this driving voltage that this driving voltage generation unit is exported in order to drive this freeze mode display, is to realize overdriving with this freeze mode display picture element voltage of retaking of a year or grade.
7. data drive circuit as claimed in claim 1, wherein, this driving voltage that this driving voltage generation unit is exported in order to drive this freeze mode display, is to realize deinterleave with this freeze mode display picture element voltage of retaking of a year or grade.
8. data drive circuit as claimed in claim 1, wherein, this driving voltage that this driving voltage generation unit is exported in order to drive this freeze mode display, is to realize motion compensation with this freeze mode display picture element voltage of retaking of a year or grade.
9. data drive circuit as claimed in claim 1, wherein, this driving voltage that this driving voltage generation unit is exported in order to drive this freeze mode display, is to come the conversion of achieve frame transfer rate with this freeze mode display picture element voltage of retaking of a year or grade.
10. data drive circuit as claimed in claim 1, wherein, these a plurality of reference voltages produce according to a gamma curve.
11. a driving method that is used for a freeze mode display includes:
Receive a video data;
According to a sampled signal, sampling and the voltage that keeps a driving voltage output terminal are to produce a sampling voltage;
According to a plurality of reference voltages, a polarity selection signal and this sampling voltage, this video data is carried out signal Processing, to export a driving voltage; And
Export this driving voltage to this freeze mode display.
12. driving method as claimed in claim 11 wherein, according to these a plurality of reference voltages, this polarity selection signal and this sampling voltage, carries out signal Processing to this video data, comprises to export this driving voltage:
According to these a plurality of reference voltages, this video data is converted to second voltage of an analog form; And
According to this polarity selection signal and this sampling voltage, this second voltage is carried out signal Processing, to produce this driving voltage.
13. driving method as claimed in claim 12, wherein, according to this polarity selection signal and this sampling voltage, this second voltage is carried out signal Processing, comprise in addition according to this polarity selection signal to produce this driving voltage, with the polar switching of this sampling voltage to the corresponding polarity of this second voltage.
14. driving method as claimed in claim 11, wherein, according to this sampled signal, sampling and the voltage that keeps this driving voltage output terminal, comprise in addition according to these a plurality of reference voltages to produce this sampling voltage, this sampling voltage is converted to first numerical data of a digital form.
15. driving method as claimed in claim 11 wherein, is exported this driving voltage to this freeze mode display, in order to drive this freeze mode display, is to realize overdriving with this freeze mode display picture element voltage of retaking of a year or grade.
16. driving method as claimed in claim 11 wherein, is exported this driving voltage to this freeze mode display, is to realize deinterleave with this freeze mode display picture element voltage of retaking of a year or grade.
17. driving method as claimed in claim 11 wherein, is exported this driving voltage to this freeze mode display, is to realize motion compensation with this freeze mode display picture element voltage of retaking of a year or grade.
18. driving method as claimed in claim 11 wherein, is exported this driving voltage to this freeze mode display, is to come the conversion of achieve frame transfer rate with this freeze mode display picture element voltage of retaking of a year or grade.
19. driving method as claimed in claim 11, wherein, these a plurality of reference voltages are to produce according to a gamma curve.
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| CN2007101283718A CN101345026B (en) | 2007-07-10 | 2007-07-10 | Frame data buffering apparatus and related frame data acquisition method |
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| CN103581504B (en) * | 2012-07-20 | 2017-06-20 | 晨星软件研发(深圳)有限公司 | Motion compensation image processor and image treatment method |
| CN104916264B (en) * | 2015-07-02 | 2017-11-14 | 新港海岸(北京)科技有限公司 | A kind of liquid crystal display overdrive circuit |
| CN106097991B (en) * | 2016-05-30 | 2018-08-07 | 深圳市华星光电技术有限公司 | The data drive circuit and driving method of liquid crystal display panel |
| JP2018041001A (en) * | 2016-09-09 | 2018-03-15 | セイコーエプソン株式会社 | Display driver, electro-optical device, electronic apparatus, and control method for display driver |
| CN107045862B (en) * | 2017-06-20 | 2019-12-13 | 惠科股份有限公司 | Driving circuit and method of display panel and display device |
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| US6154192A (en) * | 1997-05-07 | 2000-11-28 | Sony Corporation | Liquid crystal display device and data line drive circuit of liquid crystal display device |
| CN1729504A (en) * | 2002-12-20 | 2006-02-01 | 皇家飞利浦电子股份有限公司 | Video driver with integrated sample-and-hold amplifier and column buffer |
| JP2006259763A (en) * | 2006-05-01 | 2006-09-28 | Sony Corp | Display device |
| CN1892788A (en) * | 2005-06-30 | 2007-01-10 | Lg.菲利浦Lcd株式会社 | Analog sampling apparatus for liquid crystal display |
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| US6154192A (en) * | 1997-05-07 | 2000-11-28 | Sony Corporation | Liquid crystal display device and data line drive circuit of liquid crystal display device |
| CN1729504A (en) * | 2002-12-20 | 2006-02-01 | 皇家飞利浦电子股份有限公司 | Video driver with integrated sample-and-hold amplifier and column buffer |
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| JP2006259763A (en) * | 2006-05-01 | 2006-09-28 | Sony Corp | Display device |
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