CN101335307B - Semiconductor voltage-stabilizing device and manufacturing method therefor - Google Patents
Semiconductor voltage-stabilizing device and manufacturing method therefor Download PDFInfo
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- CN101335307B CN101335307B CN2007100432607A CN200710043260A CN101335307B CN 101335307 B CN101335307 B CN 101335307B CN 2007100432607 A CN2007100432607 A CN 2007100432607A CN 200710043260 A CN200710043260 A CN 200710043260A CN 101335307 B CN101335307 B CN 101335307B
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- semiconductor
- voltage
- stabilizing device
- conductivity
- polysilicon
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Abstract
The invention discloses a voltage stabilizer of a low-voltage semiconductor and a manufacturing method thereof, which simplifies the traditional structure and improves the consistency of reverse electric leakage characteristic and breakdown voltage. The technical proposal is that the voltage stabilizer comprises: an underlay substrate composed of a first conductive semiconductor and a first semiconductor area thereof with first conductivity, a second semiconductor area with second conductivity and established on the surface of the first semiconductor area, a polysilicon layer with second conductivity and high impurity concentration and established on the surface of the first semiconductor area and an MIS structure established on the surface of the first semiconductor area and covered by the polysilicon layer, wherein, reverse bias is imposed on the underlay composed of the first conductive semiconductor and a PN junction formed on the second semiconductor area with second conductivity, together with the surface depletion and the dispersing of the electric field of the first semiconductor area generated by the MIS structure which senses under the reverse bias, so as to jointly generate the ideal voltage-stabilizing characteristic of the voltage stabilizer. The voltage stabilizer of the invention is applied in the manufacturing field of semiconductor devices.
Description
Technical field
The present invention relates to a kind of structure and manufacture method of semiconductor voltage-stabilizing device, relate in particular to a kind of structure and manufacture method of making low volt Zener voltage-stabiliser tube.
Background technology
Extensively utilization semiconductor zener voltage regulator spare is in low volt voltage clamp in the electronic product, and this low volt voltage-stabilizing device is by a back-biased P
+N
+Knot forms.This voltage-stabilizing device is the electric current formed Zener breakdown of passing through potential barrier what be lower than that the 7V scope relied on.Tradition for overcoming the junction leakage on surface, has the dark PN junction that diffuses to form by ring in the construction of the edge of planar junction in this low volt voltage-stabilizing device.Because be formed on the substrate of low-resistance by ring, its surperficial counter doping concentration must be very high, the degree of depth of knot is very big.Consequently PN junction ends the electric leakage of ring itself owing to the dislocation that height impurity compensation brings becomes very big.It is complicated that therefore technology also becomes.
Summary of the invention
The object of the present invention is to provide a kind of low voltage semiconductor voltage-stabilizing device, suppress reverse leakage current.
Another object of the present invention is to provide a kind of manufacture method of low voltage semiconductor voltage-stabilizing device, improve the consistency of reverse breakdown voltage.
Technical scheme of the present invention is: the invention discloses a kind of semiconductor voltage-stabilizing device, described voltage-stabilizing device comprises:
One substrate base that constitutes by first conductive semiconductor, i.e. first semiconductor region;
One is established in second semiconductor region with second conductivity on the described first semiconductor region surface;
One be established in the described first semiconductor region surface have second conductivity and the solid high polysilicon layer of concentration of impurity;
One is established in the polysilicon-insulating barrier-semiconductor structure around described second semiconductor region;
Wherein, described have on the PN junction that first semiconductor region that first conductive semiconductor constitutes and second semiconductor region with second conductivity form be applied with reverse bias, described polysilicon-insulating barrier-semiconductor structure is responded to first semiconductor region that produces under described reverse bias surface depletion and electric field disperse, to produce the desirable stabilized voltage characteristic of described voltage-stabilizing device.
Above-mentioned semiconductor voltage-stabilizing device, wherein, described first semiconductor region with first conductivity is heavily doped
Above-mentioned semiconductor voltage-stabilizing device, wherein, described second semiconductor region with second conductivity is heavily doped.
Above-mentioned semiconductor voltage-stabilizing device, wherein, the heavy doping with second conductivity of described second semiconductor region is introduced by doped polycrystalline silicon layer.
Above-mentioned semiconductor voltage-stabilizing device, wherein, described polysilicon-insulating barrier-semiconductor structure is present in the periphery of described second semiconductor region, is by the polysilicon that mixes, silicon dioxide layer, first semiconductor region is constituted.
Above-mentioned semiconductor voltage-stabilizing device, wherein, described substrate base is made of the semiconductor of low resistance, and its resistivity is higher than 0.001 ohmcm.
Above-mentioned semiconductor voltage-stabilizing device, wherein, described first conductivity is the N type, described second conductivity is the P type.
Above-mentioned semiconductor voltage-stabilizing device, wherein, described first conductivity is the P type, described second conductivity is the N type.
The present invention has proposed a kind of manufacture method of semiconductor voltage-stabilizing device in addition, comprising:
Growth first silicon dioxide layer on the substrate base that constitutes by first conductive semiconductor;
Form first window at described first silicon dioxide layer by silicon dioxide layer photoetching and corrosion, growth second silicon dioxide layer in first window;
In described first window, form second window littler than described first window by silicon dioxide layer photoetching and corrosion;
Deposition one deck polysilicon and described polysilicon mixed with second conductive impurities on described first window;
Described polysilicon becomes required figure via dry method or wet etching, and further do to advance diffusion to form heavily doped second semiconductor region by described second window with second conductivity to described second conductive impurities, between first window and second window, the annular region that is established in around second semiconductor region constitutes polysilicon-insulating barrier-semiconductor structure, by the described polysilicon that covers, second silicon dioxide layer and first semiconductor region form.The manufacture method of above-mentioned semiconductor voltage-stabilizing device, wherein, described substrate base is made of the semiconductor of low resistance, and its resistivity is higher than 0.001 ohmcm.
The manufacture method of above-mentioned semiconductor voltage-stabilizing device, wherein, described second semiconductor region forms in second window.
The manufacture method of above-mentioned semiconductor voltage-stabilizing device, wherein, the thickness of described second silicon dioxide layer is between 20 dust to 1000 dusts.
The manufacture method of above-mentioned semiconductor voltage-stabilizing device, wherein, with the thickness of the polysilicon layer of low pressure chemical sedimentation deposition at 1000 dust to 3000 dusts.
The manufacture method of above-mentioned semiconductor voltage-stabilizing device, wherein, the mode of described polysilicon layer being mixed described second conductive-type impurity comprises that ion injects or the impurity source diffusion.
The manufacture method of above-mentioned semiconductor voltage-stabilizing device, wherein, the temperature in described second conductive impurities propelling diffusion is between 900 degrees centigrade to 1200 degrees centigrade.
The manufacture method of above-mentioned semiconductor voltage-stabilizing device, wherein, described first conductivity is the N type, described second conductivity is the P type.
The manufacture method of above-mentioned semiconductor voltage-stabilizing device, wherein, described first conductivity is the P type, described second conductivity is the N type.
The present invention contrasts prior art following beneficial effect: the edge of voltage-stabilizing device midplane PN junction of the present invention is to exhaust and end by metal (the polysilicon)-semiconductor surface charges of insulating barrier-semiconductor (MIS) structure.The benefit of doing like this is two aspects: 1) save traditional guard ring structure in the manufacturing process; 2) thus the MIS structure has disperseed the fringe field of plane PN junction more effectively to suppress edge current leakage.
Description of drawings
Fig. 1 is the sectional view of an embodiment of semiconductor voltage-stabilizing device of the present invention.
Fig. 2 to Fig. 3 is the schematic diagram of the manufacture process of semiconductor voltage-stabilizing device of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.
Fig. 1 shows the cross section of a preferred embodiment of thyrector of the present invention, and present embodiment is with P
+N
+Two-layer structure illustrates technical scheme of the present invention.In the semiconductor voltage-stabilizing device, N type semiconductor constitutes substrate of bottom portion substrate 1, and substrate base is made of the semiconductor of low resistance, and its resistivity is higher than 0.001 ohmcm, covers layer of silicon dioxide 3 on substrate base 1.Substrate base 1 can be heavily doped.P+ diffusion region 7 is diffuseed to form by 8 pairs of silicon faces of the heavily doped polysilicon layer of P type.Because the solid concentration ratio of p type impurity in polysilicon 8 is bigger, and therefore can form the voltage-stabiliser tube that the P+ layer 7 with higher concentration gradient is made the Zener low breakdown voltage at the interface of polysilicon 8/ silicon substrate substrate 1.Metal level (polysilicon)-insulating barrier-semiconductor structure (MIS structure) is present in the periphery of P+ layer 7, is to be made of the polysilicon 8, silicon dioxide layer 3 and the substrate base 1 that mix.Form PN junction between substrate base 1 and the P+ layer 7, apply reverse bias on PN junction, the MIS structure is responded to the substrate base 1 that produces under reverse bias surface depletion and electric field disperse, to produce the desirable stabilized voltage characteristic of voltage-stabilizing device.
Fig. 2～4 show the manufacture method of above-mentioned semiconductor voltage-stabilizing device.See also Fig. 2, be lower than 0.001 ohm in resistivity. centimetre N type semiconductor substrate base 1 on the growth layer of silicon dioxide 3, its thickness is at 5000 dust to 12000 dusts.Remove silicon dioxide 3 with common photoetching and caustic solution and form window 2.Growth layer of silicon dioxide 5 in window 2, its thickness is at 20 dust to 1000 dusts.
Referring to Fig. 3, in window 2, remove silicon dioxide 5 and form the window 4 littler than window 2 with common photoetching and caustic solution.
Referring to Fig. 1, deposition one deck polysilicon 8 and on window 2 to polysilicon 8 heavily doped p type impurities, wherein with the thickness of the polysilicon layer of low pressure chemical sedimentation deposition at 1000 dust to 3000 dusts, the mode of mixing p type impurity comprises that ion injects or the impurity source diffusion.Remove unnecessary polysilicon with common photoetching method and method for etching plasma, polysilicon is corroded into required figure via dry method or wet method.The polysilicon that stays more extends on the silicon dioxide 3 except that covering window 2.P type impurity in the polysilicon 8 does to advance diffusion to form heavily doped P+ district 7 by window 4.The temperature of p type impurity in advancing diffusion is between 900 degrees centigrade to 1200 degrees centigrade.
In above-mentioned manufacture method, the annular region between window 2 and window 4 constitutes polysilicon-insulating barrier-semiconductor (MIS) structure, is formed by the polysilicon 8, silicon dioxide 5 and the substrate base 1 that cover.
Should be understood that the present invention is with P
+N
+The embodiment of two-layer structure illustrates that those skilled in the art the present invention as can be known also can be applied to N equally
+P
+Two-layer structure.
The foregoing description provides to those of ordinary skills and realizes or use of the present invention; those of ordinary skills can be under the situation that does not break away from invention thought of the present invention; the foregoing description is made various modifications or variation; thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (17)
1. semiconductor voltage-stabilizing device, described voltage-stabilizing device comprises:
One substrate base that constitutes by first conductive semiconductor, i.e. first semiconductor region;
One is established in second semiconductor region with second conductivity on the described first semiconductor region surface;
One be established in the described first semiconductor region surface have second conductivity and the solid high polysilicon layer of concentration of impurity;
One is established in the polysilicon-insulating barrier-semiconductor structure around described second semiconductor region;
Wherein, described have on the PN junction that first semiconductor region that first conductive semiconductor constitutes and second semiconductor region with second conductivity form be applied with reverse bias, described polysilicon-insulating barrier-semiconductor structure is responded to first semiconductor region that produces under described reverse bias surface depletion and electric field disperse, to produce the desirable stabilized voltage characteristic of described voltage-stabilizing device.
2. semiconductor voltage-stabilizing device according to claim 1 is characterized in that, described first semiconductor region with first conductivity is heavily doped.
3. semiconductor voltage-stabilizing device according to claim 1 is characterized in that, described second semiconductor region with second conductivity is heavily doped.
4. semiconductor voltage-stabilizing device according to claim 3 is characterized in that, the heavy doping with second conductivity of described second semiconductor region is introduced by doped polycrystalline silicon layer.
5. semiconductor voltage-stabilizing device according to claim 1 is characterized in that described polysilicon-insulating barrier-semiconductor structure is present in the periphery of described second semiconductor region, is by the polysilicon that mixes, silicon dioxide layer, and first semiconductor region is constituted.
6. semiconductor voltage-stabilizing device according to claim 1 is characterized in that described substrate base is made of the semiconductor of low resistance, and its resistivity is higher than 0.001 ohmcm.
7. semiconductor voltage-stabilizing device according to claim 1 is characterized in that, described first conductivity is the N type, and described second conductivity is the P type.
8. semiconductor voltage-stabilizing device according to claim 1 is characterized in that, described first conductivity is the P type, and described second conductivity is the N type.
9. the manufacture method of a semiconductor voltage-stabilizing device comprises:
Growth first silicon dioxide layer on the substrate base that constitutes by first conductive semiconductor;
Form first window at described first silicon dioxide layer by silicon dioxide layer photoetching and corrosion, growth second silicon dioxide layer in first window;
In described first window, form second window littler than described first window by silicon dioxide layer photoetching and corrosion;
Deposition one deck polysilicon and described polysilicon mixed with second conductive impurities on described first window;
Described polysilicon becomes required figure via dry method or wet etching, and further do to advance diffusion to form heavily doped second semiconductor region by described second window with second conductivity to described second conductive impurities, between first window and second window, the annular region that is established in around second semiconductor region constitutes polysilicon-insulating barrier-semiconductor structure, by the described polysilicon that covers, second silicon dioxide layer and first semiconductor region form.
10. the manufacture method of semiconductor voltage-stabilizing device according to claim 9 is characterized in that, described substrate base is made of the semiconductor of low resistance, and its resistivity is higher than 0.001 ohmcm.
11. the manufacture method of semiconductor voltage-stabilizing device according to claim 9 is characterized in that, described second semiconductor region forms in second window.
12. the manufacture method of semiconductor voltage-stabilizing device according to claim 9 is characterized in that, the thickness of described second silicon dioxide layer is between 20 dust to 1000 dusts.
13. the manufacture method of semiconductor voltage-stabilizing device according to claim 9 is characterized in that, with the thickness of the polysilicon layer of low pressure chemical sedimentation deposition at 1000 dust to 3000 dusts.
14. the manufacture method of semiconductor voltage-stabilizing device according to claim 9 is characterized in that, the mode of described polysilicon layer being mixed described second conductive-type impurity comprises that ion injects or the impurity source diffusion.
15. the manufacture method of semiconductor voltage-stabilizing device according to claim 9 is characterized in that, the temperature in described second conductive impurities propelling diffusion is between 900 degrees centigrade to 1200 degrees centigrade.
16. the manufacture method according to each described semiconductor voltage-stabilizing device in the claim 9～15 is characterized in that, described first conductivity is the N type, and described second conductivity is the P type.
17. the manufacture method according to each described semiconductor voltage-stabilizing device in the claim 9～15 is characterized in that, described first conductivity is the P type, and described second conductivity is the N type.
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|---|---|---|---|
| CN2007100432607A CN101335307B (en) | 2007-06-29 | 2007-06-29 | Semiconductor voltage-stabilizing device and manufacturing method therefor |
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|---|---|---|---|
| CN2007100432607A CN101335307B (en) | 2007-06-29 | 2007-06-29 | Semiconductor voltage-stabilizing device and manufacturing method therefor |
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|---|---|
| CN101335307A CN101335307A (en) | 2008-12-31 |
| CN101335307B true CN101335307B (en) | 2010-12-08 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108109912B (en) * | 2012-09-27 | 2021-08-03 | 罗姆股份有限公司 | Chip diode, method for manufacturing chip diode, circuit module, and electronic device |
| CN104538300A (en) * | 2014-12-19 | 2015-04-22 | 扬州国宇电子有限公司 | Technological method for adjusting barrier height of Schottky diode by doping silicon dioxide film |
| CN104659110B (en) * | 2014-12-22 | 2017-11-21 | 天津天物金佰微电子有限公司 | Voltage-regulator diode and its processing technology |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4948989A (en) * | 1989-01-31 | 1990-08-14 | Science Applications International Corporation | Radiation-hardened temperature-compensated voltage reference |
| US5386138A (en) * | 1993-06-10 | 1995-01-31 | Nec Corporation | Semiconductor device with diodes connected in series |
-
2007
- 2007-06-29 CN CN2007100432607A patent/CN101335307B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4948989A (en) * | 1989-01-31 | 1990-08-14 | Science Applications International Corporation | Radiation-hardened temperature-compensated voltage reference |
| US5386138A (en) * | 1993-06-10 | 1995-01-31 | Nec Corporation | Semiconductor device with diodes connected in series |
Non-Patent Citations (2)
| Title |
|---|
| JP特开2006-179518A 2006.07.06 |
| JP特开平4-215468A 1992.08.06 |
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