CN101330089A - Detection device and electronic apparatus - Google Patents

Abstract

The present invention provides a detector comprising: a scanning line (10) arranged on a substrate, a detection line (14), first power supply cords (11a, 11b), a second power supply cord (12), and a pixel circuit (40) arranged corresponding to the intersection point of the scanning line (10) and the detection line (14). The pixel circuit (40) comprises an amplifier transistor (45) for supplying the detection signal corresponding to an electrical potential of a gate electrode to the detection line (14), a detection element connected with the gate electrode of the amplifier transistor (45) leading the gate electrical potential of the amplifier transistor (45) to change according to the change of the extrinsic factor, a reset transistor (41) which activates according to the electrical potential of the scanning line (10), and a first capacity element for holding the grid electrical potential of the amplifier transistor (45). The scanning line (10) is formed at layer which is different from the gate electrode of the amplifier transistor (45) and the gate electrode of the reset transistor (41), and at least a part of the scanning line is overlapped with the gate electrode of the reset transistor (41) under overhead view condition.

Description

Checkout gear and electronic equipment

Technical field

The electronic equipment that the present invention relates to checkout gear and carried this checkout gear.

Background technology

As one of checkout gear that uses in the middle of 2 dimension transducers, imageing sensors, optical profile type touch sensor etc., known have a following checkout gear.This checkout gear constitutes, have photo-electric conversion element, change capacity cell and the transistor of accumulating the quantity of electric charge according to the light income of this photo-electric conversion element as detecting element, and by transistorized conduction and cut-off action, read the electric charge accumulation amount (for example, with reference to patent documentation 1) in the capacity cell.

In addition, in said structure, accumulate electric capacity if photo-electric conversion element is replaced as, then above-mentioned capacity cell accumulate the quantity of electric charge, change according to this increase and decrease of accumulating the extraneous factor of capacitance.As checkout gear, also can adopt to use and accumulate the structure of electric capacity as detecting element.

[patent documentation 1] spy opens flat 4-212458 communique

Above-mentioned checkout gear is got over configuration detection element to high-density, and its detection resolution is high more.But, dispose transistor and the various inscapes such as wiring that are connected with transistorized terminal to high-density, the problem that can bring characteristics of transistor to worsen, property difference is increased.Perhaps because of the complicated problem that causes signal delay, decrease in yield of Wiring structure.

Summary of the invention

The present invention proposes at least a portion that addresses the above problem, can be in such a way or application examples realize.

[application examples 1] a kind of checkout gear has: substrate; Be configured in the multi-strip scanning line on the aforesaid substrate, many detection lines, many articles the 1st power lines, many articles the 2nd power lines; And a plurality of unit circuits that are provided with corresponding to the crosspoint of above-mentioned scan line and above-mentioned detection line, above-mentioned unit circuit has: the 1st transistor, its the 1st terminal is connected with above-mentioned detection line, the 2nd terminal is connected with above-mentioned the 1st power line, and supplies with the detection signal corresponding with the current potential of gate electrode to above-mentioned detection line; Detecting element, it is connected with the above-mentioned the 1st transistorized gate electrode, and the above-mentioned the 1st transistorized grid potential is changed according to extraneous factor; The 2nd transistor, its 1st terminal is connected with the above-mentioned the 1st transistorized gate electrode, and the 2nd terminal is connected with above-mentioned the 2nd power line, and gate electrode is connected with above-mentioned scan line; And the 1st capacity cell, it keeps the above-mentioned the 1st transistorized grid potential, above-mentioned scan line is formed in the layer different with the above-mentioned the 2nd transistorized gate electrode with the above-mentioned the 1st transistorized gate electrode, and is configured to: overlapping with at least a portion of above-mentioned the 2nd transistorized gate electrode under the situation of overlooking.

According to such structure,,, can detect extraneous factor so go out above-mentioned electric current by the unit circuit of scanning line selection by sequence detection because the 1st transistor is to the corresponding big or small electric current with extraneous factor of detection line output.Here, because scan line is formed in different with the gate electrode layers, and is configured to pass through from the top of the 2nd transistorized gate electrode, so allocation unit circuit to high-density.In the above description, so-called " overlooking under the situation " is meant the meaning of " observing from the normal direction of substrate ".In said structure, also can be electrically connected the 1st power line and the 2nd power line.That is, also can shared the 1st power line and the 2nd power line.Like this, can simplify the circuit structure of checkout gear.And, can simplify the layer structure of unit circuit and the densification that realizes unit circuit.

In above-mentioned detection device, scan line and the above-mentioned the 2nd transistorized gate electrode are on the above-mentioned the 2nd transistorized gate electrode, by being electrically connected at the formed contact hole of the normal direction of aforesaid substrate [application examples 2].

According to such structure, owing to scan line is connected with gate electrode in the normal direction of substrate, so do not need to be used for the zone of the connecting wiring between scan line and the 2nd transistor.Therefore, allocation unit circuit to high-density.

[application examples 3] is in above-mentioned detection device, the above-mentioned the 1st transistorized channel region has certain angle with the bearing of trend that the above-mentioned the 2nd transistorized channel region is configured to relative above-mentioned scan line, and above-mentioned scan line is configured under the situation of overlooking across the above-mentioned the 1st transistorized channel region and the above-mentioned the 2nd transistorized channel region.

According to such structure, allocation unit circuit to high-density.

[application examples 4] is in above-mentioned detection device, above-mentioned detection line is formed in the different layers with above-mentioned the 2nd power line, above-mentioned detection line is configured under the situation of overlooking to extend along the bearing of trend of above-mentioned the 2nd power line, and its at least a portion and above-mentioned the 2nd power line are overlapping.

According to such structure, because can be with less area configuration detection line and the 2nd power line, so can dwindle the configuration space of unit circuit at line direction, thus unit circuit can be formed to high-density.In addition, in above-mentioned structure, also can be electrically connected the 1st power line and the 2nd power line.That is, also can shared the 1st power line and the 2nd power line.Like this, can simplify the circuit structure of checkout gear.And, can simplify the layer structure of unit circuit and the densification that realizes unit circuit.

[application examples 5] along 2 above-mentioned the 1st power lines of adjacent above line configuration, is formed in the different mutually layers in the row of above-mentioned unit circuit in above-mentioned detection device.

According to such structure, can under the situation of overlooking, be configured in approaching position to the 1st power line.Therefore, can dwindle the configuration space of the unit circuit on column direction.

In above-mentioned detection device, the above-mentioned the 1st transistorized orientation is the direction of extending along the above-mentioned the 2nd transistorized orientation [application examples 6].

According to such structure, because the 1st transistorized orientation is a direction along the 2nd transistorized channel length, so can be in the zone of minimum the 1st transistorized channel region and the 2nd transistorized channel region centralized configuration.Here, so-called channel length is meant, the length of extending to the direction of the 2nd terminal from transistorized the 1st terminal in the channel region.Thus, can dispose the 1st transistor and the 2nd transistor to high-density.In addition, in said structure, also can be electrically connected the 1st power line with the 2nd power line.That is, also can shared the 1st power line and the 2nd power line.Like this, can simplify the circuit structure of checkout gear.And, can simplify the layer structure of unit circuit and the densification that realizes unit circuit.

In above-mentioned detection device, above-mentioned the 1st transistor and above-mentioned the 2nd transistor are configured to its orientation and intersect with the bearing of trend of above-mentioned scan line and the bearing of trend of above-mentioned detection line under the situation of overlooking [application examples 7].

According to such structure, owing to can dwindle the configuration space of the 1st transistor and the 2nd transistorized channel region, so can dwindle the configuration space of unit circuit.Thus, can improve the resolution of checkout gear.In above-mentioned, so-called " overlooking under the situation " is meant the meaning of " observing from the normal direction of substrate ".

[application examples 8] is in above-mentioned detection device, bearing of trend along above-mentioned scan line under the situation of overlooking disposes the above-mentioned the 1st transistorized the 1st terminal and the above-mentioned the 2nd transistorized the 1st terminal, and the bearing of trend along above-mentioned scan line under the situation of overlooking disposes the above-mentioned the 1st transistorized the 2nd terminal and the above-mentioned the 2nd transistorized the 2nd terminal.

According to such structure, can be configured to linearity along the upwardly extending wiring in the side of scan line.Therefore, can prevent the signal delay that causes because of the complexity that connects up.

In above-mentioned detection device, above-mentioned the 1st transistor is vertical with the above-mentioned the 2nd transistorized orientation bearing of trend with above-mentioned scan line under the situation of overlooking [application examples 9].

According to such structure, can be overlapping at the upwardly extending wiring in the side vertical and the 1st transistor and the 2nd transistor with scan line, thus can dispose these inscapes to high-density.

[application examples 10] is in above-mentioned detection device, above-mentioned the 1st capacity cell has the 1st electrode and the 2nd electrode, and the above-mentioned the 1st transistorized channel region and the above-mentioned the 2nd transistorized channel region are covered by at least one side of above-mentioned the 1st electrode and above-mentioned the 2nd electrode under the situation of overlooking.

According to such structure and since the 1st transistorized channel region and the 2nd transistorized channel region under the situation of overlooking by at least one side covering in the 1st electrode and the 2nd electrode, so can utilize 1 or 2 light shield layers to block channel region.Therefore, can reduce the 1st transistor and the 2nd transistorized cut-off current.In said structure, also can be electrically connected the 1st power line with the 2nd power line.That is, also can shared the 1st power line and the 2nd power line.Like this, can simplify the circuit structure of checkout gear.And, can simplify the layer structure of unit circuit and the densification that realizes unit circuit.

[application examples 11] in above-mentioned detection device, above-mentioned the 1st electrode is done the electrode of above-mentioned detecting element by dual-purpose.

According to such structure, can enlarge the occupied area of the 1st capacity cell and detecting element respectively.

[application examples 12] a kind of checkout gear has: substrate; Be configured in the multi-strip scanning line on the aforesaid substrate, many detection lines, many articles the 1st power lines, many articles the 2nd power lines; And a plurality of unit circuits that are provided with corresponding to the crosspoint of above-mentioned scan line and above-mentioned detection line, above-mentioned unit circuit has: the 1st transistor, its the 1st terminal is connected with above-mentioned detection line, the 2nd terminal is connected with above-mentioned the 1st power line, and supplies with the detection signal corresponding with the current potential of gate electrode to above-mentioned detection line; Detecting element, it is connected with the above-mentioned the 1st transistorized gate electrode, and the above-mentioned the 1st transistorized grid potential is changed according to extraneous factor; The 2nd transistor, its 1st terminal is connected with the above-mentioned the 1st transistorized gate electrode, and the 2nd terminal is connected with above-mentioned the 2nd power line, and gate electrode is connected with above-mentioned scan line; And the 1st capacity cell, it keeps the above-mentioned the 1st transistorized grid potential, in the row of above-mentioned unit circuit, be sandwiched in the position between 2 adjacent above lines, be formed with above-mentioned the 1st power line, and adjacent per 2 above lines form 1 above-mentioned the 1st power line, and above-mentioned the 1st power line is to the unit circuit supply power of 2 adjacent above lines.

According to such structure,,, can detect extraneous factor so go out above-mentioned electric current by the unit circuit of scanning line selection by sequence detection because the 1st transistor is to the corresponding big or small electric current with extraneous factor of detection line output.Here and since the 1st power line in adjacent unit circuit by shared, so can reduce the quantity of the 1st power line, thereby can improve the configuration density of unit circuit.

[application examples 13] clips the inscape of 2 adjacent above-mentioned unit circuits of above-mentioned the 1st power line in above-mentioned detection device, with the bearing of trend line symmetrical manner formation of above-mentioned relatively the 1st power line.

According to such structure, can reduce the property difference of unit circuit.

[application examples 14] clips a pair of above-mentioned transistorized channel region in 2 adjacent above-mentioned unit circuits of above-mentioned the 1st power line in above-mentioned detection device, use the silicon fiml that fuses to constitute.

According to such structure,, can improve the rate of finished products in the manufacturing process owing to can reduce the quantity of the contact site of the 1st transistor AND gate wiring.

[application examples 15] is in above-mentioned detection device, the above-mentioned the 2nd transistorized channel region, use to cross over the silicon fiml that the boundary line of 2 adjacent above-mentioned unit circuits fuses and constitute, a pair of above-mentioned the 2nd transistor that is formed in above-mentioned adjacent 2 unit circuits has the 2nd shared terminal, and above-mentioned the 2nd shared terminal is electrically connected with above-mentioned the 2nd power line.

According to such structure, owing to can reduce the quantity of the contact site of the 1st transistor AND gate wiring, so can improve the total rate of finished products of manufacturing process.In addition, in said structure, also can be electrically connected the 1st power line with the 2nd power line.That is, also can shared the 1st power line and the 2nd power line.Like this, can simplify the circuit structure of checkout gear.And, can simplify the layer structure of unit circuit and the densification that realizes unit circuit.

[application examples 16] a kind of checkout gear has: substrate; Be configured in the multi-strip scanning line on the aforesaid substrate, many detection lines, many power lines; And a plurality of unit circuits that are provided with corresponding to the crosspoint of above-mentioned scan line and above-mentioned detection line, above-mentioned unit circuit has: the 1st transistor, its the 1st terminal is connected with above-mentioned detection line, the 2nd terminal is connected with said power, and supplies with the detection signal corresponding with the current potential of gate electrode to above-mentioned detection line; Detecting element, it is connected with the above-mentioned the 1st transistorized gate electrode, and the above-mentioned the 1st transistorized grid potential is changed according to extraneous factor; The 2nd transistor, its 1st terminal is connected with the above-mentioned the 1st transistorized gate electrode, and the 2nd terminal is connected with said power, and gate electrode is connected with above-mentioned scan line; And the 1st capacity cell, it keeps the above-mentioned the 1st transistorized grid potential, above-mentioned scan line is formed in the layer different with the above-mentioned the 2nd transistorized gate electrode with the above-mentioned the 1st transistorized gate electrode, and is overlapping with at least a portion of above-mentioned the 2nd transistorized gate electrode under the situation of overlooking.

According to such structure,,, can detect extraneous factor so go out above-mentioned electric current by the unit circuit of scanning line selection by sequence detection because the 1st transistor is to the corresponding big or small electric current with extraneous factor of detection line output.Here, scan line is formed in different with the gate electrode layers, and passes through from the 2nd transistorized gate electrode top, so allocation unit circuit to high-density.In addition, because each unit circuit can adopt the structure with single power supply line,, can simplify the circuit structure of checkout gear so compare with structure with many power lines.In addition, owing to need in different layers, not form many power lines, can simplify the layer structure of unit circuit.And, can reduce the configuration area of power line, more high accuracy component unit circuit.

In above-mentioned detection device, above-mentioned detection line and said power are formed in the different layers [application examples 17], and above-mentioned detection line is configured to, and the bearing of trend to said power under the situation of overlooking extends, and at least a portion and said power are overlapping.

According to such structure since can be in small size configuration detection line and power line, so can dwindle the configuration space of unit circuit, can form unit circuit to high-density at line direction.In addition, because each unit circuit can adopt the structure with single power supply line,, can simplify the circuit structure of checkout gear so compare with structure with many power lines.In addition, owing to need in different layers, not form many power lines, can simplify the layer structure of unit circuit.And, can reduce the configuration area of power line, more high accuracy component unit circuit.

[application examples 18] in above-mentioned detection device, the above-mentioned the 1st transistorized orientation is the direction along above-mentioned the 2nd transistorized orientation.

According to such structure, because the 1st transistorized orientation is a direction along the 2nd transistorized orientation, so can be in the zone of minimum the 1st transistorized channel region and the 2nd transistorized channel region centralized configuration.Can dispose the 1st transistor and the 2nd transistor to high-density thus.In addition, because each unit circuit can adopt the structure with single power supply line,, can simplify the circuit structure of checkout gear so compare with structure with many power lines.In addition, owing to need in different layers, not form many power lines, can simplify the layer structure of unit circuit.And, can reduce the configuration area of power line, more high accuracy component unit circuit.

[application examples 19] is in above-mentioned detection device, above-mentioned the 1st capacity cell has the 1st electrode and the 2nd electrode, the above-mentioned the 1st transistorized channel region and the above-mentioned the 2nd transistorized channel region can be covered by at least one side of above-mentioned the 1st electrode and above-mentioned the 2nd electrode under the situation of overlooking.

According to such structure, because the 1st transistorized channel region and the 2nd transistorized channel region cover by at least one side of the 1st electrode and the 2nd electrode under the situation of overlooking, so can utilize 1 or 2 light shield layers to block channel region.Therefore, can reduce the 1st transistor and the 2nd transistorized cut-off current.In addition, because each unit circuit can adopt the structure with single power supply line,, can simplify the circuit structure of checkout gear so compare with structure with many power lines.In addition, owing to need in different layers, not form many power lines, can simplify the layer structure of unit circuit.And, can reduce the configuration area of power line, more high accuracy component unit circuit.

[application examples 20] possessed the electronic equipment of above-mentioned detection device.

According to such structure, can realize having possessed the electronic equipment of the input interface of high detection sensitivity.

Description of drawings

Fig. 1 is the block diagram of the structure of expression checkout gear.

Fig. 2 is the circuit diagram of the structure of remarked pixel circuit.

Fig. 3 is the block diagram of the structure of expression 1X driver.

Fig. 4 is the block diagram of the structure of expression 2X driver.

Fig. 5 is the sequential chart of signal waveform of each one of expression checkout gear.

Fig. 6 is the key diagram of the signal flow in the expression reseting period.

Fig. 7 is the key diagram of the signal flow during the expression initialization.

Fig. 8 is the key diagram of the signal flow between the expression detection period.

Fig. 9 is the key diagram of the biasing of remarked pixel circuit.

Figure 10 is the curve that changes the time of the current potential of expression detection line.

Figure 11 is the vertical view in the zone that comprises a plurality of image element circuits of checkout gear.

Figure 12 is the amplification plan view of image element circuit.

Figure 13 is the vertical view of the 1st layer, the 3rd layer configuration in the inscape of expression Figure 11.

Figure 14 is the vertical view of the 1st layer, the 2nd layer, the 4th layer configuration in the inscape of expression Figure 11.

Figure 15 is the vertical view of the 1st layer, the 5th layer configuration in the inscape of expression Figure 11.

Figure 16 is the vertical view of the configuration of expression the 1st capacity cell and photodiode.

Figure 17 extracts the vertical view that the 1st power line and semiconductor layer etc. are represented out from Figure 11.

Figure 18 is the vertical view of variation of the configuration of expression the 1st power line.

Figure 19 is the profile of the checkout gear of the B-B line in Figure 11.

Figure 20 is the profile of the checkout gear of the C-C line in Figure 11.

Figure 21 is the profile that has used the checkout gear of the 2nd capacity cell as detecting element.

Figure 22 is the circuit diagram of the checkout gear of variation 1-2.

Figure 23 is the vertical view in the zone that comprises a plurality of image element circuits of the checkout gear of variation 1-2.

Figure 24 is the vertical view of the 1st layer, the 3rd layer configuration in the inscape of expression Figure 23.

Figure 25 is the vertical view in the zone that comprises a plurality of image element circuits of checkout gear.

Figure 26 is the amplification plan view of image element circuit.

Figure 27 is the vertical view of the 1st layer, the 5th layer configuration in the inscape of expression Figure 25.

Figure 28 is the vertical view of the 1st layer, the 2nd layer configuration in the inscape of expression Figure 25.

Figure 29 is the vertical view of the 1st layer, the 3rd layer, the 4th layer configuration in the inscape of expression Figure 25.

Figure 30 is the profile of the checkout gear of the D-D line of expression in Figure 25.

Figure 31 is the profile that has used the checkout gear of the 2nd capacity cell as detecting element.

Figure 32 is the vertical view in the zone that comprises a plurality of image element circuits of the checkout gear of variation 2-2.

Figure 33 is the vertical view of the 1st layer, the 5th layer configuration in the inscape of expression Figure 32.

Figure 34 is the stereogram as the mobile phone of electronic equipment.

Among the figure: 1,2-checkout gear; 5,6-substrate; The 10-scan line; 11,11a, 11b-the 1st power line; 12-the 2nd power line; The 14-detection line; 40-is as the image element circuit of unit circuit; 41-is as the 2nd transistorized reset transistor; 41a, 45a-semiconductor layer; 41c, 45c-channel region; 41d, 45d-drain region; 41g, 45g-gate electrode; 41s, 45s-source region; 43-the 1st capacity cell; 43a-the 1st electrode; 43b-the 2nd electrode; The 43d-dielectric film; 44-the 2nd capacity cell; 44b-the 2nd electrode; The 44d-insulating barrier; 45-is as the 1st transistorized amplifier transistor; 47-is as the photodiode of detecting element; The 48-anode; The 51-underlying insulation film; The 52-gate insulating film; 53,54,55-interlayer dielectric; The 56-planarization film; The 57-insulating barrier; 61～67-repeater electrode; 71～78,79a, 79b, 81～89-contact hole; 500-is as the mobile phone of electronic equipment.

Embodiment

Below, with reference to accompanying drawing, the execution mode of checkout gear and electronic equipment is described.In addition, in each accompanying drawing shown below,,, there is an amount of difference so the size of inscape is compared with the inscape of reality with ratio because each inscape is adopted the size dimension that can discern on drawing.

＜the 1 execution mode 〉

(structure of A. circuit and action)

Fig. 1 represents the structure of the checkout gear of the 1st execution mode.As shown in the drawing, checkout gear 1 has pixel region A, Y driver 100,1X driver 200A, 2X driver 200B and control circuit 300.Wherein, in pixel region A, be formed with m article of the 1st power line 11 on directions X, extending in couples at the m bar scan line 10 that extends on the directions X, with each scan line 10, with the upwardly extending n in the Y side of directions X quadrature article of the 2nd power line 12 and with each the 2nd power line 12 the upwardly extending n bar detection line 14 in Y side in couples.With the corresponding position, each crosspoint of scan line 10 and the 2nd power line 12, dispose image element circuit 40 (unit circuit).Therefore, these image element circuits 40 be arranged be configured to vertical m capable * horizontal n row rectangular.

Y driver 100 is chosen in each image element circuit 40 of arranging among the pixel region A in each horizontal scan period with behavior unit, and to each scan line 10 output scanning signal Y1～Ym.1X driver 200A is to the detection signal X1～Xn that supplies with from n bar detection line 14 maintenances of take a sample, and according to the result that sampling keeps, detection signal VID is synthesized in generation.In addition, 2X driver 200B is to the 2nd power line 12 supply line voltage RSL.Supply voltage RSL becomes the side among the 1st power supply potential VDD or the 2nd power supply potential VSS.And 1X driver 200A is pre-charged to the 2nd power supply potential VSS to each detection line 14 with predetermined timing.As described later, when the current potential of the 1st power line 11 is the 1st power supply potential VDD, from the detection signal X1～Xn of the corresponding size of each image element circuit 40 outputs with the light quantity of incident light.In addition, in each detection signal X1～Xn, the signal that time division multiplexing is exported from m the image element circuit of arranging at column direction 40.Control circuit 300 is supplied with various control signals such as clock signal to Y driver 100,1X driver 200A and 2X driver 200B.

The structure of Fig. 2 remarked pixel circuit 40.Though this image element circuit 40 is configured in i (i is the integer of 1≤i≤m) row j (j is the integer of 1≤j≤n) row, other image element circuits 40 also are to constitute equally.Image element circuit 40 has the photodiode 47 as detecting element.Photodiode 47 is used to export the electric current of corresponding size with the light quantity of incident light, is the photo-electric conversion element that transform light energy is become electric energy.The anode of photodiode 47 is connected with fixed potential, and its negative electrode is connected with grid as the 1st transistorized amplifier transistor 45.In addition, between the grid of amplifier transistor 45 and the 1st power line 11, be provided with the 1st capacity cell 43 of the grid potential that keeps amplifier transistor 45.In the 1st capacity cell 43, accumulate from the electric charge of photodiode 47 outputs.Between the grid and the 2nd power line 12 of amplifier transistor 45, be provided with as the 2nd transistorized reset transistor 41.This reset transistor 41 is as switch element performance function, when sweep signal Yi becomes when selecting current potential, becomes conducting state, when becoming non-selection current potential, becomes cut-off state.When reset transistor 41 was conducting state, the current potential of the 2nd power line 12 was fed into the grid of amplifier transistor 45.And in addition, the drain electrode of amplifier transistor 45 is electrically connected with the 1st power line 11, and its source electrode is electrically connected with detection line 14.In addition, because to the relation of the drain electrode in the amplifier transistor 45 and source electrode, a side high current potential is defined as drain electrode, a side low current potential is defined as source electrode, so according to biasing, will drain sometimes and source electrode is put upside down.

Fig. 3 is the block diagram of expression 1X driver 200A.1X driver 200A has each the corresponding processing unit Ua1～Uan with n bar detection line 14.Here, though only processing unit Ua1 is described, other processing units also have same structure.Transmission gate 20, capacity cell 21 and capacity cell 22 are as sample-and-hold circuit performance function.When transmission gate 20 is high level at sampled signal SHG, become conducting state, become cut-off state during low level.Obtain thus and keep detection signal X1.In addition, inverter 23 is as amplifying circuit performance function.Transmission gate 24 is used for the input of inverter 23 biasing is adjusted into intermediate potential.That is, when control signal AMG became high level, the input and output of inverter 23 were by short circuit, thereby an input current potential biasing is adjusted into intermediate potential.The lead-out terminal of inverter 23 is connected with wiring L by switching transistor 25.The grid of switching transistor 25 is supplied to the output signal of shift register 26.Shift register 26 generates output signal by will pass on beginning pulsed D X forwarding successively according to X clock signal XCK.According to this output signal, each processing unit Ua1～Uan supplies with detection signal to wiring L exclusively, and in wiring L, detection signal is merged, and exports as merging detection signal VID by buffer B.In addition, supply with sampled signal SHG, control signal AMG, pass on beginning pulsed D X and X clock signal XCK from control circuit 300.

Fig. 4 is the block diagram of the structure of expression 2X driver 200B.2X driver 200B has respectively each the corresponding processing unit Ub1～Ubn with the n row.Here, though only processing unit Ub1 is described, other processing units also have same structure.Transistor 27 and transistor 28 carry out conduction and cut-off control by control signal SG1 and control signal SG2.Here, control signal SG2 is the reverse signal of control signal SG1.Therefore, transistor 27 and transistor 28 mutual exclusions ground become conducting state, supply with the 1st power supply potential VDD or the 2nd power supply potential VSS to the 2nd power line 12.In addition, transistor 29 becomes conducting state during for high level at control signal RG, supplies with the 2nd power supply potential VSS to detection line 14.Thus, can carry out precharge to detection line 14.

Below, the action of checkout gear 1 is described.Fig. 5 is the sequential chart of signal waveform of each one of expression checkout gear 1.Sweep signal Y1～Ym order during the part of each horizontal scan period becomes high level.As shown in the drawing, i horizontal scan period by reseting period Trest, initialization during between Tini, detection period between Tdet and reading duration Tread constitute.

At first, in reseting period Trest, the grid potential of amplifier transistor 45 is set at the 2nd power supply potential VSS.As shown in Figure 5, during this period, because sweep signal Yi becomes high level, so reset transistor 41 becomes conducting state.At this moment, because control signal SG1 is a low level, and control signal SG2 is a high level, so transistor 28 becomes conducting state, the 2nd power supply potential VSS is fed into the grid of amplifier transistor 45 by the 2nd power line 12.And,,, detection line 13 is precharged as the 2nd power supply potential VSS so transistor 29 becomes conducting state because control signal RG is a high level.Under the situation of m=n=3, as shown in Figure 6, in whole image element circuits 40, the grid potential of amplifier transistor 45 is set to the 2nd power supply potential VSS.

Then, among the Tini, control signal SG1 is a high level during initialization, and transistor 27 becomes conducting state, and the 1st power supply potential VDD is fed into the grid of amplifier transistor 45 via the 2nd power line 12 and reset transistor 41.As shown in Figure 7, during initialization, among the Tini, be supplied to the row that sweep signal Y1～Ym becomes high level that is only limited to of the 1st power supply potential VDD.It in example shown in Figure 7 the 2nd row.Image element circuit 40 for other row is remained on the 2nd power supply potential VSS that writes among the reseting period Trest by the 1st capacity cell 43.In addition, during initialization among the Tini, because sampled signal SHG and control signal AMG are high level, so transmission gate 20 and 24 becomes conducting state.At this moment, because detection line 14 has been supplied with the 2nd power supply potential VSS, so the current potential of square end of capacity cell 21 becomes the 2nd power supply potential VSS, the current potential of the opposing party's terminal is set to intermediate potential.Thus, the current potential of capacity cell 21 is initialised.

Then, among the Tdet, as shown in Figure 5, the current potential of power supply signal Gpi is the 1st power supply potential VDD between detection period.In addition, because control signal RG is a low level,, do not supply with the 2nd power supply potential VSS to detection line 14 so transistor 29 becomes cut-off state.As shown in Figure 8, between detection period among the Tdet, from the image element circuit 40 output detection signal X1～X3 of selected row (being the 2nd row in this example).

Fig. 9 represents the biasing of the image element circuit 40 of selected the 2nd row the 2nd row.As shown in the drawing, if the voltage of photodiode 47 is made as Vpd, then the grid potential Vg of amplifier transistor 45 is Vg=VDD-Vpd.Voltage Vpd changes according to the light quantity to the incident light of photodiode 47.That is, photodiode 47 changes the grid potential of amplifier transistor 45 according to the light quantity as the incident light of extraneous factor.And, the electric current of determining according to grid potential as detection signal X2, is outputed to detection line 14.In other words, amplifier transistor 45 is supplied with the detection signal X2 corresponding with the current potential of gate electrode to detection line 14.

If the current potential of detection line 14 is made as Vsense, then current potential Vsense changes as shown in Figure 10.Here, characteristic Q1 represents that the light quantity of incident light is few, dark situation, and characteristic Q2 represents that the light quantity of incident light is big, bright situation.That is, under dark situation, because the voltage Vpd of photodiode 47 is little, so grid potential Vg height.Therefore, the electric current that flows out from the source electrode of amplifier transistor 45 is big, and the current potential Vsense of detection line 14 is risen rapidly.On the other hand, under bright situation, because the voltage Vpd of photodiode 47 is big, so grid potential Vg is low.Therefore, the electric current that flows out owing to the source electrode from amplifier transistor 45 is little, so the current potential Vsense of detection line 14 slowly rises.And when Vsense=Vg-Vth, amplifier transistor 45 becomes cut-off state.Like this, because the light quantity of corresponding incident light, the quantity of electric charge difference of inflow detection line 14 is so come out it in above-mentioned processing unit Ua2 as voltage detecting.

(concrete structure of B. image element circuit)

Below, the concrete structure of image element circuit 40 is described.Figure 11 is the vertical view in the zone that comprises a plurality of image element circuits 40 of expression checkout gear 1, and Figure 12 is the amplification plan view of pixel region 40.Pixel region 40 is configured to rectangular along a plurality of row and columns.In the following description, the row or column of image element circuit 40 is abbreviated as " OK " or " row ".Figure 19, Figure 20 are respectively the profiles of the checkout gear 1 of B-B, C-C line in Figure 11.Shown in Figure 19,20, image element circuit 40 has the 1st layer of comprising semiconductor layer 41a, 45a, comprise gate electrode 41g, 45g the 2nd layer, comprise the 2nd power line 12 and detection line 14 etc. the 3rd layer, comprise scan line 10 and the 1st power line 11b etc. the 4th layer and comprise the 5th layer of the 1st power line 11Adeng.Figure 13 is the inscape of the 1st layer and the 3rd layer is extracted in expression out from an inscape shown in Figure 11 vertical view.Figure 14 is the inscape of the 1st layer, the 2nd layer and the 4th layer is extracted in expression out from an inscape shown in Figure 11 vertical view.Figure 15 is the inscape of the 1st layer and the 5th layer is extracted in expression out from an inscape shown in Figure 11 vertical view.

At first, with reference to profile shown in Figure 19, the structure of image element circuit 40 is described.On substrate 5, form the underlying insulation film 51 that constitutes by silica etc.As substrate 5, can use quartz base plate and glass substrate etc.On underlying insulation film 51, form the 1st layer that comprises semiconductor layer 41a, 45a.On the 1st layer, form the gate insulating film 52 that constitutes by silica etc., form the 2nd layer that comprises gate electrode 41g, 45g in the above.

Semiconductor layer 41a for example is made of the polysilicon film as silicon fiml, its have based on from the electric field of gate electrode 41g and form the channel region 41c of raceway groove, as the drain region 41d of the 1st terminal with as the source region 41s of the 2nd terminal.Semiconductor layer 45a is made of the polysilicon film as silicon fiml too, and have based on from the electric field of gate electrode 45g and form the channel region 45c of raceway groove, as the drain region 45d of the 1st terminal with as the source region 45s of the 2nd terminal.Semiconductor layer 41a, 45a also can adopt LDD (Lightly Doped Drain) structure.For example, also can adopt between channel region 41c (45c) and drain region 41d (45d) the low concentration drain region is set, and the structure of low concentration source region is set between channel region 41c (45c) and source region 41s (45s).

Gate electrode 41g, 45g can be by in for example Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), the Mo refractory metals such as (molybdenums) at least a, metal monomer, alloy, metal silicide, multi-crystal silicification thing, with formations such as material behind these material laminations or conductivity polysilicons.Gate electrode 41g, 45g observe under the situation of overlooking and are formed at least respectively and channel region 41c, 45c overlapping areas.Here, so-called " observing under the situation of overlooking " is meant the meaning (following same) of " observing from the normal direction of substrate 5 ".

As shown in figure 14, semiconductor layer 41a and semiconductor layer 45a are configured to be parallel to each other.That is, semiconductor layer 41a is along the bearing of trend setting of semiconductor layer 45a.Therefore, the orientation of channel region 41c becomes along the direction of the orientation of channel region 45c.Perhaps, the direction of the channel length of channel region 41c also can be parallel with the direction of the channel length of channel region 45c.Here, channel region 41c (45c) be among the semiconductor layer 41a (45a) with gate electrode 41g (45g) overlapping areas, so-called channel length is meant the length of extending to source region 41s (45s) direction from drain region 41d (45d) among the channel region 41c (45c).According to such structure, because can be channel region 41c and channel region 45c centralized configuration in the zone of minimum, so can dispose amplifier transistor 45 and reset transistor 41 to high-density.In addition, be to handle through laser annealing and under the situation of the low temperature polycrystalline silicon that forms at semiconductor layer 41a, 45a, having can be based on the advantage of the size Control transistor characteristic of channel region 41c, 45c.And, be under the situation of low temperature polycrystalline silicon particularly at semiconductor layer 41a, 45a, can make amplifier transistor 45 consistent with the current characteristics of reset transistor 41, for example, can make both conducting electric currents identical with cut-off current.In checkout gear 1, under the situation that certain image element circuit 40 is failure to actuate, must make amplifier transistor 45 and reset transistor 41 all become cut-off state reliably, according to above-mentioned structure, carry out this action easily.

More particularly, amplifier transistor 45 need improve the sensitivity of output current to grid potential near threshold region when making image element circuit 40 actions.And, under the situation that does not make its action,, need end reliably in order to obtain good S/N ratio at the detection signal Xn of the image element circuit 40 that moves.In addition, reset transistor 41 becomes cut-off state reliably by making the current potential of answering scan line 10 become low level situation, and the grid potential of the amplifier transistor 45 in the time of can keeping light to detect effectively can improve the S/N ratio of detection signal Xn.The direction of the channel length by being configured to channel region 41c becomes along the direction of the channel length of channel region 45c as described above, can easily carry out these actions.

In addition, as shown in figure 11, the channel length of channel region 41c, 45c is configured to, and the bearing of trend under the situation of overlooking intersects with the bearing of trend of scan line 10 and the bearing of trend of detection line 14.Perhaps, also can be configured to make the bearing of trend of above-mentioned channel length to become direction to the angular direction along image element circuit 40.Perhaps, also can be configured to make the bearing of trend of above-mentioned channel length to become with respect to being 45 angles of spending along the bearing of trend of scan line 10 or the bearing of trend of detection line 14.Equally, also can form with the 1st power line 11a, 11b, the 2nd power line 12 and intersect, or be the angle of 45 degree.In addition, in the present embodiment, scan line the 10, the 1st power line 11a, 11b are by transverse direction (line direction) configuration along figure, and the 2nd power line 12, detection line 14 dispose along the longitudinal direction (column direction) of figure.According to such structure,, further be the configuration space that dwindles semiconductor layer 41a, 45a, so can reduce the size of image element circuit 40 owing on the longitudinal direction of Figure 11 and transverse direction, can dwindle the configuration space of channel region 41c, 45c.Thus, can improve the resolution of checkout gear 1.

Here, be and under the situation of the low temperature polycrystalline silicon that forms at semiconductor layer 41a, 45a through laser annealing, preferentially channel region 41c, 45c are configured to annealing relatively and become 45 angles of spending with the length direction of laser beam.Like this, can finish annealing with a spot of laser radiation to semiconductor layer 41a, 45a.Therefore, can reduce the inconsistent of the characteristic that causes based on laser annealing.

In addition, as shown in Figure 11, in amplifier transistor 45, drain region 45d (the 1st terminal) and source region 45s (the 2nd terminal), under the situation of overlooking, be configured in the direction of intersecting along bearing of trend with scan line the 10, the 1st power line 11a, 11b, the 2nd power line 12 and detection line 14.Perhaps also can be drain region 45d and source region 45s the angular direction is disposed along image element circuit 40.Perhaps, also can be drain region 45d, source region 45s direction configuration along 10 one-tenth miter angles of relative scanning line.Equally, in reset transistor 41, drain region 41d (the 1st terminal) and source region 41s (the 2nd terminal) are configured in the direction of intersecting along the bearing of trend with scan line the 10, the 1st power line 11a, 11b, the 2nd power line 12, detection line 14 under the situation of overlooking.Perhaps, also can be drain region 41d and source region 41s the angular direction is disposed along image element circuit 40.Perhaps also can drain region 41d, source region 41s along the direction configuration of 10 one-tenth miter angles of relative scanning line.According to such structure, the state that can become to be separated from each other each transistorized the 1st terminal and the 2nd terminal arrangement.In addition, when the configuration of the wiring of carrying out extending, can be suppressed at the minimal while, be configured to linearity in handle and amplifier transistor 45 and reset transistor 41 overlapping areas at the longitudinal direction of Figure 11 and transverse direction.Therefore, can prevent the signal delay that causes because of the complexity that connects up.

And as shown in figure 11, the drain region 45d of amplifier transistor 45 and the drain region 41d of reset transistor 41 are disposed by the bearing of trend along scan line 10 and the 1st power line 11a, 11b under the situation of overlooking.In addition, the source region 41s of the source region 45s of amplifier transistor 45 and reset transistor 41 is disposed by the bearing of trend along scan line 10 and the 1st power line 11a, 11b under the situation of overlooking.According to such structure, the wiring that the transverse direction (line direction) of Figure 11 can be extended, promptly scan line the 10, the 1st power line 11a, 11b are configured to linearity.Therefore, can prevent the signal delay that causes because of the complexity that connects up.

In addition, gate electrode 45g is extended the drain region 41d position overlapped that is set to reset transistor 41 under the situation of overlooking, and is electrically connected with drain region 41d by contact hole 72 (Figure 19).Thus, can utilize the output control amplifier transistor 45 of reset transistor 41.By making semiconductor layer 41a, 41b become configuration as described above, drain region 41d is positioned at from channel region 45c extends on the line segment of short-axis direction of semiconductor layer 45a, promptly be present on the perpendicular bisector of semiconductor layer 45a.Therefore, gate electrode 45g, can easily be formed on the 41d of drain region only to the unidirectional extension of the short-axis direction of semiconductor layer 45a by being initial point with channel region 45c.And, can guarantee that the contact site among the 41d of drain region is bigger.

Return Figure 19, on the 2nd layer, the interlayer dielectric 53 across being made of silica etc. is formed with the 3rd layer that comprises the 2nd power line 12, detection line 14 etc.In addition, on the 3rd layer, also be formed with repeater electrode 61,62,65 (Figure 13, Figure 20).The 2nd power line 12 is electrically connected with the source region 41s of reset transistor 41 by connecting the contact hole 71 that interlayer dielectric 53 and gate insulating film 52 are provided with.Detection line 14 is electrically connected with the drain region 45d of amplifier transistor 45 by connecting the contact hole 73 that interlayer dielectric 53 and gate insulating film 52 are provided with.Repeater electrode 61 is electrically connected with the drain region 41d of reset transistor 41 by connecting the contact hole 72 that interlayer dielectric 53 and gate insulating film 52 are provided with.Repeater electrode 62,65 is electrically connected with the source region 45s of amplifier transistor 45 by connecting the contact hole 74 that interlayer dielectric 53 and gate insulating film 52 are provided with.

The planar configuration of above-mentioned the 3rd layer inscape as shown in figure 13.The 2nd power line 12 and detection line 14 extend along the column direction of image element circuit 40 (Figure 11), and the 2nd power line 12 is configured in the left end side of image element circuit 40 in Figure 13, and detection line 14 is configured in the right-hand member side of image element circuit 40 in Figure 13.Thus, in image element circuit 40, amplifier transistor 45 and reset transistor 41 are configured under the situation of overlooking between the 2nd power line 12 and the detection line 14.In other words, the connecting portion of the connecting portion of the 2nd power line 12 and reset transistor 41 and detection line 14 and amplifier transistor 45 is in the zone than the outer edge of the more close image element circuit 40 of channel region 41c, 45c (Figure 11).According to such structure, can be the wiring of extending, promptly the 2nd power line 12 and detection line 14 are configured to linearity at the longitudinal direction (column direction) of Figure 11.Therefore, can prevent the signal delay that causes because of the complexity that connects up.

Repeater electrode 61 is configured among the drain region 41d (Figure 11) of reset transistor 41 and contact hole 72 overlapping areas at least.Repeater electrode 62,65 is configured among the source region 45s of amplifier transistor 45 and contact hole 74 overlapping areas at least.Here, in image element circuit 40 of certain row, dispose repeater electrode 62, and with the image element circuit 40 of these image element circuit 40 adjacent lines in dispose repeater electrode 65.That is, repeater electrode 62,65 is disposed by interlacing.More specifically be, in image element circuit 40, form repeater electrode 62, in image element circuit 40, form repeater electrode 65 with the 1st power line 11b (Figure 11) with the 1st power line 11a (Figure 11).Repeater electrode 65 extends to the configuring area of contact hole 78 (Figure 14) in the configuring area of the 1st power line 11b.

Return Figure 19, on the 3rd layer,, form the 4th layer that includes scan line 10 grades across the interlayer dielectric 54 that constitutes by silica etc.On the 4th layer, except scan line 10, also be formed with the 1st power line 11b (Figure 14, Figure 20).Scan line 10 is electrically connected with the gate electrode 41g of reset transistor 41 by connecting the contact hole 75 that interlayer dielectric 54,53 is provided with.The 1st power line 11b is by connecting the contact hole 78 that interlayer dielectric 54,53 is provided with, and (Figure 20) is electrically connected with repeater electrode 65.Here, owing to repeater electrode 65 is connected with the source region 45s of amplifier transistor 45, so the 1st power line 11b is electrically connected with this source region 45s.As described later, in the present embodiment, be respectively formed in the different layers as 2 kind of the 1st power line 11a, 11b of the 1st power line.The 3rd layer the 1st power line 11b is a side wherein.

The planar configuration of above-mentioned the 4th layer inscape as shown in figure 14.Scan line 10 is configured to at least a portion of the gate electrode 41g of reset transistor 41 overlapping under the situation of overlooking.In the present embodiment, further be configured to state across the channel region 41c of the channel region 45c of amplifier transistor 45 and reset transistor 41, and linearly.In addition, scan line 10 orientation that is configured to relative channel region 41c, 45c has certain angle.In the present embodiment, this certain angle is 45 degree.In addition, as described above, the gate electrode 41g of scan line 10 and reset transistor 41 is electrically connected by the contact hole 75 that forms in the normal direction of substrate 5 on gate electrode 41g.Like this, scan line 10 be configured to the 2nd layer and non-the 3rd layer of different layer in and by 2 transistorized above, and the normal direction at substrate 5 is connected with gate electrode 41g, therefore, do not need to be provided in addition the zone of the wiring of scan line 10, do not need to be used for the zone of scan line 10 and the connecting wiring of reset transistor 41 yet.Therefore, can dispose amplifier transistor 45 and reset transistor 41 to high-density.In this manual, what is called is in the connection of the normal direction of substrate 5, for example be meant that under the situation of the connection that utilizes contact hole, the formation direction of contact hole has the composition of the normal direction of substrate 5, be not limited to the situation that contact hole accurately forms along the normal direction of substrate 5.

The 1st power line 11b is parallel to scan line 10 and is configured to linearity, promptly is configured to linearity along line direction.The 1st power line 11b is disposed by interlacing.

Return Figure 19, on the 4th layer, the interlayer dielectric 55 across being made of silica etc. is formed with the 5th layer that comprises the 1st power line 11a, repeater electrode 63,64 (Figure 20).The 1st power line 11a is 2 kind of the 1st the opposing party in the power line 11.The 1st power line 11a is electrically connected with repeater electrode 62 by connecting the contact hole 77 that interlayer dielectric 55,54 is provided with.Here, owing to repeater electrode 62 is connected with the source region 45s of amplifier transistor 45, so the 1st power line 11a is electrically connected with this source region 45s.Repeater electrode 63 is connected with repeater electrode 61 by the contact hole 76 that perforation interlayer dielectric 55,54 is provided with.Repeater electrode 64 is connected with repeater electrode 65 by the contact hole 77 that perforation interlayer dielectric 55,54 is provided with.

The planar configuration of above-mentioned the 5th layer inscape as shown in figure 15.The 1st power line 11a is configured along the line direction of image element circuit 40, and is configured to the configuring area that its part is projected into contact hole 74,77.Repeater electrode 63 is configured among the drain region 41d of reset transistor 41 and contact hole 72,76 overlapping areas at least.Repeater electrode 64 is configured among the source region 45s of amplifier transistor 45 and contact hole 74,77 overlapping areas at least.64 of repeater electrodes are configured in the image element circuit 40 with the 1st power line 11b.

Here, in conjunction with Figure 17, the configuration of the 1st power line 11a, 11b is described.Figure 17 is the vertical view that extraction the 1st power line 11a, 11b, semiconductor layer 41a, 45a etc. represent from Figure 11.The 1st power line 11a, 11b are extended by linearity and are arranged on the direction parallel with scan line 10.More specifically be, the 1st power line 11a is formed on the upper end side of image element circuit 40 in Figure 17, and the 1st power line 11b is formed on the lower end side of image element circuit 40.And, be formed with the row of image element circuit 40 of the 1st power line 11a and the row of image element circuit 40 that is formed with the 1st power line 11b by alternate configurations.Therefore, the 1st power line 11a and the 1st power line 11b are configured in approaching position mutually under the situation of overlooking.

In addition, as mentioned above, the 1st power line 11a is formed on the 5th layer (Figure 19), and the 1st power line 11b is formed on the 4th layer (Figure 20) different with it.Therefore, and the 1st power line 11a, 11b are formed on the situation of one deck and compare, can be configured in position more approaching under the situation of overlooking to the 1st power line 11a, 11b.Therefore, can dwindle the configuration space of the image element circuit 40 of longitudinal direction (column direction) at Figure 17.

In addition, as shown in figure 18, it is overlapped also can be configured under the situation of overlooking its part to the 1st power line 11a, 11b.Like this, can further dwindle the configuration space of image element circuit 40 on column direction.

Return Figure 19, on the 5th layer, form the planarization film 56 that constitutes by allyl resin etc., lamination the 1st capacity cell 43 and as the photodiode 47 of detecting element in order on planarization film 56.The 1st capacity cell 43 and photodiode 47 are formed in each image element circuit 40.

The structure of the dielectric film 43d that the 1st capacity cell 43 had from lower layer side order lamination the 2nd electrode 43b that is made of Al-Nd etc., be made of silicon nitride etc., the 1st electrode 43a that constitutes by Al-Nd etc.The 2nd electrode 43b is electrically connected with the 1st power line 11b or repeater electrode 64 (Figure 20) by being formed on the contact hole 79b in the planarization film 56.Therefore, the 2nd electrode 43b is electrically connected with the source region 45s of amplifier transistor 45 by repeater electrode 62 or repeater electrode 65.Contact hole 79b under the situation of overlooking, be formed on the 2nd electrode 43b overlapping areas in.In addition, the 1st electrode 43a is electrically connected with repeater electrode 63 by being formed on the contact hole 79a in the planarization film 56.Therefore, the 1st electrode 43a is electrically connected with the drain region 41d of reset transistor 41 and the gate electrode 45g of amplifier transistor 45 by repeater electrode 61.Contact hole 79a under the situation of overlooking, be formed on the 1st electrode 43a overlapping areas in.Like this, according to the contact hole 79a of the normal direction by being located at substrate 5, the structure that 79b is electrically connected, can connect effectively, and can enlarge the line number/space that is located at the wiring of one deck.In addition, the 1st electrode 43a is under the situation of overlooking, and its part is overlapping with semiconductor layer 41a, and the 2nd electrode 43b is under the situation of overlooking, and its part is overlapping with semiconductor layer 45a.Based on such feature, also can obtain to enlarge the effect that is located at the line number/space of the wiring of one deck.

And,, carry out (shared contact structure) by same contact hole 72 for being connected of the drain region 41d of the 1st electrode 43a and reset transistor 41 and being connected of the drain region 41d of the gate electrode 45g of amplifier transistor 45 and reset transistor 41.According to such structure, can reduce the employed zone of contact hole under the situation of overlooking, thereby can dispose image element circuit 40 to high-density.

The planar configuration of the 1st electrode 43a, the 2nd electrode 43b as shown in figure 16.The 2nd electrode 43b is formed on the zone except the drain region 41d of reset transistor 41 in the image element circuit 40, and the 1st electrode 43a is formed on roughly all faces of image element circuit 40.Therefore, the channel region 45c of amplifier transistor 45 and the channel region 41c of reset transistor 41 under the situation of overlooking, are covered by at least one side of the 1st electrode 43a and the 2nd electrode 43b.According to such structure, owing to can utilize 1 or 2 light shield layers (the 1st electrode 43a, the 2nd electrode 43b) to block channel region 45c, 41c (Figure 11), so can reduce the cut-off current of amplifier transistor 45 and reset transistor 41.Thus, can improve the S/N ratio of detection signal Xn.

Return Figure 19, the 1st electrode 43a of the 1st capacity cell 43 is done the negative electrode of photodiode 47 by dual-purpose.The structure of the n layer 47n that photodiode 47 had from lower layer side order lamination the 1st electrode 43a as negative electrode, be made of amorphous silicon, i layer 47i, p layer 47p and the transparent anode 48 that constitutes by ITO (IndiumTin Oxide).Photodiode 47 as shown in figure 16, is formed near the rectangular area, image element circuit 40 centers under the situation of overlooking.Around the rectangular area of photodiode 47, be formed with the dielectric film 57 that constitutes by silicon nitride etc.Like this,, form the structure of photodiode overlappingly, can enlarge the occupied area of the 1st capacity cell 43, photodiode 47 respectively with the 1st capacity cell 43 according to the negative electrode of the 1st electrode 43a dual-purpose of the 1st capacity cell 43 being made photodiode 47.

(variation 1-1)

The checkout gear 1 of present embodiment is to use photodiode 47 as detecting element, but in addition, can also use other various detecting elements.Figure 21 is the profile that has used the checkout gear 1 of the 2nd capacity cell 44 as detecting element, and the position of the B-B line among the position of section and Figure 11 is corresponding.The 2nd capacity cell 44 and the 1st capacity cell 43 overlap to form, and have had from following stacked beginning layer the structure of the 1st electrode 43a, insulating barrier 44d, the 2nd electrode 44b.Here, the 1st electrode 43a is the electrode shared with the 1st capacity cell 43.On the 2nd capacity cell 44, dispose the substrate 6 that constitutes by glass or transparent resin etc.When substrate 6 deformed owing to extraneous factor, the varied in thickness of insulating barrier 44d made the capacity of the 2nd capacity cell 44 change thus.Its result is accumulated in the quantity of electric charge change in the 2nd capacity cell 44, and the grid potential of amplifier transistor 45 is changed.Therefore, by the checkout gear 1 of the 2nd capacity cell 44, also can detect extraneous factor as the detecting element use.

(variation 1-2)

The checkout gear 1 of present embodiment has 2 power lines (the 1st power line the 11, the 2nd power line 12) in each image element circuit 40, make it shared but also can adopt, in each image element circuit 40, have the structure of single power supply line by these power lines are electrically connected.Figure 22 is the circuit diagram of checkout gear 1 with image element circuit 40 of such formation.In each image element circuit 40, a side's of the 1st capacity cell 43 terminal is electrically connected with the 2nd power line 12 (also abbreviating power line 12 in this variation as).And an end of reset transistor 41 and amplifier transistor 45 (source electrode or drain electrode) all is electrically connected with power line 12.Like this, can be to an end of the terminal of the 1st capacity cell 43 and reset transistor 41, amplifier transistor 45 by power line 12 supply line voltage RSL.Here, supply voltage RSL becomes the side among the 1st power supply potential VDD or the 2nd power supply potential VSS.

According to such structure, also can carry out and above-mentioned execution mode similar detection action.That is, at first, at reseting period Trest, reset transistor 41 becomes conducting state, and the 2nd supply voltage VSS is fed into the grid of amplifier transistor 45 by power line 12.And detection line 14 is precharged to the 2nd power supply potential VSS.Then, Tini during initialization becomes in the row of high level at sweep signal Y1～Ym, and the 1st power supply potential VDD is provided for the grid of amplifier transistor 45 by power line 12 and reset transistor 41.At this moment, the other end of the 1st capacity cell 43 also is supplied to the 1st power supply potential VDD by power line 12.Then, Tdet between detection period is from the image element circuit 40 output detection signal X1～X3 of selected row.At this moment, the detection signal X1～X3 of the corresponding size of amplifier transistor 45 outputs with grid potential.Here, the grid potential of amplifier transistor 45 changes to photodiode 47 quantity of incident light owing to corresponding, so detection signal X1～X3 becomes the size corresponding with this incident light quantity.

Figure 23 is the vertical view in the zone that comprises a plurality of image element circuits 40 of the checkout gear 1 of this variation.In addition, Figure 24 is the vertical view of the configuration of the 1st layer (having formed the layer of semiconductor layer 41a, 45a), the 3rd layer (having formed the layer of power line 12) in the inscape of expression Figure 23.As shown in these figures, power line 12 has longitudinal direction (column direction) configuration along figure, and is used for the 12a of branch portion that source region 41s is connected with source region 45s at each image element circuit 40.The 12a of branch portion is electrically connected with source region 41s and source region 45s by contact hole 71,74.In addition, source region 41s, 45s are electrically connected with the 2nd electrode 43b of the 1st capacity cell 43 by contact hole 77.

The checkout gear 1 of present embodiment does not have the 1st power line 11a, 11b.Therefore, can be omitted in the 5th layer (Figure 15) that comprises in the 1st execution mode, comprise the 1st power line 11a and repeater electrode 63,64.In this case, as long as in comprising the 4th layer of scan line 10, resetting repeater electrode, and the 1st electrode 43a of the 1st capacity cell 43, the 2nd electrode 43b be electrically connected with this repeater electrode respectively get final product with repeater electrode 63,64 corresponding positions.

According to the structure of this variation,,, can simplify the circuit structure of checkout gear 1 so compare with structure with many power lines because each image element circuit (unit circuit) 40 has single power line 12.And, owing to need in different layers, not form many power lines 12, so can simplify the layer structure of image element circuit 40.And, can reduce the configuration area of power line 12, constitute image element circuit 40 with higher precision.

＜the 2 execution mode 〉

Below, the 2nd execution mode of checkout gear is described.The checkout gear of present embodiment is different with the 1st execution mode aspect the configuration of the inscape of image element circuit 40, and other aspects are identical with the 1st execution mode.

Figure 25 is the vertical view in the zone that comprises a plurality of image element circuits 40 of checkout gear 2 of present embodiment, and Figure 26 is the amplification plan view of image element circuit 40.Figure 30 is the profile of the checkout gear 2 of the D-D line in Figure 25.As shown in figure 30, have the 1st layer of comprising semiconductor layer 41a, 45a, comprise gate electrode 41g, 45g the 2nd layer, comprise the 3rd layer of detection line 14 etc., comprise the 4th layer of scan line the 10, the 1st power line 11 etc. and comprise the 5th layer of the 2nd power line 12 etc.Figure 27 is that the vertical view that the inscape of the 1st layer and the 5th layer is represented is extracted in expression out from inscape shown in Figure 25.Figure 28 is the vertical view that the inscape of expression extraction layers 1 and 2 from inscape shown in Figure 25 is represented.Figure 29 is that the vertical view that the inscape of the 1st layer, the 3rd layer and the 4th layer is represented is extracted in expression out from inscape shown in Figure 25.

At first, describe with reference to the profile of Figure 30 structure image element circuit 40.On substrate 5, be formed with the underlying insulation film 51 that constitutes by silica etc.On underlying insulation film 51, be formed with the 1st layer that comprises semiconductor layer 41a, 45a.On the 1st layer, be formed with the gate insulating film 52 that constitutes by silica etc., be formed with the 2nd layer that comprises gate electrode 41g, 45g in the above.

Semiconductor layer 41a for example is made of polysilicon film, has based on the channel region 41c that forms raceway groove from the electric field of gate electrode 41g, as the drain region 41d of the 1st terminal with as the source region 41s of the 2nd terminal.Semiconductor layer 45a also is same, has based on the channel region 45c that forms raceway groove from the electric field of gate electrode 45g, as the drain region 45d of the 1st terminal with as the source region 45s of the 2nd terminal.Semiconductor layer 41a, 45a also can adopt the LDD structure. Gate electrode 41g, 45g are formed on respectively and channel region 41c, 45c overlapping areas under the situation of overlooking at least.

As shown in figure 28, semiconductor layer 41a, 45a are configured to zigzag in the mode that staggers mutually at column direction.And semiconductor layer 41a, 45a are that the silicon fiml that is formed continuously by the boundary line of 2 image element circuits 40 crossing over adjacency constitutes, and become the shape of symmetry in the longitudinal direction.That is, 1 semiconductor layer 41a becomes the structure that drain region 41d, channel region 41c, source region 41s, channel region 41c, drain region 41d are formed a line.Source region 41s wherein by shared, and is electrically connected with the 2nd power line 12 in 2 adjacent image element circuits 40.Equally, 1 semiconductor layer 45a becomes the structure that drain region 45d, channel region 45c, source region 45s, channel region 45c, drain region 45d are formed a line.Source region 45s wherein by shared, and is electrically connected with the 1st power line 11 in 2 adjacent image element circuits 40.In above-mentioned, channel region 41c, 45c be among semiconductor layer 41a, the 45a with gate electrode 41g, 45g overlapping areas.According to such structure, owing to reducing semiconductor layer 41a, 45a the quantity that contacts, so can improve the rate of finished products in the manufacturing process with wiring.

In addition, semiconductor layer 41a and semiconductor layer 45a are configured to be parallel to each other.That is, semiconductor layer 41a is set up along the bearing of trend of semiconductor layer 45a.Therefore, the orientation of channel region 41c becomes along the direction of the direction of the channel length of channel region 45c.Perhaps, the direction of the channel length of channel region 41c also can be parallel with the orientation of channel region 45c.According to such structure, because can be in the zone of minimum, so can dispose amplifier transistor 45 and reset transistor 41 to high-density channel region 41c and channel region 45c centralized configuration.In addition, be to handle through laser annealing and under the situation of the low temperature polycrystalline silicon that forms at semiconductor layer 41a, 45a, having can be based on the advantage of the size Control transistor characteristic of channel region 41c, 45c.And particularly semiconductor layer 41a, 45a are under the situation of low temperature polycrystalline silicon, can make amplifier transistor 45 consistent with the current characteristics of reset transistor 41, for example, can make both conducting electric currents identical with cut-off current.In checkout gear 2, under the situation that certain image element circuit 40 is failure to actuate, must make amplifier transistor 45 and reset transistor 41 all become cut-off state reliably, according to above-mentioned structure, carry out this action easily.

In addition, as shown in figure 28, the channel length of channel region 41c, 45c is configured to: its bearing of trend is vertical with the bearing of trend (line direction) of scan line 10 (Figure 29) under the situation of overlooking.According to such structure, can be overlapping the wiring of column directions such as power line 12, detection line 14 and amplifier transistor 45 and reset transistor 41, thus can dispose these inscapes to high-density.

In addition, in amplifier transistor 45,, under the situation of overlooking, dispose along the direction vertical with the bearing of trend (line direction) of scan line the 10, the 1st power line 11 drain region 45d (the 1st terminal) and source region 45s (the 2nd terminal).Equally, in reset transistor 41, drain region 41d (the 1st terminal) is disposed along the direction vertical with the bearing of trend (line direction) of scan line the 10, the 1st power line 11 under the situation of overlooking with source region 41s (the 2nd terminal).According to such structure, the wiring carrying out extending at line direction during the i.e. configuration of scan line 10 and the 1st power line 11, can be suppressed at the minimal while in handle and amplifier transistor 45 and reset transistor 41 overlapping areas, is configured to linearity.Therefore, can prevent the signal delay that causes because of the complexity that connects up.And, being under the situation of the low temperature polycrystalline silicon of formation, to utilize the laser parallel, can easily carry out annealing in process to semiconductor layer 41a, 45a with the column direction of image element circuit 40 through the laser annealing processing.The electrical characteristics of semiconductor layer 41a, 45a are strong to the interdependence of crystallization direction, and particularly under the situation of laser annealing, according to the direction of laser radiation, this interdependence is more obvious.Therefore, according to the structure of present embodiment, can obtain high semiconductor layer 41a, the 45a of consistent degree of electrical characteristics.

In addition, as shown in figure 28, in each image element circuit 40, the channel region 45c of amplifier transistor 45 and the channel region 41c of reset transistor 41 at column direction by the configuration of staggering mutually.Equally, the contact point of amplifier transistor 45 and reset transistor 41 and various wirings, also at column direction by the configuration of staggering mutually.In other words, under the situation of overlooking, along the angled direction of the bearing of trend of relative scanning line 10, the channel region 45c of configuration amplifier transistor 45 and the channel region 41c of reset transistor 41.According to such structure, the wiring of line direction, promptly scan line 10 and the 1st power line 11, with channel region 41c, 45c and drain region 41d, 45d, source region 41s, when 45s is connected, do not need complicated bending is carried out in the wiring of these line directions, can be configured to linearity.Thus, can prevent the signal delay that causes because of the complexity that connects up.

In addition, gate electrode 45g is extended the drain region 41d position overlapped that is set to reset transistor 41 under the situation of overlooking, and, be electrically connected with drain region 41d by contact hole 82.Thus, can utilize the output control amplifier transistor 45 of reset transistor 41.By making semiconductor layer 41a, 45a become configuration as described above, drain region 41d is positioned at from channel region 45c on the line segment of the short-axis direction extension of semiconductor layer 45a.Therefore, gate electrode 45g, can easily be formed on the 41d of drain region only to the unidirectional extension of the short-axis direction of semiconductor layer 45a by to be initial point on the channel region 45c.And, can guarantee that the contact site among the 41d of drain region is bigger.And gate electrode 45g is configured to linearity by the bearing of trend along scan line 10.Thus, the wiring for beyond the gate electrode 45g also is being configured to linearity easily on the direction of scan line 10.Thus, can prevent the signal delay that causes because of the complexity that connects up.

Return Figure 30, on the 2nd layer, the interlayer dielectric 53 across being made of silica etc. is formed with the 3rd layer that comprises detection line 14 grades.In addition, on the 3rd layer, also be formed with repeater electrode 66,67.Detection line 14 is electrically connected with the drain region 45d of amplifier transistor 45 by connecting the contact hole 83 that interlayer dielectric 53 and gate insulating film 52 are provided with.Repeater electrode 66,67 is electrically connected with the drain region 41d and the source region 41s of reset transistor 41 respectively by connecting the contact hole 82,81 that interlayer dielectric 53 and gate insulating film 52 are provided with.

The planar configuration of above-mentioned the 3rd layer inscape as shown in figure 29.Detection line 14 is configured to parallel with the longitudinal direction (column direction) of figure, and its part bends to the bending of " ㄑ " font, with the contact hole 84 of avoiding the 1st power line 11.Repeater electrode 66 be configured at least among the drain region 41d of reset transistor 41 with contact hole 82 overlapping areas.Repeater electrode 67 be configured at least among the source region 41s of reset transistor 41 with contact hole 81 overlapping areas.

Return Figure 30, on the 3rd layer,, be formed with the 4th layer that comprises scan line the 10, the 1st power line 11 etc. across the interlayer dielectric 54 that constitutes by silica etc.Scan line 10 is electrically connected with the gate electrode 41g of reset transistor 41 by connecting the contact hole 85 that interlayer dielectric 54,53 is provided with.The 1st power line 11 is electrically connected with the source region 45s of amplifier transistor 45 by connecting the contact hole 84 that interlayer dielectric 54,53 and gate insulating film 52 are provided with.

The planar configuration of above-mentioned the 4th layer inscape as shown in figure 29.Scan line 10 extends along the longitudinal direction (line direction) of figure and is provided with, and is configured to at least a portion of the gate electrode 41g of reset transistor 41 overlapping under the situation of overlooking.In addition, as described above, the gate electrode 41g of scan line 10 and reset transistor 41 is electrically connected by the contact hole 85 that forms in the normal direction of substrate 5 on gate electrode 41g.Like this, scan line 10 be configured in the 2nd layer and non-the 3rd layer layer by 2 transistorized above, and the normal direction at substrate 5 is connected with gate electrode 41g, therefore, do not need to be provided in addition the zone of the wiring of scan line 10, do not need to be used for the zone of scan line 10 and the connecting wiring of reset transistor 41 yet.Therefore, can dispose amplifier transistor 45 and reset transistor 41 to high-density.

The 1st power line 11 is extended by the transverse direction (line direction) along figure and is provided with, and is configured under the situation of overlooking with at least a portion of the source region 45s of amplifier transistor 45 overlapping.Here, the 1st power line 11 is formed on the position that is sandwiched in the row of image element circuit 40 between the 2 adjacent row, and 2 adjacent relatively row form 1.And each the 1st power line is to the capable supply power of 2 adjacent image element circuits 40.That is, the 1st power line 11 is shared by the row of 2 adjacent image element circuits 40 institute.And, constitute the bearing of trend line symmetry of relative the 1st power line 11 across the inscape of 2 adjacent image element circuits 40 of the 1st power line 11.According to such structure,, can improve the configuration density of image element circuit 40 to the restricted number of the 1st power line 11 by being Min..That is, compare with the structure that between the adjacent row of image element circuit 40, forms 2 article of the 1st power line 11, owing to do not need to be provided with the configuring area of the 1st power line 11 and the space between 2 article of the 1st power line, so, can dwindle the configuration space of image element circuit 40.In addition, dispose the inscape of image element circuit 40 symmetrically, can reduce the property difference of image element circuit 40 by line.

Return Figure 30, on the 4th layer,, form the 5th layer that includes the 2nd power line 12, repeater electrode 63,64 across the interlayer dielectric 55 that constitutes by silica etc.The 2nd power line 12 is electrically connected with repeater electrode 67 by connecting the contact hole 86 that interlayer dielectric 55,54 is provided with.Here, owing to repeater electrode 67 is connected with the source region 41s of reset transistor 41, so the 2nd power line 12 is electrically connected with this source region 41s.Repeater electrode 63 is connected with repeater electrode 66 by the contact hole 87 that perforation interlayer dielectric 55,54 is provided with.Repeater electrode 64 is electrically connected with the 1st power line 11 by the contact hole 88 that perforation interlayer dielectric 55 is provided with, and further, is electrically connected with the source region 45s of amplifier transistor 45.

The contact site of repeater electrode 64 and the 1st power line 11, i.e. the formation position of contact hole 88, under the situation of overlooking, its part is overlapping with detection line 14.Like this, according to the structure of present embodiment, can effectively utilize the top area of detection line 14.Thus, but high density forms image element circuit 40.

The planar configuration of above-mentioned the 5th layer inscape as shown in figure 27.The 2nd power line 12 have longitudinal direction (column direction) along figure extend configuration, be used for the branch portion that is connected with the source region 41s of reset transistor 41.As mentioned above, the source region 41s of reset transistor 41 since in 2 adjacent image element circuits 40 by shared, so, utilize 1 contact site leading to source region 41s, can be to 2 reset transistor 41 supply powers.

Here, as shown in figure 25, the 2nd power line 12 and detection line 14 all are the wirings of extending along column direction, and the 2nd power line 12 is formed on the 5th layer, and detection line 14 is formed on the 3rd layer, promptly are respectively formed in the different layers.Therefore, the 2nd power line 12 and detection line 14 can be configured to have at least a part overlapping under the situation of overlooking.In the present embodiment, the 2nd power line 12 is overlapped with detection line 14.According to such structure, because can be 2 cloth line overlaps, so can dwindle the configuration space of image element circuit 40 at line direction, but high density forms image element circuit 40.

Return Figure 30, on the 5th layer, form the planarization film 56 that constitutes by allyl resin etc., lamination the 1st capacity cell 43 and as the photodiode 47 of detecting element in order on planarization film 56.The 1st capacity cell 43 and photodiode 47 are formed in each image element circuit 40.

The 1st capacity cell 43 has from the structure of lower layer side begun the order lamination the 2nd electrode 43b that is made of Al-Nd etc., the dielectric film 43d that is made of silicon nitride etc., the 1st electrode 43a that is made of Al-Nd etc.The 2nd electrode 43b is electrically connected with repeater electrode 64 by being formed on the contact hole 79b in the planarization film 56.Therefore, the 2nd electrode 43b is electrically connected with the source region 45s of amplifier transistor 45 by repeater electrode the 64, the 1st power line 11.Contact hole 79b under the situation of overlooking, be formed on the 2nd electrode 43b overlapping areas in.In addition, the 1st electrode 43a is electrically connected with repeater electrode 63 by being formed on the contact hole 79a in the planarization film 56.Therefore, the 1st electrode 43a is electrically connected with the drain region 41d of reset transistor 41 and the gate electrode 45g of amplifier transistor 45 by repeater electrode 63,66.Contact hole 79a under the situation of overlooking, be formed on the 1st electrode 43a overlapping areas in.Like this, according to the contact hole 79a of the normal direction by being located at substrate 5, the structure that 79b is electrically connected, can connect reliably, and can enlarge the line number/space that is located at the wiring of one deck.In addition, the 1st electrode 43a is under the situation of overlooking, and its part is overlapping with semiconductor layer 41a, and the 2nd electrode 43b is under the situation of overlooking, and its part is overlapping with semiconductor layer 45a.Based on such feature, also can obtain to enlarge the effect that is located at the line number/space of the wiring of one deck.

And,, carry out (shared contact structure) by same contact hole 82 for being connected of the drain region 41d of the 1st electrode 43a and reset transistor 41 and being connected of the drain region 41d of the gate electrode 45g of amplifier transistor 45 and reset transistor 41.According to such structure, can reduce the employed zone of contact hole under the situation of overlooking, thereby can dispose image element circuit 40 to high-density.

The 2nd electrode 43b be formed in the image element circuit 40 except the drain region 41d of reset transistor 41 and neighbouring the zone, the 1st electrode 43a is formed on roughly whole of image element circuit 40.Therefore, the channel region 45c of amplifier transistor 45 and the channel region 41c of reset transistor 41 under the situation of overlooking, are covered by at least one side of the 1st electrode 43a and the 2nd electrode 43b.According to such structure, owing to can utilize 1 or 2 light shield layers (the 1st electrode 43a, the 2nd electrode 43b) to block channel region 45c, 41c, so can reduce the cut-off current of amplifier transistor 45 and reset transistor 41.Thus, can improve the S/N ratio of detection signal Xn.

The 1st electrode 43a of the 1st capacity cell 43 is done the negative electrode of photodiode 47 by dual-purpose.Photodiode 47 has the structure of the transparent anode 48 that constitutes from lower layer side begun the order lamination n layer 47n that constitutes as the 1st electrode 43a of negative electrode, by amorphous silicon, i layer 47i, p layer 47p with by ITO.Around photodiode 47, be formed with the dielectric film 57 that constitutes by silicon nitride etc.Like this,, overlap to form the structure of photodiode 47, can enlarge the occupied area of the 1st capacity cell 43, photodiode 47 respectively with the 1st capacity cell 43 according to the negative electrode of the 1st electrode 43a dual-purpose of the 1st capacity cell 43 being made photodiode 47.

(variation 2-1)

The checkout gear 2 of present embodiment is to use photodiode 47 as detecting element, but in addition, can also use other various detecting elements.Figure 31 is the profile that has used the checkout gear 2 of the 2nd capacity cell 44 as detecting element, and the position of the D-D line among the position of section and Figure 25 is corresponding.The 2nd capacity cell 44 and the 1st capacity cell 43 overlap to form, and have the structure of the 1st electrode 43a, insulating barrier 44d, the 2nd electrode 44b that begun lamination from lower floor.Here, the 1st electrode 43a is the electrode shared with the 1st capacity cell 43.On the 2nd capacity cell 44, dispose the substrate 6 that constitutes by glass or transparent resin etc.When substrate 6 deformed owing to extraneous factor, the thickness of insulating barrier 44d changed, and the capacity of the 2nd capacity cell 44 is changed.Its result is accumulated in the quantity of electric charge change in the 2nd capacity cell 44, and the grid potential of amplifier transistor 45 is changed.Therefore, as the checkout gear 2 that detecting element uses, also can detect extraneous factor to the 2nd capacity cell 44.

(variation 2-2)

The checkout gear 2 of present embodiment has 2 power lines (the 1st power line the 11, the 2nd power line 12) in each image element circuit 40, but also can adopt by these power lines are electrically connected sharedly, in each image element circuit 40, have the structure of single power supply line 12.Have the circuit diagram of checkout gear 2 of the image element circuit 40 of such formation, identical with above-mentioned variation 1-2 shown in Figure 22.According to such structure, also can carry out the detection action identical with above-mentioned execution mode.

Figure 32 is the vertical view in the zone that comprises a plurality of image element circuits 40 of the checkout gear 2 of this variation.In addition, Figure 33 is the vertical view of the configuration of the 1st layer (having formed the layer of semiconductor layer 41a, 45a), the 5th layer (having formed the layer of power line 12) in the inscape of expression Figure 32.As shown in these figures, power line 12 is by along the configuration of the longitudinal direction (column direction) of figure, and is electrically connected with contact hole 81,84,86,88 to the branch portion of the direction extension that intersects with column direction.More specifically be that power line 12 is electrically connected with source region 41s by contact hole 81,86, in addition, is electrically connected with source region 45s by contact hole 89.And power line 12 is electrically connected with the 2nd electrode 43b of the 1st capacity cell 43 in the position of contact hole 79b.

The checkout gear 2 of this variation 2 does not have the 1st power line 11.Therefore, among the 4th layer (Figure 29) that in the 2nd execution mode, is comprised, comprise the 1st power line 11 and scan line 10, can omit the 1st power line 11.

According to the structure of this variation,,, can simplify the circuit structure of checkout gear 2 so compare with structure with a plurality of power lines because each image element circuit (unit circuit) 40 has single power line.And, owing to need in different layers, not form many power lines 12, so can simplify the structure of image element circuit 40.And, can reduce the configuration area of power line 12, more high density constitutes image element circuit 40.

＜electronic equipment 〉

Above-mentioned checkout gear 1 (comprises checkout gear 2.Below same.) for example can carry in the mobile phone 500 as electronic equipment as shown in figure 34 and be used.Mobile phone 500 has display part 510 and operation keys 520.Display part 510 can show the various information that are representative by the content of operation keys 520 inputs and incoming information.In addition, in the inside of display part 510 checkout gear 1 is installed.When contact pen or finger etc. during near checkout gear 1, detect the variation of incident light quantity by checkout gear 1, this positional information is input in the electronic equipment.Like this, mobile phone 500 has the user interface that has used checkout gear 1.

In addition, checkout gear 1 can also use in various electronic equipments such as portable computer, digital camera, Digital Video, mobile unit, stereo set except using above-mentioned mobile phone 500.In addition, checkout gear 1 can be applicable in the image read-outs such as scanner and camera head.

Claims (20)

1. a checkout gear has: substrate; Be configured in the multi-strip scanning line on the aforesaid substrate, many detection lines, many articles the 1st power lines, many articles the 2nd power lines; And a plurality of unit circuits that are provided with corresponding to the crosspoint of above-mentioned scan line and above-mentioned detection line, it is characterized in that,

Above-mentioned unit circuit has:

The 1st transistor, its 1st terminal is connected with above-mentioned detection line, and the 2nd terminal is connected with above-mentioned the 1st power line, and supplies with the detection signal corresponding with the current potential of gate electrode to above-mentioned detection line;

Detecting element, it is connected with the above-mentioned the 1st transistorized gate electrode, and the above-mentioned the 1st transistorized grid potential is changed according to extraneous factor;

The 2nd transistor, its 1st terminal is connected with the above-mentioned the 1st transistorized gate electrode, and the 2nd terminal is connected with above-mentioned the 2nd power line, and gate electrode is connected with above-mentioned scan line; And

The 1st capacity cell, it keeps the above-mentioned the 1st transistorized grid potential,

Above-mentioned scan line is formed in the layer different with the above-mentioned the 2nd transistorized gate electrode with the above-mentioned the 1st transistorized gate electrode, and is configured under the situation of overlooking overlapping with at least a portion of above-mentioned the 2nd transistorized gate electrode.

2. checkout gear according to claim 1 is characterized in that,

Above-mentioned scan line and the above-mentioned the 2nd transistorized gate electrode are on the above-mentioned the 2nd transistorized gate electrode, by being electrically connected at the formed contact hole of the normal direction of aforesaid substrate.

3. checkout gear according to claim 1 is characterized in that,

The above-mentioned the 1st transistorized channel region has certain angle with the bearing of trend that the above-mentioned the 2nd transistorized channel region is configured to relative above-mentioned scan line,

Above-mentioned scan line is configured under the situation of overlooking across the above-mentioned the 1st transistorized channel region and the above-mentioned the 2nd transistorized channel region.

4. checkout gear according to claim 1 is characterized in that,

Above-mentioned detection line is formed in the different layers with above-mentioned the 2nd power line,

Above-mentioned detection line is configured under the situation of overlooking to extend along the bearing of trend of above-mentioned the 2nd power line, and its at least a portion and above-mentioned the 2nd power line are overlapping.

5. checkout gear according to claim 1 is characterized in that,

Along 2 above-mentioned the 1st power lines of adjacent above line configuration, be formed in the different mutually layers in the row of above-mentioned unit circuit.

6. checkout gear according to claim 1 is characterized in that,

The direction of above-mentioned the 1st its channel length of transistor is the direction of extending along the above-mentioned the 2nd transistorized orientation.

7. checkout gear according to claim 6 is characterized in that,

Above-mentioned the 1st transistor and above-mentioned the 2nd transistor are configured to its orientation and intersect with the bearing of trend of above-mentioned scan line and the bearing of trend of above-mentioned detection line under the situation of overlooking.

8. checkout gear according to claim 6 is characterized in that,

Bearing of trend along above-mentioned scan line under the situation of overlooking disposes the above-mentioned the 1st transistorized the 1st terminal and the above-mentioned the 2nd transistorized the 1st terminal, and the bearing of trend along above-mentioned scan line under the situation of overlooking disposes the above-mentioned the 1st transistorized the 2nd terminal and the above-mentioned the 2nd transistorized the 2nd terminal.

9. checkout gear according to claim 6 is characterized in that,

Above-mentioned the 1st transistor is vertical with above-mentioned its orientation of the 2nd transistor bearing of trend with above-mentioned scan line under the situation of overlooking.

10. checkout gear according to claim 1 is characterized in that,

Above-mentioned the 1st capacity cell has the 1st electrode and the 2nd electrode,

The above-mentioned the 1st transistorized channel region and the above-mentioned the 2nd transistorized channel region are covered by at least one side in above-mentioned the 1st electrode and above-mentioned the 2nd electrode under the situation of overlooking.

11. checkout gear according to claim 10 is characterized in that,

Above-mentioned the 1st electrode is also used as the electrode of above-mentioned detecting element.

12. a checkout gear has: substrate; Be configured in the multi-strip scanning line on the aforesaid substrate, many detection lines, many articles the 1st power lines, many articles the 2nd power lines; And a plurality of unit circuits that are provided with corresponding to the crosspoint of above-mentioned scan line and above-mentioned detection line, it is characterized in that,

Above-mentioned unit circuit has:

The 1st transistor, its 1st terminal is connected with above-mentioned detection line, and the 2nd terminal is connected with above-mentioned the 1st power line, and supplies with the detection signal corresponding with the current potential of gate electrode to above-mentioned detection line;

Detecting element, it is connected with the above-mentioned the 1st transistorized gate electrode, and the above-mentioned the 1st transistorized grid potential is changed according to extraneous factor;

The 2nd transistor, its 1st terminal is connected with the above-mentioned the 1st transistorized gate electrode, and the 2nd terminal is connected with above-mentioned the 2nd power line, and gate electrode is connected with above-mentioned scan line; And

The 1st capacity cell, it keeps the above-mentioned the 1st transistorized grid potential,

In the row of above-mentioned unit circuit,, be formed with above-mentioned the 1st power line by 2 adjacent positions that above line clipped, and 1 above-mentioned the 1st power line of every 2 adjacent above lines formation,

Above-mentioned the 1st power line is to the unit circuit supply power of 2 adjacent above lines.

13. checkout gear according to claim 12 is characterized in that,

The inscape that clips 2 adjacent above-mentioned unit circuits of above-mentioned the 1st power line constitutes, and the bearing of trend of above-mentioned relatively the 1st power line is the line symmetry.

14. checkout gear according to claim 12 is characterized in that,

Clip a pair of above-mentioned transistorized channel region in 2 adjacent above-mentioned unit circuits of above-mentioned the 1st power line, use the silicon fiml that fuses to constitute.

15. checkout gear according to claim 12 is characterized in that,

The above-mentioned the 2nd transistorized channel region, the silicon fiml that the boundary line of 2 above-mentioned unit circuits that the use leap is adjacent fuses constitutes,

A pair of above-mentioned the 2nd transistor that is formed in above-mentioned adjacent 2 unit circuits has the 2nd shared terminal, and above-mentioned the 2nd shared terminal is electrically connected with above-mentioned the 2nd power line.

16. a checkout gear has: substrate; Be configured in the multi-strip scanning line on the aforesaid substrate, many detection lines, many power lines; And a plurality of unit circuits that are provided with corresponding to the crosspoint of above-mentioned scan line and above-mentioned detection line, it is characterized in that,

Above-mentioned unit circuit has:

The 1st transistor, its 1st terminal is connected with above-mentioned detection line, and the 2nd terminal is connected with said power, and supplies with the detection signal corresponding with the current potential of gate electrode to above-mentioned detection line;

Detecting element, it is connected with the above-mentioned the 1st transistorized gate electrode, and the above-mentioned the 1st transistorized grid potential is changed according to extraneous factor;

The 2nd transistor, its 1st terminal is connected with the above-mentioned the 1st transistorized gate electrode, and the 2nd terminal is connected with said power, and gate electrode is connected with above-mentioned scan line; And

The 1st capacity cell, it keeps the above-mentioned the 1st transistorized grid potential,

Above-mentioned scan line is formed in the layer different with the above-mentioned the 2nd transistorized gate electrode with the above-mentioned the 1st transistorized gate electrode, and is overlapping with at least a portion of above-mentioned the 2nd transistorized gate electrode under the situation of overlooking.

17. checkout gear according to claim 16 is characterized in that,

Above-mentioned detection line is formed in the different layers with said power,

Above-mentioned detection line is configured under the situation of overlooking to extend to the bearing of trend of said power, and at least a portion and said power are overlapping.

18. checkout gear according to claim 16 is characterized in that,

Above-mentioned its orientation of the 1st transistor is the direction along above-mentioned the 2nd transistorized orientation.

19. checkout gear according to claim 16 is characterized in that,

Above-mentioned the 1st capacity cell has the 1st electrode and the 2nd electrode,

The above-mentioned the 1st transistorized channel region and the above-mentioned the 2nd transistorized channel region are covered by at least one side in above-mentioned the 1st electrode and above-mentioned the 2nd electrode under the situation of overlooking.

20. an electronic equipment is characterized in that, has possessed any described checkout gear in the claim 1 to 19.

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