CN101330063A - Active element array structure and manufacturing method thereof - Google Patents
Active element array structure and manufacturing method thereof Download PDFInfo
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- CN101330063A CN101330063A CNA200810144382XA CN200810144382A CN101330063A CN 101330063 A CN101330063 A CN 101330063A CN A200810144382X A CNA200810144382X A CN A200810144382XA CN 200810144382 A CN200810144382 A CN 200810144382A CN 101330063 A CN101330063 A CN 101330063A
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Abstract
The invention discloses an active element array structure and a manufacturing method thereof. The manufacturing method comprises the following steps: a first patterned conductor layer, a patterned semiconductor layer, a second patterned conductor, a patterned gate insulated layer and a patterned protective layer are formed by using a first photomask process, a second photomask process and a third photomask process, wherein, the patterned gate insulated layer is provided with a first opening, and the patterned protective layer is provided with a second opening and a third opening. The first opening is provided with a first side, the second opening is provided with a second side, and the third opening is provided with a third side. At last, a transparent conductive layer is deposited on the patterned structures, and the transparent conductive layers on the first opening and the second opening respectively form a section at the place corresponding to the first side and the second side.
Description
Technical field
The present invention relates to active element array structure and manufacture method thereof in a kind of display floater.
Background technology
The display unit of display floater and use display floater becomes the main flow of all kinds of display unit gradually.The display screens of flat-plate type monitor, mobile phone and the digital camera of flat-surface television, PC and the kneetop computer of for example various panel display screen, family expenses etc. are the product of a large amount of use display floaters.Especially, the product of liquid crystal display panel of thin film transistor (TFT LCD) for being widely used at present.
Generally speaking, promote fine ratio of product and reduce manufacturing cost and complexity, be the important goal of desiring to reach in the improvement research of the technology of liquid crystal display panel of thin film transistor.According to present technical development, adopt three road photo-marsk processes can reach the purpose that reduces manufacturing cost and complexity.Generally speaking, in the employed three road photo-marsk process technology, adopt photoresist to divest technology (lift offprocess) usually at present.Yet in the technology of large-area display panels, the large tracts of land photoresist divests the quite complicated difficulty of technology of technology, and divests incomplete situation easily; If photoresist divests imperfectly in the technology, then cause the fine ratio of product of thin-film transistor to descend.
Summary of the invention
Purpose of the present invention can be made active element array structure by three road photo-marsk processes for a kind of active element array structure and manufacture method thereof are provided, and can reduce manufacturing cost and have higher technology yield.
The manufacture method of active element array structure of the present invention comprises: form first conductor layer on substrate, and carry out the first road photo-marsk process to form first patterning conductor layer; On substrate, form gate insulation layer, semiconductor layer and second conductor layer, and carry out the second road photo-marsk process, this second conductor layer is formed second patterning conductor layer so that this semiconductor layer is formed patterned semiconductor layer; Form protective layer; Carry out the 3rd road photo-marsk process, this gate insulation layer is formed the patterned gate insulating barrier, this protective layer is formed the patterning protective layer, wherein the patterned gate insulating barrier has first opening, and this patterning protective layer has second opening and the 3rd opening.First opening has first side, and also formation is less than first angles of 90 degree, and second opening has second side and also forms second angles of spending less than 90, and the 3rd opening has the 3rd side and also forms the 3rd angles of spending greater than 90.Form transparency conducting layer, be positioned on this first opening and this second opening this transparency conducting layer respectively to should first side and the position of this second side have section respectively, this transparency conducting layer that is positioned on the 3rd opening is continuous face to position that should the 3rd side.
Description of drawings
Fig. 1 is the schematic flow sheet of active element array structure technology in the embodiment of the invention;
Fig. 2 a is the schematic flow sheet of the second road photo-marsk process in the technology shown in Figure 1;
Fig. 2 b is the schematic flow sheet of the 3rd road photo-marsk process in the technology shown in Figure 1;
Fig. 3 a is the complete structure schematic diagram of active element array structure of the present invention;
Fig. 3 b is in the cutaway view of structural cutting line A-A ', B-B ', C-C ', D-D ' after step 1003 is finished in the technology shown in Figure 1;
Fig. 3 c is the accompanying drawing that step 1009 is finished deposition on the metacoxal plate 10 in the technology shown in Figure 1;
Fig. 3 d is the accompanying drawing of formed patterning photoresist layer after step 1011-2 finishes in the technology shown in Figure 1;
Fig. 3 e is the accompanying drawing after step 1011-3 finishes in the technology shown in Figure 1;
Fig. 4 a is in the accompanying drawing of the drain electrode part of cutting line D-D ' after step 1011-4 finishes in the technology shown in Figure 1;
Fig. 4 b is in the accompanying drawing of the drain electrode part of cutting line D-D ' after step 1011-5 finishes in the technology shown in Figure 1; And
Fig. 5 completes the back in the cutaway view of cutting line A-A ', B-B ', C-C ', D-D ' for active element array structure.
Description of reference numerals
10 substrates, 51 first openings
100 active element array structures, 512 first sides
102 scan lines, 61 second openings
102 ' scanning connection pad, 612 second sides
104 data wires 71 the 3rd opening
104 ' data connection pads 712 the 3rd side
106 common wire θ
1First angle
107 electric capacity line θ
2Second angle
201 first patterning conductor layer θ
3The 3rd angle
203 patterned semiconductor layer d
1First thickness
205 second patterning conductor layer d
2Second thickness
22 gate insulation layer C channel regions
221 patterned gate insulating barrier D drain electrode
24 protective layer ES etch-stop districts
241 patterning protective layer G grids
30 patterning photoresist layer S source electrodes
40 transparency conducting layers
Embodiment
The invention provides active element array structure and manufacture method thereof in a kind of liquid crystal indicator panel.Active element among the present invention for example can be amorphous silicon film transistor (a-SiThin-Film-Transistor, a-Si TFT), or polycrystalline SiTFT (p-Si TFT), perhaps is other similar semiconductor circuit components.
Fig. 1 is a schematic flow sheet of making active element array structure 100 in the embodiment of the invention, Fig. 3 a is the complete structure schematic diagram of the active element array structure 100 of present embodiment, the active device array of present embodiment is example with the thin film transistor (TFT) array, cutting line A-A ' is corresponding to the scanning connection pad 102 ' part of active element array structure 100, cutting line B-B ' is corresponding to data connection pad 104 ' part, the part that corresponding common wire of cutting line C-C ' (common line) 106 and data wire 104 interlock, and cutting line D-D ' is the drain electrode part of corresponding transistor 108.
Fig. 3 b is that active element array structure 100 was along the cutaway view of cutting line A-A ', B-B ', C-C ', D-D ', please in the lump with reference to figure 1, Fig. 3 a and Fig. 3 b after step 1003 was finished in the flow chart shown in Figure 1.At the beginning, step 1001 deposits first conductor layer (not shown) on substrate 10.Substrate 10 is preferably glass substrate, yet in different embodiment, substrate 10 also can adopt polymeric substrates, for example plastic substrate.And the material of first conductor layer is preferably alloy or other metal alloys of molybdenum (Mo) or aluminium (Al).Then, step 1003 is carried out the technology of the first road photomask, is first patterning conductor layer 201 so that first conductor layer is patterned to.Shown in Fig. 3 a, first patterning conductor layer 201 comprises multi-strip scanning line 102, a plurality of grid G that are connected with scan line 102 and scanning connection pad 102 ', and alternately many common wires 106 parallel, and the electric capacity line 107 that is connected with common wire 106 with scan line 102.Specifically, Fig. 3 b is after step 1003 is finished, and is formed with the accompanying drawing of first patterning conductor layer 201 on the substrate 10.
Please continue with reference to figure 1, Fig. 3 a and Fig. 3 c, Fig. 3 c is depicted as and proceeds to step 1009 and finish on the metacoxal plate 10 in the cutaway view of cutting line A-A ', B-B ', C-C ', D-D '.Please refer to Fig. 1, step 1005 deposits gate insulation layer 22, semiconductor layer (figure does not show) and second conductor layer (figure does not show) in regular turn on substrate 10.Then, step 1007 is carried out the second road photo-marsk process, the semiconductor layer pattern of deposition in the step 1005 is changed into be patterned semiconductor layer 203 second conductor layer to be patterned as second patterning conductor layer 205, afterwards, forms protective layer in step 1009.Shown in Fig. 3 a, patterned semiconductor layer 203 comprises a plurality of channel region C and a plurality of etch-stops district ES, these channel regions C is positioned at these grid G tops, and second patterning conductor layer 205 comprises many data wires 104, a plurality of source S, a plurality of drain D and a plurality of data connection pad 104 '.Data wire 104 intersects with scan line 102 and common wire 106; data wire 104 connects source S and data connection pad 104 '; and source S and drain D are positioned at the top of these grid G and channel region C; etch-stop district ES is positioned at these data wire 104 and these common wire 106 intersections, the common wire 106 of protection below when being used for etching.Detailed speech, the scanning connection pad 102 ' part among Fig. 3 c shown in cutting line A-A ' deposits first patterning conductor layer 201, gate insulation layer 22 in regular turn on it, and protective layer 24; Data connection pad 104 ' part shown in the cutting line B-B ' deposits gate insulation layer 22, patterned semiconductor layer 203, second patterning conductor layer 205 in regular turn on it, and the protective layer 24 of the superiors; In data wire shown in the cutting line C-C ' 104 and the part that common wire 106 interlocks, deposit first patterning conductor layer 201, gate insulation layer 22, patterned semiconductor layer 203, second patterning conductor layer 205 on it in regular turn, and protective layer 24; Have gate insulation layer 22, patterned semiconductor layer 203, second patterning conductor layer 205 in regular turn in the part of transistor drain shown in the cutting line D-D ', and protective layer 24.
And in the step 1007 shown in Figure 1, the detailed process of the second road photo-marsk process is shown in Fig. 2 a.The employed second road photomask of this embodiment is preferably semi-transparent mask.At first, step 1007-1 deposits the photoresist layer on second conductor layer.Secondly, among the step 1007-2 with the photoresist layer patternization.Patterning photoresist layer 30 has first caliper zones and second caliper zones of different-thickness photoresist, and the photoresist thickness of first caliper zones is less than the photoresist thickness of second caliper zones.Then carry out step 1007-3 to carry out the etch process first time, second conductor layer and the semiconductor layer that is not covered by the photoresist layer produced etched pattern.Carry out step 1007-4 afterwards, remove the photoresist of first caliper zones,, former second conductor layer that is positioned under the first caliper zones photoresist is removed to carry out the etching second time of step 1007-5.Thereafter, carry out step 1007-6, the photoresist layer is removed comprehensively.So, the processing step 1007 of the patterned semiconductor layer 203 and second patterning conductor layer 205 is finished.
After step 1009 among Fig. 1 is finished, continue step 1011, carry out the 3rd road photo-marsk process.And the detailed process of the 3rd road photo-marsk process of step 1011 is shown in Fig. 2 b.The 3rd road photo-marsk process is that gate insulation layer and protective layer are formed patterned gate insulating barrier and patterning protective layer respectively.Employed the 3rd road photomask of this embodiment is preferably semi-transparent mask.At first in step 1011-1 deposition photoresist layer.Then step 1011-2 carries out patterning to the photoresist layer.Fig. 3 d for step 1011-2 finish after the accompanying drawing of formed patterning photoresist layer 30.Shown in Fig. 3 d cutting line D-D ', have first caliper zones and second caliper zones at drain electrode patterning photoresist layer 30 partly, first caliper zones and second caliper zones have first thickness d respectively
1With second thickness d
2, and first thickness d
1Photoresist thickness less than second thickness d
2Photoresist thickness.
Then, please cooperate with reference to figure 2b, 3a and Fig. 3 e.Step 1011-3 among Fig. 2 b is the etching first time of carrying out the 3rd road photo-marsk process.Etching for the first time is that etching is carried out in the zone that is not covered by any photoresist layer, comprises the gate insulation layer 22 of part and the protective layer 24 of part.Etch process preferably adopts reactive ion etch process for the first time.Fig. 3 e is after etching for the first time finishes, the accompanying drawing of formed patterned gate insulating barrier 221 and patterning protective layer 241.By Fig. 3 e as seen, after etching is for the first time finished, the scanning connection pad part shown in the cutting line A-A ', patterned gate insulating barrier 221 forms two openings respectively with patterning protective layer 241, and makes outside first patterning conductor layer, 201 parts are exposed to.Detailed speech, patterned gate insulating barrier 221 formed openings are that first opening, 51, the first openings 51 have first side 512 and expose part first patterning conductor layer 201 (scanning connection pad 102 '); Patterning protective layer 241 formed openings are that second opening, 61, the second openings 61 have second side 612 and corresponding first opening 51 and expose this first patterning conductor layer 201 of part (scanning connection pad 102 ').First side 512 and second side 612 are undercut construction, and preferably, patterned gate insulating barrier 221 forms first angle theta between first side 512 and first patterning conductor layer 201 under it
1, first angle theta
1Less than 90 °, patterning protective layer 241 forms second angle theta between second side 612 and the patterned gate insulating barrier 221 under it
2, second angle theta
2Less than 90 °.
Data connection pad part among Fig. 3 e shown in the cutting line B-B ', patterning protective layer 241 forms second opening 61, make that second patterning conductor layer 205 (data connection pad 104 ') part is exposed to outside.Second side 612 is a undercut construction, and preferably, patterning protective layer 241 forms second angle theta between second side 612 and second patterning conductor layer 205 under it
2, second angle theta
2Also less than 90 °.Similarly; in common wire shown in the cutting line C-C ' and the staggered part of data wire; that is ES position, etch-stop district; second opening 61 that patterning protective layer 241 forms makes outside patterned semiconductor layer 203 (etch-stop district ES) part is exposed to; and second side 612 of patterning protective layer 241 is a undercut construction; preferably, patterning protective layer 241 also forms second angle theta less than 90 ° between second side 612 and the patterned semiconductor layer under it 203
2In the drain electrode part shown in the cutting line D-D ', patterning protective layer 241 also forms opening, to expose second patterning conductor layer 205 (drain D) of part.
Please in the lump with reference to figure 2b and Fig. 4 a.At first please refer to the detail flowchart of the step 1011 of Fig. 2 b.After step 1011-3 finishes, carry out step 1011-4, remove the partially patterned photoresist layer 30 of tool first caliper zones.Generally speaking the method that removes the photoresist layer is the using plasma ashing, for example oxygen gas plasma ashing (O
2Plasma ashing); Adopt oxygen gas plasma ashing mode removable by photoresist that organic material constituted.And Fig. 4 a for step 1011-4 finish after in the accompanying drawing of the drain electrode of cutting line D-D ' part.As seen from the figure, after the partially patterned photoresist layer 30 of first caliper zones is removed, originally by the partially patterned protective layer 241 of photoresist layer 30 covering thereby outside being exposed to.Please in the lump with reference to figure 2b and Fig. 4 b.Shown in Fig. 2 b, after step 1011-4 finishes, carry out the etching second time at step 1011-5, the partially patterned protective layer 241 outside it will be exposed in step 1011-4 removes.The preferred using plasma etching of etch process for the second time.Ask for an interview Fig. 4 b, after the patterning protective layer 241 of cutting line D-D ' part was removed, patterning protective layer 241 formed the 3rd opening 71, and outside second patterning conductor layer 205 of part is exposed to.The 3rd opening 71 has the 3rd side 712, and patterning protective layer 241 forms the 3rd angle theta between the 3rd side 712 and second patterning conductor layer 205 under it
3, this 3rd angle theta
3Greater than 90 °.At last, be that the patterning photoresist layer 30 that will not be removed as yet Removes All among the step 1011-6; So far, the 3rd road photo-marsk process of step 1011 is finished.
Please refer to the schematic flow sheet that Fig. 1 makes active element array structure 100.As shown in Figure 1, carry out step 1013 after step 1011 is finished, on the zone of finishing the 3rd road photo-marsk process, form transparency conducting layer 40.The mode that forms transparency conducting layer 40 for example can be chemical vapour deposition technique (CVD) or physical vaporous deposition (PVD); The material of transparency conducting layer be preferably tin indium oxide (Indium Tin Oxide, ITO).Please in the lump with reference to figure 5, it is the structure accompanying drawing after step 1013 is finished.As shown in the figure, on the scanning connection pad part of cutting line A-A ', because first side 512 of patterned gate insulating barrier 221 and first angle theta between first patterning conductor layer 201 under it
1Less than 90 °, just the surface of first side 512 slopes inwardly; Based on physical characteristic, will can not cover during transparency conducting layer 40 depositions to first side 512.In other words; transparency conducting layer 40 is deposited on respectively on the plane of the patterned gate insulating barrier 221, patterning protective layer 241 and first patterning conductor layer 201 that are positioned at different level; yet, on patterned gate insulating barrier 221, patterning protective layer 241 and 201 formed sides of the section of having difference of first patterning conductor layer, interrupt.By first side 512 and first angle theta
1The interruption part that causes transparency conducting layer 40 is to be used for defining the position that needs electrical isolation.Similarly, because second side 612 also is (second angle theta just that slopes inwardly
2Less than 90 °), in the data connection pad part of cutting line B-B ' and data wire and the staggered part of common wire of cutting line C-C ', transparency conducting layer 40 all interrupts (transparency conducting layer 40 is not covered in second side 612) in second side, 612 parts, is not given unnecessary details herein.
Yet, among Fig. 5 in the drain electrode part shown in the cutting line D-D ', the 3rd angle theta between the 3rd side 712 of patterning protective layer 241 and second patterning conductor layer 205 under it
3Greater than 90 °, just the 3rd side 712 is surperficial outward-dipping.Based on physical characteristic, will cover to the 3rd side 712 during transparency conducting layer 40 depositions.In other words; transparency conducting layer 40 is deposited on respectively on the plane of the patterning protective layer 241 that is positioned at different level and second patterning conductor layer 205; also be deposited on the 3rd side 712; second patterning conductor layer 205 that links to each other with the 3rd side 712 so, respectively covers continuously and can electrically connect mutually by transparency conducting layer 40 with patterning protective layer 241.
Furthermore, please cooperate with reference to figure 3a and Fig. 5.Fig. 5 for the above embodiment of the present invention in the complete structure of the active element array structure 100 shown in Fig. 3 a in the cutaway view of cutting line A-A ', B-B ', C-C ', D-D '.
By Fig. 3 a as seen, active element array structure 100 has scan line 102 and connected scanning connection pad 102 ', data wire 104 and connected data connection pad 104 '; Wherein, scan line 102 intersects with data wire 104, and common wire 106 is parallel and crossing with data wire 104 with scan line 102.In addition, has transparency conducting layer 40 (formation pixel electrode) in the zone that is surrounded between scan line 102 and the data wire 104.Formed active element (transistor) is electrically connected on scan line 102, data wire 104 and transparency conducting layer 40.In addition, electric capacity line 107 is overlapped with transparency conducting layer 40, and this overlapping part forms storage capacitors, and storage capacitors and transistor drain electrically connect.
Please refer to the cutaway view of cutting line A-A ' among Fig. 5, the both sides of first patterning conductor layer 201 have patterned gate insulating barrier 221 and patterning protective layer 241 in regular turn.And patterned gate insulating barrier 221 and first opening 51 and second opening 61 that patterning protective layer 241 forms respectively make patterning conductor layer 201 parts of winning expose and can be covered by transparency conducting layer 40.Wherein and since first opening 51 and second opening 61 first angle that forms respectively and second angle all less than 90 °, so transparency conducting layer 40 is in first side 512 of first opening 51 and second side, the 612 formation sections of second opening 61.
Please refer to the cutaway view of cutting line B-B ' among Fig. 5, there are patterned gate insulating barrier 221 and patterned semiconductor layer 203 in the below of second patterning conductor layer 205, and both sides then are coated with patterning protective layer 241.Patterning protective layer 241 formed second openings 61 make second patterning conductor layer, 205 parts expose and can be covered by transparency conducting layer 40.Wherein, because second opening, 61 formed second angles are less than 90 °, so transparency conducting layer 40 forms sections in second side 612 of second opening 61.
Please refer to the cutaway view of cutting line C-C ' among Fig. 5, first patterning conductor layer 201, patterned gate insulating barrier 221, patterned semiconductor layer 203 are arranged on the substrate 10 in regular turn, and second patterning conductor layer 205; Patterning protective layer 241 covers the patterned semiconductor layer 203 of second patterning conductor layer 205 and part.Second opening 61 that patterning protective layer 241 forms makes patterned semiconductor layer 203 parts expose (that is, etch-stop district ES is partly exposed) and can be covered by transparency conducting layer 40.Wherein, because second opening, 61 formed second angles are less than 90 °, so transparency conducting layer 40 interrupts second side 612 in second opening 61.
Please refer to the cutaway view of cutting line D-D ' among Fig. 5, deposit patterned gate insulating barrier 221, patterned semiconductor layer 203 on the substrate 10 in regular turn, and second patterning conductor layer 205; Second patterning conductor layer 205 of patterning protective layer 241 cover parts.The 3rd opening 71 that patterning protective layer 241 forms makes patterned semiconductor layer 203 parts expose and can be covered by transparency conducting layer 40.Wherein, because the 3rd opening 71 formed the 3rd angles are greater than 90 °, therefore, transparency conducting layer 40 is continuous face in the 3rd side 712 of the 3rd opening 71.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is only for implementing example of the present invention.Must be pointed out that the embodiment that has disclosed does not limit the scope of the invention.On the contrary, be contained in the modification of the spirit of claim and scope and be equal to be provided with and all be contained in the scope of the present invention.
Claims (13)
1. the manufacture method of an active element array structure comprises:
On substrate, form first conductor layer;
Carry out the first road photo-marsk process so that this first conductor layer is patterned to first patterning conductor layer, this first patterning conductor layer comprises multi-strip scanning line, a plurality of grids that are connected with this multi-strip scanning line and a plurality of scanning connection pad, and with this multi-strip scanning line parallel and many common wires alternately;
On this substrate, form gate insulation layer, semiconductor layer and second conductor layer in regular turn;
Carry out the second road photo-marsk process, so that this semiconductor layer is formed patterned semiconductor layer, this second conductor layer is formed second patterning conductor layer, this patterned semiconductor layer comprises a plurality of channel regions and a plurality of etch-stops district, these a plurality of channel regions are positioned at this a plurality of grids top, this second patterning conductor layer comprises many data wires, a plurality of drain electrodes, a plurality of source electrodes and a plurality of data connection pad, these many data wires and this multi-strip scanning line and these many common wires intersect, these many data wires connect these a plurality of source electrodes and these many data connection pads, and these a plurality of drain electrodes are positioned at these a plurality of grids and this a plurality of channel regions top with these a plurality of source electrodes, and this a plurality of etch-stops district is positioned at these many data wires and these many common wire intersections;
On this substrate, form protective layer;
Carry out the 3rd road photo-marsk process, this gate insulation layer is formed the patterned gate insulating barrier, this protective layer is formed the patterning protective layer, this patterned gate insulating barrier has a plurality of first openings and exposes this first patterning conductor layer of part, this patterning protective layer has a plurality of second openings and a plurality of the 3rd opening, part this a plurality of second openings are to should a plurality of first openings and expose partly this first patterning conductor layer, and these a plurality of second openings of part expose this second patterning conductor layer of part or this patterned semiconductor layer of part, these a plurality of the 3rd openings then expose this second patterning conductor layer of part, wherein, this first opening, this second opening and the 3rd opening have first side respectively, second side and the 3rd side; And
Deposit transparent conductive layer on this substrate, wherein, be positioned on this first opening and this second opening this transparency conducting layer respectively to should first side and the position of this second side form section respectively.
2. the manufacture method of active element array structure as claimed in claim 1, wherein, this first side and this two side faces are undercut construction.
3. the manufacture method of active element array structure as claimed in claim 2, wherein, this first patterned conductor interlayer of this first side and below forms first angle, form second angle between this patterned gate insulating barrier of this second side and below, this second patterning conductor layer or this patterned semiconductor layer, this first angle and this second angle are all less than 90 degree.
4. the manufacture method of active element array structure as claimed in claim 1, wherein, this second patterned conductor interlayer of the 3rd side and below forms the 3rd angle, and the 3rd angle is greater than 90 degree.
5. the manufacture method of active element array structure as claimed in claim 1, wherein this second road photo-marsk process comprises:
Form the photoresist layer;
With this photoresist layer patternization, to form patterning photoresist layer, it has first caliper zones and second caliper zones, and this first caliper zones is thin than this second caliper zones;
Carry out first etch process, to remove this second layer conductor layer of part and this semiconductor layer of part that is not covered by this patterning photoresist layer;
Carry out second etch process, remove this second conductor layer of part that is positioned between this first caliper zones and this semiconductor layer; And
Remove this patterning photoresist layer comprehensively, form this patterned semiconductor layer and this second patterning conductor layer.
6. the manufacture method of active element array structure as claimed in claim 1, wherein the 3rd road photo-marsk process comprises:
Form the photoresist layer;
With this photoresist layer patternization, to form patterning photoresist layer, it has first caliper zones and second caliper zones, and this first caliper zones is thin than this second caliper zones;
Carry out first etch process,, form these a plurality of first openings and these a plurality of second openings to remove this gate insulation layer of part and this protective layer that is not covered by this patterning photoresist layer;
Carry out plasma ashing technology, remove this patterning photoresist layer of part of this first caliper zones;
Carry out second etch process, to form these a plurality of the 3rd openings at this protective layer of part that is not covered by this patterning photoresist layer; And
Remove this patterning photoresist layer comprehensively.
7. an active element array structure is disposed on the substrate, comprising:
First patterning conductor layer is disposed on this substrate, this first patterning conductor layer comprise multi-strip scanning line, a plurality of grids that are connected with this multi-strip scanning line and a plurality of scanning connection pad and with this multi-strip scanning line parallel and many alternate common wires;
The patterned gate insulating barrier is disposed on this first patterning conductor layer and this substrate, and this patterned gate insulating barrier has a plurality of first openings, to expose this first patterning conductor layer of part;
Patterned semiconductor layer is disposed on this patterned gate insulating barrier, and this patterned semiconductor layer comprises a plurality of channel regions and a plurality of etch-stops district, and these a plurality of channel regions are positioned at this a plurality of grids top;
Second patterning conductor layer, be disposed on this patterned semiconductor layer, this second patterning conductor layer comprises many data wires, a plurality of drain electrode and a plurality of source electrodes that are connected with these many data wires and a plurality of data connection pad, wherein these many data wires and this multi-strip scanning line intersect, and these a plurality of drain electrodes are positioned at these a plurality of grids and this a plurality of channel regions top with these a plurality of source electrodes, and this a plurality of etch-stops district is positioned at these many data wires and these many common wire intersections;
The patterning protective layer, this patterning protective layer has a plurality of second openings and a plurality of the 3rd opening, part this a plurality of second openings are to should a plurality of first openings and expose partly this first patterning conductor layer, and these a plurality of second openings of part expose this second patterning conductor layer of part or this patterned semiconductor layer, these a plurality of the 3rd openings expose this second patterning conductor layer of part, wherein, this first opening, this second opening and the 3rd opening have first side, second side and the 3rd side respectively; And
Transparency conducting layer, be disposed at all sidedly on this substrate, wherein be positioned on this first opening and this second opening this transparency conducting layer respectively to should first side and the position of this second side have section respectively, this transparency conducting layer that is positioned on the 3rd opening is continuous face to position that should the 3rd side.
8. active element array structure as claimed in claim 7, wherein, this first opening and this second opening are undercut construction.
9. active element array structure as claimed in claim 7, wherein, this first patterned conductor interlayer of this first side and below forms first angle, form second angle between this patterned gate insulating barrier of this second side and below, this second patterning conductor layer or this patterned semiconductor layer, this first angle and this second angle are all less than 90 degree.
10. active element array structure as claimed in claim 7, wherein this second patterned conductor interlayer of the 3rd side and below forms the 3rd angle, and the 3rd angle is greater than 90 degree.
11. active element array structure as claimed in claim 7, wherein these a plurality of first openings expose this a plurality of scanning connection pads.
12. active element array structure as claimed in claim 7, wherein part this a plurality of second openings are to should a plurality of first openings and expose this a plurality of scanning connection pads, and these a plurality of second openings of part expose these a plurality of data connection pads or this a plurality of etch-stops district partly.
13. active element array structure as claimed in claim 7, wherein these a plurality of the 3rd openings are positioned at this a plurality of drain electrodes top and expose this a plurality of drain electrodes.
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| CN103855087A (en) * | 2014-02-24 | 2014-06-11 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN106298646A (en) * | 2016-08-17 | 2017-01-04 | 深圳市华星光电技术有限公司 | The manufacture method of TFT substrate |
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2008
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101771049B (en) * | 2008-12-29 | 2012-04-25 | 万国半导体有限公司 | Real chip level package power metal oxide semiconductor field effect tube based on a bottom source electrode metal oxide semiconductor field effect tube |
| CN103855087A (en) * | 2014-02-24 | 2014-06-11 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN103855087B (en) * | 2014-02-24 | 2016-04-27 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display unit |
| US9379148B2 (en) | 2014-02-24 | 2016-06-28 | Boe Technology Group Co., Ltd. | Array substrate and method of manufacturing the same, and display device |
| US9698171B2 (en) | 2014-02-24 | 2017-07-04 | Boe Technology Group Co., Ltd. | Array substrate and method of manufacturing the same, and display device |
| CN106298646A (en) * | 2016-08-17 | 2017-01-04 | 深圳市华星光电技术有限公司 | The manufacture method of TFT substrate |
| WO2018032670A1 (en) * | 2016-08-17 | 2018-02-22 | 深圳市华星光电技术有限公司 | Method for manufacturing tft substrate |
| CN106298646B (en) * | 2016-08-17 | 2019-07-02 | 深圳市华星光电技术有限公司 | The production method of TFT substrate |
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