CN101330019B - Method for etching through-hole and method for removing passivation layer within the through-hole - Google Patents
Method for etching through-hole and method for removing passivation layer within the through-hole Download PDFInfo
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- CN101330019B CN101330019B CN2007100421443A CN200710042144A CN101330019B CN 101330019 B CN101330019 B CN 101330019B CN 2007100421443 A CN2007100421443 A CN 2007100421443A CN 200710042144 A CN200710042144 A CN 200710042144A CN 101330019 B CN101330019 B CN 101330019B
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Abstract
The invention discloses an etching method of a through hole, which comprises the steps as follows: a semiconductor substrate is provided; a passivating layer and a dielectric layer are deposited on the semiconductor substrate in sequence; a resist layer which has a through hole design is formed on the dielectric layer; the resist layer which has the through hole design is taken as a mask to etch the dielectric layer; the resist layer which has the through hole design or the etched dielectric layer is taken as the mask and fluorin-containing carbon-free gas is used for etching the passivating layer to form the through hole. A method for removing the passivating layer in the through hole provided by the invention comprises the steps as follows: a semiconductor substrate is provided; a passivating layer and a dielectric layer that has a contact hole are deposited on the semiconductor substrate in sequence, the contact hole is used for defining a through hole area; and the fluorin-containing carbon-free gas is used for etching the passivating layer in the through hole area. The production of polymer or residues during the etching process for removing the through hole can be reduced by selecting the fluorin-containing carbon-free gas as etching gas.
Description
Technical field
The present invention relates to the ic manufacturing technology field, passivation layer removal method in particularly a kind of etching method for forming through hole and the through hole area.
Background technology
Along with integrated circuit develops to the deep-submicron size, the dense degree of device and the complexity of technology constantly increase, and the strictness of technical process is controlled become even more important.Wherein, through hole has important function as the passage that is connected between multiple layer metal inter-level interconnects and device active region and the external circuitry in device architecture is formed, and the improvement of via etch process always is subjected to those skilled in the art's great attention.
The step of using existing method etching through hole comprises: the semiconductor-based end is provided; Deposit passivation layer and dielectric layer in turn on the described semiconductor-based end; On described dielectric layer, form patterned resist layer; With described patterned resist layer is mask, and order described dielectric layer of etching and passivation layer are to form through hole.Before the described passivation layer of deposition, also can comprise the step that forms oxide layer.
Usually, utilize fluorocarbon gas as via etch gas.But actual production finds that Fig. 1 is the structural representation of through hole interpolymer defective in the explanation prior art, as shown in Figure 1, utilize described fluorocarbon gas after removing through hole inner medium layer 30, when continuing to remove passivation layer 20, easily surface, the described semiconductor-based ends 10 forms polymer 21 in through hole.Be positioned at described semiconductor-based basal surface described polymer will follow-up to described through hole filled conductive material when forming device interconnection, cause contact resistance to increase, and then influence the device electric property, when serious, even the initiation component failure.
Perhaps, when when deposition deposits an oxide layer before the described passivation layer in advance, utilize described fluorocarbon gas to remove described passivation layer after, can form polymer on the oxide layer surface.The described polymer that is positioned at described oxide layer surface will stop the etching of described semiconductor-based basal surface oxide layer, promptly form residue at described semiconductor-based basal surface, then follow-up in described through hole the filled conductive material when forming device interconnection, cause contact resistance to increase, and then influence the device electric property, when serious, even cause component failure.
Thus, how to remove the polymer or the residue that form at described semiconductor-based basal surface behind the described passivation layer of etching and become those skilled in the art's problem demanding prompt solution.
On December 7th, 2005, disclosed notification number provided a kind of method of removing passivation layer in the Chinese patent of " CN1230876C ", the method that Fig. 2 provides in the documents for explanation utilizes is removed the schematic flow sheet of passivation layer, as shown in Figure 2, step 201: the mist that utilizes hydrogen and fluorocarbon gas composition is as the described passivation layer of etching gas etching; Step 202: clean the semiconductor substrate surface of removing passivation layer with fluorine-containing cleaning solvent; Step 203: the semiconductor substrate surface of removing passivation layer with washed with de-ionized water.Promptly, in the process of utilizing hydrogen and fluorocarbon gas removal passivation layer, also can in through hole, form polymer by semiconductor substrate surface, be that described polymer can clean in proper order by fluorine-containing cleaning solvent and deionized water and is removed, in other words, after utilizing described method to remove passivation layer, for not forming polymer at semiconductor substrate surface, need to increase fluorine-containing cleaning solvent and washed with de-ionized water step, and in the actual production process, along with reducing and the increase of through hole depth-to-width ratio of device size, utilize the wet difficulty of removing polymer of cleaning increasing.
Summary of the invention
The invention provides a kind of etching method for forming through hole, after can reducing via etch and finishing, the generation of semiconductor substrate surface polymer or residue in the through hole; The invention provides the passivation layer method of removaling in a kind of through hole area, can reduce the generation of polymer when removing the interior passivation layer of through hole area or residue.
A kind of etching method for forming through hole provided by the invention comprises:
The semiconductor-based end, be provided;
Deposit passivation layer and dielectric layer in turn on the described semiconductor-based end;
On described dielectric layer, form resist layer with via hole image;
With described resist layer with via hole image is mask, the described dielectric layer of etching;
With described have the resist layer of via hole image or the described dielectric layer of etching be mask, adopt the described passivation layer of fluorine-containing carbon-free gas etching, to form through hole.
Alternatively, before deposit passivation layer, also comprise the step of deposited oxide layer; Alternatively, before forming through hole, also comprise the step of the described oxide layer of etching; Alternatively, described passivation material comprises a kind of or its combination in silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide or the carbonitride of silicium; Alternatively, described fluorine-containing carbon-free gas includes but not limited to a kind of or its combination in Nitrogen trifluoride, silicon fluoride or the hydrogen fluoride.
A kind of method of removing passivation layer in the through hole area comprises:
The semiconductor-based end, be provided;
Deposit passivation layer and have the dielectric layer of contact hole in turn on the described semiconductor-based end, described contact hole is in order to the definition through hole area;
Adopt described passivation layer in the described through hole area of fluorine-containing carbon-free gas etching.
Alternatively, the described step with dielectric layer of contact hole of deposition comprises:
The described dielectric layer of deposition on described passivation layer;
The described dielectric layer of etching is to form described dielectric layer with contact hole.
Alternatively, the step that forms described contact hole comprises:
On described dielectric layer, form resist layer with via hole image;
With described resist layer with via hole image is mask, and the described dielectric layer of etching is to form described contact hole.
Alternatively, before the described passivation layer of deposition, also comprise the step of deposited oxide layer; Alternatively, described passivation material comprises a kind of or its combination in silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide or the carbonitride of silicium; Alternatively, described fluorine-containing carbon-free gas comprises a kind of or its combination in Nitrogen trifluoride, silicon fluoride or the hydrogen fluoride.
Compared with prior art, the present invention has the following advantages: by selecting for use fluorine-containing carbon-free gas as the passivation layer etching gas, can reduce the generation of polymer when removing passivation layer in the through hole or residue, and then follow-up in described through hole the filled conductive material when forming device interconnection, unlikely owing to the excessive contact resistance of formation, and influence the device electric property.
Description of drawings
Fig. 1 is the structural representation of through hole interpolymer defective in the explanation prior art;
The method that Fig. 2 provides in the documents for explanation utilizes is removed the schematic flow sheet of passivation layer;
Fig. 3 is the schematic flow sheet of the etching method for forming through hole of the explanation embodiment of the invention;
Fig. 4 is the schematic flow sheet of passivation layer removal method in the through hole area of the explanation embodiment of the invention.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work for those skilled in the art with advantage of the present invention.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
The invention provides a kind of etching method for forming through hole, the step of using said method etching through hole comprises: the semiconductor-based end is provided; Deposit passivation layer and dielectric layer in turn on the described semiconductor-based end; On described dielectric layer, form resist layer with via hole image; With described resist layer with via hole image is mask, adopts the described dielectric layer of fluoro-gas etching; With described have the resist layer of via hole image or the described dielectric layer of etching be mask, adopt the described passivation layer of fluorine-containing carbon-free gas etching, to form through hole.
Fig. 3 is the schematic flow sheet of the etching method for forming through hole of the explanation embodiment of the invention, and as shown in Figure 3, the concrete steps of using method etching through hole provided by the invention comprise:
Step 301: the semiconductor-based end is provided.
The described semiconductor-based end via definition device active region on the Semiconductor substrate and finish shallow trench isolation from, form after forming grid structure and source region and drain region then.
In addition, the described semiconductor-based end also can via on the Semiconductor substrate definition device active region and finish shallow trench isolation from, then form grid structure and source region and drain region after, and then after depositing first interlayer dielectric layer, continue to form the ground floor through hole, and fill described ground floor through hole, subsequently, form behind the formation the first metal layer.
Can expand ground, behind deposition N interlayer dielectric layer, continue to form N layer through hole, and fill described N layer through hole, subsequently, form the N metal level after, obtain the described semiconductor-based end.
Obviously, the number N of the interlayer dielectric layer that comprises can be any natural number at described the semiconductor-based end, and as 1,3,5,7 or 9 etc., the concrete number of the interlayer dielectric layer that comprises is determined according to product requirement at described the semiconductor-based end.
Described before-metal medium layer covers described grid structure and source region and drain region and fills up the linear slit that is positioned between described grid structure; Described grid structure comprises the side wall and the gate oxide of grid, all around gate.Described grid structure also can comprise the barrier layer that covers described grid and side wall.
Step 302: deposit passivation layer and dielectric layer in turn on the described semiconductor-based end.
Described passivation material includes but not limited to a kind of or its combination in silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide or the carbonitride of silicium.The deposition process of described passivation layer can adopt traditional technology, repeats no more.
Before deposit passivation layer, can comprise the step of deposited oxide layer.Described oxide layer perhaps, in order to isolate at the described semiconductor-based end in processing procedure, makes it avoid polluting in order to improve described passivation layer to the degree of adhesion at the described semiconductor-based end.
Step 303: on described dielectric layer, form resist layer with via hole image.
Step 304: with described resist layer with via hole image is mask, the described dielectric layer of etching.
Etching gas includes but not limited to octafluoroization three carbon (C
3F
8), octafluoroization four carbon (C
4F
8), hexafluoroization four carbon (C
4F
6), hexafluoroization two carbon (C
2F
6), Nitrogen trifluoride (NF
3), silicon fluoride (SiF
4) or hydrogen fluoride (HF) in a kind of and the combination.
Step 305: with described have the resist layer of via hole image or the described dielectric layer of etching be mask, adopt the described passivation layer of fluorine-containing carbon-free gas etching, to form through hole.
Described fluorine-containing carbon-free gas includes but not limited to Nitrogen trifluoride (NF
3), silicon fluoride (SiF
4) or hydrogen fluoride (HF) in a kind of or its combination, be preferably NF
3
Also need comprise assist gas in the etching reaction chamber during the described passivation layer of etching, described assist gas is in order to provide dissociate gas and balanced reaction chamber pressure, and described assist gas can be selected argon gas (Ar) and helium (He) for use.Required plasma dissociation power (SRF) scope is 300～500 watts (W); Required plasma sputter power (BRF) scope is 50～200W; The range of flow of described fluorine-containing carbon-free gas is 5～20sccm; The range of flow of described argon gas is 200～400sccm; The range of flow of described helium is 300～450sccm.
In addition,, comprise the step of deposited oxide layer, then before forming through hole, also comprise the step of the described oxide layer of etching if before deposit passivation layer.
Etching gas includes but not limited to octafluoroization three carbon (C
3F
8), octafluoroization four carbon (C
4F
8), hexafluoroization four carbon (C
4F
6), hexafluoroization two carbon (C
2F
6), Nitrogen trifluoride (NF
3), silicon fluoride (SiF
4) or hydrogen fluoride (HF) in a kind of and the combination.
It should be noted that, adopt fluorine-containing carbon-free the gas described dielectric layer of etching, passivation layer and the oxide layer that may exist in turn, can reduce the steps such as cleaning in the etching reaction chamber in the processing procedure, be beneficial to the raising of production efficiency.
By selecting the etching gas of fluorine-containing carbon-free gas for use as passivation layer in the etching through hole, can reduce the generation of polymer when removing passivation layer in the through hole or residue, then follow-up in described through hole the filled conductive material when forming device interconnection, unlikely owing to the excessive contact resistance of formation, and influence the device electric property.
The step of using passivation layer in the method removal through hole area provided by the invention comprises: the semiconductor-based end is provided; Deposit passivation layer and have the dielectric layer of contact hole in turn on the described semiconductor-based end, described contact hole is in order to the definition through hole area; Adopt described passivation layer in the described through hole area of fluorine-containing carbon-free gas etching.
Fig. 4 is the schematic flow sheet of passivation layer removal method in the through hole area of the explanation embodiment of the invention, and as shown in Figure 4, the concrete steps of using described passivation layer in the method removal through hole area provided by the invention comprise:
Step 401: the semiconductor-based end is provided.
The described semiconductor-based end via definition device active region on the Semiconductor substrate and finish shallow trench isolation from, form after forming grid structure and source region and drain region then.
In addition, the described semiconductor-based end also can via on the Semiconductor substrate definition device active region and finish shallow trench isolation from, then form grid structure and source region and drain region after, and then after depositing first interlayer dielectric layer, continue to form the ground floor through hole, and fill described ground floor through hole, subsequently, form behind the formation the first metal layer.
Can expand ground, behind deposition N interlayer dielectric layer, continue to form N layer through hole, and fill described N layer through hole, subsequently, form the N metal level after, obtain the described semiconductor-based end.
Obviously, the number N of the interlayer dielectric layer that comprises can be any natural number at described the semiconductor-based end, and as 1,3,5,7 or 9 etc., the concrete number of the interlayer dielectric layer that comprises is determined according to product requirement at described the semiconductor-based end.
Described before-metal medium layer covers described grid structure and source region and drain region and fills up the linear slit that is positioned between described grid structure; Described grid structure comprises the side wall and the gate oxide of grid, all around gate.Described grid structure also can comprise the barrier layer that covers described grid and side wall.
Step 402: deposit passivation layer and have the dielectric layer of contact hole in turn on the described semiconductor-based end, described contact hole is in order to the definition through hole area.
After described contact hole means and form via hole image in described dielectric layer, has the zone of described via hole image in the described dielectric layer; Described through hole area means the zone that can form through hole behind the described passivation layer in removing described zone.
Described passivation material includes but not limited to a kind of or its combination in silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide or the carbonitride of silicium.The deposition process of described passivation layer can adopt traditional technology, repeats no more.
Depositing described step with dielectric layer of contact hole comprises: the described dielectric layer of deposition on described passivation layer; The described dielectric layer of etching is to form described dielectric layer with contact hole.
The step that forms described contact hole comprises: form the resist layer with via hole image on described dielectric layer; With described resist layer with via hole image is mask, and the described dielectric layer of etching is to form described contact hole.
The described passivation layer surface of described contact hole expose portion, the described passivation layer of described exposed portions can be removed after experience subsequent etching process, after described passivation layer is removed, will form through hole; Then, by filled conductive material in described through hole, the interconnection of device and external circuit will be realized.
In addition, before deposit passivation layer, can comprise the step of deposited oxide layer.Described oxide layer perhaps, in order to isolate at the described semiconductor-based end in processing procedure, makes it avoid polluting in order to improve described passivation layer to the degree of adhesion at the described semiconductor-based end.
At this moment, after described passivation layer is removed, continue to remove described oxide layer, can form through hole; And then, by filled conductive material in described through hole, will realize the interconnection of device and external circuit.
Etching gas includes but not limited to octafluoroization three carbon (C
3F
8), octafluoroization four carbon (C
4F
8), hexafluoroization four carbon (C
4F
6), hexafluoroization two carbon (C
2F
6), Nitrogen trifluoride (NF
3), silicon fluoride (SiF
4) or hydrogen fluoride (HF) in a kind of and the combination.
Step 403: adopt described passivation layer in the described through hole of fluorine-containing carbon-free gas etching.
Described fluorine-containing carbon-free gas includes but not limited to Nitrogen trifluoride (NF
3), silicon fluoride (SiF
4) or hydrogen fluoride (HF) in a kind of or its combination, be preferably NF
3
Also need comprise assist gas in the etching reaction chamber during the described passivation layer of etching, described assist gas is in order to provide dissociate gas and balanced reaction chamber pressure, and described assist gas can be selected argon gas (Ar) and helium (He) for use.
Required plasma dissociation power (SRF) scope is 300～500 watts (W); Required plasma sputter power (BRF) scope is 50～200W; The range of flow of described fluorine-containing carbon-free gas is 5～20sccm; The range of flow of described argon gas is 200～400sccm; The range of flow of described helium is 300～450sccm.
By selecting for use fluorine-containing carbon-free gas as passivation layer etching gas in the through hole, can reduce polymer when removing passivation layer in the through hole or residue generation so that follow-up in described through hole the filled conductive material when forming device interconnection, unlikely owing to the excessive contact resistance of formation, and influence the device electric property.
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (11)
1. etching method for forming through hole comprises:
The semiconductor-based end, be provided;
Deposit passivation layer and dielectric layer in turn on the described semiconductor-based end;
On described dielectric layer, form resist layer with via hole image;
With described resist layer with via hole image is mask, the described dielectric layer of etching;
With described have the resist layer of via hole image or the described dielectric layer of etching be mask, adopt the described passivation layer of fluorine-containing carbon-free gas etching, to form through hole.
2. etching method for forming through hole according to claim 1 is characterized in that: before deposit passivation layer, also comprise the step of deposited oxide layer.
3. etching method for forming through hole according to claim 2 is characterized in that: before forming through hole, also comprise the step of the described oxide layer of etching.
4. according to claim 1 or 2 or 3 described etching method for forming through hole, it is characterized in that: described passivation material comprises a kind of or its combination in silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide or the carbonitride of silicium.
5. according to claim 1 or 2 or 3 described etching method for forming through hole, it is characterized in that: described fluorine-containing carbon-free gas includes but not limited to a kind of or its combination in Nitrogen trifluoride, silicon fluoride or the hydrogen fluoride.
6. method of removing passivation layer in the through hole area comprises:
The semiconductor-based end, be provided;
Deposit passivation layer and have the dielectric layer of contact hole in turn on the described semiconductor-based end, described contact hole is in order to the definition through hole area;
Adopt described passivation layer in the described through hole area of fluorine-containing carbon-free gas etching.
7. the method for passivation layer in the removal through hole area according to claim 6 is characterized in that: deposit described step with dielectric layer of contact hole and comprise:
The described dielectric layer of deposition on described passivation layer;
The described dielectric layer of etching is to form described dielectric layer with contact hole.
8. the method for passivation layer in the removal through hole area according to claim 7, it is characterized in that: the step that forms described contact hole comprises:
On described dielectric layer, form resist layer with via hole image;
With described resist layer with via hole image is mask, and the described dielectric layer of etching is to form described contact hole.
9. according to the method for passivation layer in claim 6 or the 7 or 8 described removal through hole areas, it is characterized in that: before the described passivation layer of deposition, also comprise the step of deposited oxide layer.
10. according to the method for passivation layer in claim 6 or the 7 or 8 described removal through hole areas, it is characterized in that: described passivation material comprises a kind of or its combination in silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide or the carbonitride of silicium.
11. according to the method for passivation layer in claim 6 or the 7 or 8 described removal through hole areas, it is characterized in that: described fluorine-containing carbon-free gas comprises a kind of or its combination in Nitrogen trifluoride, silicon fluoride or the hydrogen fluoride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100421443A CN101330019B (en) | 2007-06-18 | 2007-06-18 | Method for etching through-hole and method for removing passivation layer within the through-hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100421443A CN101330019B (en) | 2007-06-18 | 2007-06-18 | Method for etching through-hole and method for removing passivation layer within the through-hole |
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| CN101330019A CN101330019A (en) | 2008-12-24 |
| CN101330019B true CN101330019B (en) | 2010-12-22 |
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| CN2007100421443A Expired - Fee Related CN101330019B (en) | 2007-06-18 | 2007-06-18 | Method for etching through-hole and method for removing passivation layer within the through-hole |
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|---|---|---|---|---|
| CN102431960A (en) * | 2011-12-07 | 2012-05-02 | 华中科技大学 | Silicon through hole etching method |
| CN113130384A (en) * | 2020-01-16 | 2021-07-16 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor structure |
| CN112201615B (en) * | 2020-09-09 | 2024-04-19 | 长江存储科技有限责任公司 | Method for manufacturing bonding pad of semiconductor device and method for manufacturing semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5312518A (en) * | 1991-05-31 | 1994-05-17 | Sony Corporation | Dry etching method |
| US6524963B1 (en) * | 1999-10-20 | 2003-02-25 | Chartered Semiconductor Manufacturing Ltd. | Method to improve etching of organic-based, low dielectric constant materials |
| CN1468445A (en) * | 2000-08-31 | 2004-01-14 | �����ɷ� | Method for selective etching of oxides |
| CN1618121A (en) * | 2001-12-12 | 2005-05-18 | 应用材料有限公司 | Process for selectively etching dielectric layers |
-
2007
- 2007-06-18 CN CN2007100421443A patent/CN101330019B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5312518A (en) * | 1991-05-31 | 1994-05-17 | Sony Corporation | Dry etching method |
| US6524963B1 (en) * | 1999-10-20 | 2003-02-25 | Chartered Semiconductor Manufacturing Ltd. | Method to improve etching of organic-based, low dielectric constant materials |
| CN1468445A (en) * | 2000-08-31 | 2004-01-14 | �����ɷ� | Method for selective etching of oxides |
| CN1618121A (en) * | 2001-12-12 | 2005-05-18 | 应用材料有限公司 | Process for selectively etching dielectric layers |
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