CN101326635B - Semiconductor device and manufacture method thereof - Google Patents

Semiconductor device and manufacture method thereof Download PDF

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Publication number
CN101326635B
CN101326635B CN2005800523041A CN200580052304A CN101326635B CN 101326635 B CN101326635 B CN 101326635B CN 2005800523041 A CN2005800523041 A CN 2005800523041A CN 200580052304 A CN200580052304 A CN 200580052304A CN 101326635 B CN101326635 B CN 101326635B
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mentioned
film
pattern
semiconductor device
corrosion
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CN101326635A (en
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中川进一
三宫逸郎
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12347—Plural layers discontinuously bonded [e.g., spot-weld, mechanical fastener, etc.]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A semiconductor device with a flash memory and a method of manufacturing the same designed for a yield rate improvement are provided. A method of manufacturing a semiconductor device comprises steps of: exposing a photoresist by using an exposure mask (105) provided with a light shield pattern (102) having not less than two narrow portions (104); forming a plurality of strip resist patterns (68) by developing the photoresist; etching selectively a first conductive film (67) by using the resist pattern (68); forming an intermediate insulation layer (69) on the first conductive film (67); forming a second conductive film (74) on the intermediate insulation layer (69); ; patterning the first conductive film (67), the intermediate insulation film (69) and the second conductive film (74) to form a flash memory cell (FL), and forming a structural body (98) provided with a lower conductive pattern (67b), a cutaway piece (69c) of the intermediate insulation film (69) and a dummy gate electrode (74b) in order.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof.
Background technology
Now, even the flash memory (flash memory) that also can keep stored information of cutting off the electricity supply uses in the such mobile device of mobile phone, its technology is extensively popularized.
Each memory cell in this flash memory (memory cell) is formed on tunnel insulator film, floating boom (Floating gate), intermediate insulating film, control gate (control gate) successively and forms on the Semiconductor substrate, such memory cell with the integrated one-tenth of peripheral circuit on Semiconductor substrate, thereby constitute a flash memory.
For example, in following patent documentation 1 to 3 above-mentioned flash memory is disclosed.
In the manufacturing process of flash memory, carry out forming the so various pattern-forming operations of operation of control gate by conducting film being carried out pattern-forming, after pattern-forming if residual have a unnecessary film, then since this film peel off and again attached on other parts, it is bad that thereby this part becomes pattern, and then produce the low such problem of finished semiconductor device product rate.
In addition, be not limited only to flash memory, in the manufacturing process of general semiconductor device, be accompanied by the granular of pattern, the distortion of the equipment pattern of floating boom that produces because of the optical adjacent in the exposure process (optical proximity) effect etc. becomes obvious.In order to prevent such pattern deformation, usually (Optical ProximityCorrection: shape correction optical near-correction) makes the projection image of this light-shielding pattern become the design shape of equipment pattern the light-shielding pattern of middle mask (reticle) (exposure mask) to be implemented so-called OPC.
For example, in following patent documentation 4, as OPC to the repeat patterns of band shape, motion the oblique correction that cuts the angle of each pattern.
Patent documentation 1:JP spy opens the 2005-129760 communique
Patent documentation 2:JP spy opens the 2005-142362 communique
Patent documentation 3:JP spy opens the 2005-244086 communique
Patent documentation 4:JP spy opens flat 1-188857 communique
Summary of the invention
The object of the present invention is to provide a kind ofly, have flash cell, can improve the semiconductor device and the manufacture method thereof of rate of finished products.
According to a viewpoint of the present invention, a kind of semiconductor device is provided, it is characterized in that having:
Semiconductor substrate; The active region of a plurality of band shapes, it delimited on above-mentioned Semiconductor substrate, and being parallel to each other and separating has at interval; Element separating insulation film, it is formed on the above-mentioned Semiconductor substrate, and surrounds above-mentioned active region; Flash cell, it is formed with tunnel insulator film, floating boom, intermediate insulating film and control gate successively on above-mentioned active region; The bottom conductor pattern of island, it is at each of above-mentioned active region, is formed on the said elements separating insulation film of end of above-mentioned active region, and by constituting with above-mentioned floating boom identical materials; The section of above-mentioned intermediate insulating film, it forms in the mode that covers above-mentioned a plurality of bottom conductor patterns, and is shared by each of this bottom conductor pattern; Illusory conductive pattern, it is formed in the section of above-mentioned intermediate insulating film by constituting with above-mentioned control gate identical materials, and is shared by each of above-mentioned bottom conductor pattern; The fence of above-mentioned intermediate insulating film, it is on the said elements separated region, and extend to the side of above-mentioned bottom conductor pattern the side along above-mentioned active region from above-mentioned floating boom.
In addition, according to another viewpoint of the present invention, a kind of manufacture method of semiconductor device is provided, it is characterized in that, comprise:, on above-mentioned Semiconductor substrate, delimit the operation that is parallel to each other and separates the active region of spaced a plurality of band shapes by on Semiconductor substrate, forming element separating insulation film; Be positioned at the operation that forms tunnel insulator film on the above-mentioned Semiconductor substrate of above-mentioned active region; On above-mentioned tunnel insulator film and said elements separating insulation film, form the operation of first conducting film respectively; The operation of coating photoresist on above-mentioned first conducting film; Use exposure mask, the operation that above-mentioned photoresist is exposed, described exposure mask has the structure that has formed the light-shielding pattern of a plurality of band shapes on transparency carrier in parallel to each other, and described light-shielding pattern has the narrow width portion more than two that the terminad width narrows down successively; Above-mentioned photoresist is developed, form the operation of the corrosion-resisting pattern of each and the separated a plurality of band shapes comprise above-mentioned a plurality of active regions; Above-mentioned corrosion-resisting pattern as mask, is optionally carried out etched operation to above-mentioned first conducting film; Remove the operation of above-mentioned corrosion-resisting pattern; After removing above-mentioned corrosion-resisting pattern, on said elements separating insulation film and above-mentioned first conducting film, form the operation of intermediate insulating film respectively; On above-mentioned intermediate insulating film, form the operation of second conducting film; By above-mentioned first conducting film, above-mentioned intermediate insulating film and above-mentioned second conducting film are carried out pattern-forming, on above-mentioned active region, form the flash cell be formed with above-mentioned tunnel insulator film, floating boom, above-mentioned intermediate insulating film and control gate successively, and on the said elements separating insulation film of the end of above-mentioned active region, form the operation of the structure of the section that is formed with the bottom conductor pattern of island, above-mentioned intermediate insulating film successively and illusory gate electrode.
Below, effect of the present invention is described.
According to the present invention, in the operation that photoresist is exposed, use the light mask of light-shielding pattern with a plurality of band shapes, described light-shielding pattern has the narrow width portion more than two that narrows down successively towards terminal width.
By the such narrow width portion more than two is set, can prevent reducing of the focus that causes because of the optical adjacent effect, even the focusing during exposure is offset a little, can prevent that also projection image from joining each other.
Its result, corrosion-resisting pattern is being used as mask, optionally first conducting film is carried out in the etched operation, first conducting film is carried out the band shape of pattern-forming for the deflection that reduced the pattern that causes because of the optical adjacent effect, thus the interconnecting each other of first conducting film behind the pattern-forming that suppresses to produce because of the optical adjacent effect.
At this, in the operation that forms flash cell and structure, the intermediate insulating film of side that is formed with first conducting film is not etched, thereby stays as fence.In addition,, also suppressed the radian of following pattern deformation to produce of the fence between control gate and the illusory conductive pattern, become real linearity because first conductive film pattern is configured as the band shape that has suppressed the pattern deformation that causes because of the optical adjacent effect.
The fence of such linearity is the combination between different types of shape, for example, compares with the fence that curve and straight line combination obtain, and is difficult to peel off in operation.Therefore, in the present invention, can prevent because of the fence that peels off produces the pattern condition of poor of this part attached to other part, thereby can improve finished semiconductor device product rate.
In addition, in the present invention, owing to the section that has covered intermediate insulating film with illusory conductive pattern, even the first end parts of first conducting film has radian because of the optical adjacent effect, the curvilinear step part of shape that reflects first conducting film of this part forms section, also because illusory conductive pattern becomes etching mask, so step part can not become fence.Therefore, can not form this curvilinear unsettled fence, can further avoid effectively being accompanied by the generation of fence and the low situation of finished semiconductor device product rate that produces.
Description of drawings
Fig. 1 is the sectional view (its 1) in the manufacture process of imaginary semiconductor device.
Fig. 2 is the sectional view (its 2) in the manufacture process of imaginary semiconductor device.
Fig. 3 is the sectional view (its 3) in the manufacture process of imaginary semiconductor device.
Fig. 4 is the sectional view (its 4) in the manufacture process of imaginary semiconductor device.
Fig. 5 is the sectional view (its 5) in the manufacture process of imaginary semiconductor device.
Fig. 6 is the sectional view (its 6) in the manufacture process of imaginary semiconductor device.
Fig. 7 is the sectional view (its 7) in the manufacture process of imaginary semiconductor device.
Fig. 8 is the sectional view (its 8) in the manufacture process of imaginary semiconductor device.
Fig. 9 is the sectional view (its 9) in the manufacture process of imaginary semiconductor device.
Figure 10 is the sectional view (its 10) in the manufacture process of imaginary semiconductor device.
Figure 11 is the sectional view (its 11) in the manufacture process of imaginary semiconductor device.
Figure 12 is the sectional view (its 12) in the manufacture process of imaginary semiconductor device.
Figure 13 is the sectional view (its 13) in the manufacture process of imaginary semiconductor device.
Figure 14 is the sectional view (its 14) in the manufacture process of imaginary semiconductor device.
Figure 15 is the sectional view (its 15) in the manufacture process of imaginary semiconductor device.
Figure 16 is the sectional view (its 16) in the manufacture process of imaginary semiconductor device.
Figure 17 is the vertical view (its 1) in the manufacture process of imaginary semiconductor device.
Figure 18 is the vertical view (its 2) in the manufacture process of imaginary semiconductor device.
Figure 19 is the vertical view (its 3) in the manufacture process of imaginary semiconductor device.
Figure 20 is the vertical view (its 4) in the manufacture process of imaginary semiconductor device.
Figure 21 is the vertical view (its 5) in the manufacture process of imaginary semiconductor device.
Figure 22 is the vertical view (its 6) in the manufacture process of imaginary semiconductor device.
Figure 23 is the vertical view (its 7) in the manufacture process of imaginary semiconductor device.
Figure 24 is the vertical view (its 8) in the manufacture process of imaginary semiconductor device.
Figure 25 is the vertical view (its 9) in the manufacture process of imaginary semiconductor device.
Figure 26 is the vertical view (its 10) in the manufacture process of imaginary semiconductor device.
Figure 27 is the vertical view (its 11) in the manufacture process of imaginary semiconductor device.
Figure 28 is the vertical view (its 12) in the manufacture process of imaginary semiconductor device.
Figure 29 is the amplification plan view of employed reticle mask when making imaginary semiconductor device.
Figure 30 is that the flat shape of first corrosion-resisting pattern that forms for the reticle mask that uses Figure 29 when the exposure device out of focus what kind of variation takes place and carried out the vertical view that simulation obtains.
Figure 31 is the amplification plan view of the reticle mask that works out for the distortion that reduces the caused projection image of optical adjacent effect in first execution mode of the present invention.
Figure 32 is that the flat shape of first corrosion-resisting pattern that forms for the reticle mask that uses Figure 31 when the exposure device out of focus what kind of variation takes place and carried out the vertical view that simulation obtains.
Figure 33 is the amplification plan view of the reticle mask that works out for the distortion that further reduces the caused projection image of optical adjacent effect in first execution mode of the present invention.
Figure 34 is that the flat shape of first corrosion-resisting pattern that forms for the reticle mask that uses Figure 33 when the exposure device out of focus what kind of variation takes place and carried out the vertical view that simulation obtains.
Figure 35 is the figure of the SEM picture of the analog result that shows the flat shape of first corrosion-resisting pattern that the reticle mask of the reticle mask that uses respectively in the preparatory items and first execution mode of the present invention obtains in the lump, actual corrosion-resisting pattern.
Figure 36 is with reticle mask illustrated in the preparatory items (left side), only establish a narrow width portion reticle mask (central authorities), and the order that two sections narrow width portion reticle masks (right side) are set, schematically show the vertical view of the appearance that focus (focus margin) amplifies.
Figure 37 is the sectional view (its 1) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 38 is the sectional view (its 2) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 39 is the sectional view (its 3) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 40 is the sectional view (its 4) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 41 is the sectional view (its 5) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 42 is the sectional view (its 6) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 43 is the sectional view (its 7) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 44 is the sectional view (its 8) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 45 is the sectional view (its 9) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 46 is the sectional view (its 10) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 47 is the sectional view (its 11) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 48 is the sectional view (its 12) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 49 is the sectional view (its 13) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 50 is the sectional view (its 14) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 51 is the sectional view (its 15) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 52 is the sectional view (its 16) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 53 is the sectional view (its 17) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 54 is the sectional view (its 18) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 55 is the sectional view (its 19) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 56 is the sectional view (its 20) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 57 is the sectional view (its 1) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 58 is the sectional view (its 2) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 59 is the sectional view (its 3) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 60 is the sectional view (its 4) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 61 is the sectional view (its 5) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 62 is the sectional view (its 6) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 63 is the sectional view (its 7) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 64 is the sectional view (its 8) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 65 is the sectional view (its 9) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 66 is the sectional view (its 10) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 67 is the sectional view (its 11) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 68 is the sectional view (its 12) in the manufacture process of semiconductor device of second execution mode of the present invention.
Figure 69 is the amplification plan view that is illustrated in the position relation in the design of the reticle mask that illustrates among Figure 33 and illusory control gate.
Embodiment
(1) explanation of preparatory items
Before the explanation embodiments of the present invention, describe for preparatory items of the present invention.
Fig. 1 to Figure 16 is the sectional view in the manufacture process of imaginary semiconductor device, and Figure 17 to Figure 28 is its vertical view.Below, describe for the manufacture method of this semiconductor device.
At first, as shown in Figure 1, form on silicon (semiconductor) substrate 1 after the element separating tank 1a, (Chemical Vapor Deposition: chemical vapour deposition (CVD)) method is filled the silicon oxide layer as element separating insulation film 2 in this element separating tank 1a to use CVD.
Figure 17 is formed as described above element separating insulation film 2 vertical view afterwards, and the peripheral circuit area I of Fig. 1 of front and unit area II (first cross section) are the sectional views along the A1-A1 line among Figure 17.In addition, second to the 4th cross section of the unit area II among Fig. 1 is equivalent to the sectional view of B1-B1 line, C1-C1 line and D1-D1 line along Figure 17 respectively.
As shown in figure 17, peripheral circuit area I and unit area II on Semiconductor substrate 1, delimited.And, near its end of the unit area II of Figure 17, promptly near the end of the active region of the silicon substrate 1 that is surrounded by element separating tank 1a, be exaggerated.
Below, the operation before the represented cross section structure describes among Fig. 2 to obtaining.
At first, carry out thermal oxidation, form first heat oxide film 6 by surface to the silicon substrate 1 that do not form element separating insulation film 2 parts.Then, by the ion of this first heat oxide film 6 as filter membrane (throughmembrane) injected, in the deep of the silicon substrate of unit area II, form n trap 3.In addition, form a p trap 5 in the silicon substrate 1 of the part more shallow in the II of unit area, and in the silicon substrate 1 of peripheral circuit area I, form the 2nd p trap 4 than this n trap 3.
Below, describe obtaining cross section structure represented among Fig. 3 operation before.
At first, remove first heat oxide film 6, once more silicon substrate 1 is carried out thermal oxidation, on the silicon substrate 1 of peripheral circuit area I and unit area II, form tunnel insulator film 15 as filter membrane.Then, forming on tunnel insulator film 15 after the polysilicon film as first conducting film 7, apply the photoresist of eurymeric on first conducting film 7, and it is exposed, develops, is the first banded corrosion-resisting pattern 8 thereby form flat shape.
Figure 18 is the vertical view after this operation finishes, and the peripheral circuit area I of Fig. 3 of front and unit area II (first cross section) are the sectional views along the A2-A2 line of Figure 18.In addition, second to the 4th cross section of the unit area II of Fig. 3 is equivalent to respectively B2-B2 line, the C2-C2 line along Figure 18, the sectional view of D2-D2 line.
As shown in figure 18, a plurality of first corrosion-resisting patterns 8 should form to become banded mode mutually isolatedly, but in the present example, because the optical adjacent effect during exposure causes making it to form the shape that is connected with each other near the end of unit area II.
Figure 29 is the amplification plan view of the reticle mask (exposure mask) of use in order to form first corrosion-resisting pattern 8.
This reticle mask 100 is by transparency carrier 101 and is formed on the reticle mask of the attenuation type (half-tone) that the light-shielding pattern 102 on this transparency carrier 101 constituted, and above-mentioned transparency carrier 101 is made of quartz.Wherein, light-shielding pattern 102 is made of the MoSiN that covers the exposure light as KrF laser or ArF laser.
In addition, light-shielding pattern 102 is a plurality of band pattern at interval that are spaced from each other, and it is corresponding with the shape of first corrosion-resisting pattern 8 shown in Figure 18 separately.Wherein, owing to the accompanying drawing reason, in Figure 29, the bearing of trend of light-shielding pattern 102 90 ° have only been rotated from the bearing of trend of first corrosion-resisting pattern 8 (Figure 18 with reference to).
As mentioned above, even in reticle mask 100, form isolated light-shielding pattern 102 because above-mentioned optical adjacent effect, cause a plurality of first corrosion-resisting patterns 8 endways near on be connected in together.
Then, as shown in Figure 4, first corrosion-resisting pattern 8 as mask, is carried out etching to first conducting film 7, thereby be banded the pattern-forming of first conducting film 7.
After this carries out the etching end, remove first corrosion-resisting pattern 8.
Figure 19 removes first corrosion-resisting pattern 8 vertical view afterwards as described above, and the peripheral circuit area I of Fig. 4 of front and unit area II (first cross section) are the sectional views along the A3-A3 line of Figure 19.In addition, second to the 4th cross section of the unit area II of Fig. 4 is equivalent to respectively the B3-B3 line along Figure 19, C3-C3 line, and the sectional view of D3-D3 line.
As shown in figure 19, pattern-forming is that each first conducting film 7 of band shape is identical with first corrosion-resisting pattern 8, is connected with each other near its end.
Then, as shown in Figure 5, the ONO film is formed on whole of the upside of silicon substrate 1 as intermediate insulating film 9.Shown in the broken circle, this ONO film stacks gradually the first silicon oxide film 9f, silicon nitride film 9g and the second silicon oxide film 9h forms, owing to can reduce leakage current and improve dielectric constant, so be suitable as the intermediate insulating film of flash memory.
Figure 20 is the vertical view after this operation finishes, and the peripheral circuit area I of Fig. 5 of front and unit area II (first cross section) are the sectional views along the A4-A4 line of Figure 20.In addition, second to the 4th cross section of the unit area II of Fig. 5 is equivalent to respectively along the sectional view of B4-B4 line, C4-C4 line and the D4-D4 line of Figure 20.
As shown in figure 20, on intermediate insulating film 9, form the step part 9x of first conducting film 7 that reflects substrate.
At this,, need in peripheral circuit area, not form intermediate insulating film 9 because do not form the unit of flash memory at peripheral circuit area I.
Therefore, in ensuing operation, as shown in Figure 6, on intermediate insulating film 9, form second corrosion-resisting pattern 10, this second corrosion-resisting pattern 10 as mask, is removed intermediate insulating film 9 among the peripheral circuit area I by carrying out dry ecthing.Carry out in the etching at this, etching gas uses C 4F 8, Ar, CO and O 2Mist, the tunnel insulator film 15 under the intermediate insulating film 9 is also etched and remove and to remove, thus the surface of exposing the silicon substrate 1 under it.
Figure 21 is the vertical view after this operation finishes, and the peripheral circuit area I of Fig. 6 of front and unit area II (first cross section) are the sectional views along the A5-A5 line of Figure 21.In addition, second to the 4th cross section of the unit area II of Fig. 6 is equivalent to respectively along the sectional view of B5-B5 line, C5-C5 line and the D5-D5 line of Figure 21.
Then, remove after second corrosion-resisting pattern 10, clean the surface of silicon substrate 1 by wet etching process by the oxygen ashing.
Below, describe obtaining the represented cross section structure of Fig. 7 operation before.
At first, adopt 850 ℃ of underlayer temperatures, the oxidizing condition in 40 minutes processing times carries out thermal oxidation to the surface of the silicon substrate 1 that exposes from peripheral circuit area I, will form the heat oxide film of the about 12nm of thickness, and with this heat oxide film as gate insulating film 12.
In addition, adopt SiH 4And PH 3Decompression CVD method as reacting gas on each dielectric film 9,12, forms the polysilicon film of the about 180nm of thickness of in-situ doped (in situ Doping) phosphorus as second conducting film 13.Then,, on this second conducting film 13, form the silicon nitride film of the about 30nm of thickness by plasma CVD method, and with it as antireflection film 14.
Figure 22 is the vertical view after this operation finishes, and the peripheral circuit area I of Fig. 7 of front and unit area II (first cross section) are the sectional views along the A6-A6 line of Figure 22.In addition, second to the 4th cross section of the unit area II of Fig. 7 is equivalent to respectively along the sectional view of B6-B6 line, C6-C6 line and the D1-D1 line of Figure 22.
Then, as shown in Figure 8, prevent to apply photoresist on the film 14 penetrating, and it exposed, develop, with it as the 3rd corrosion-resisting pattern 16.
Figure 23 is formed as described above the 3rd corrosion-resisting pattern 16 vertical view afterwards, and the peripheral circuit area I of Fig. 8 of front and unit area II (first cross section) are the sectional views along the A7-A7 line of Figure 23.In addition, second to the 4th cross section of the unit area II of Fig. 8 is equivalent to respectively along the sectional view of B7-B7 line, C7-C7 line and the D7-D7 line of Figure 23.
As shown in figure 23, the 3rd corrosion-resisting pattern 16 covers peripheral circuit area I, and has the flat shape of the striated suitable with control gate in the II of unit area.
Then, as shown in Figure 9, the 3rd corrosion-resisting pattern 16 as etching mask, is carried out pattern-forming to first, second conducting film 7,13 and intermediate insulating film 9.Carry out this pattern-forming in plasma etch chamber, the etching gas of first, second conducting film 7,13 that is made of polysilicon adopts Cl 2And O 2Mist; The etching gas of the intermediate insulating film 9 that is made of the ONO film adopts CH 3F and O 2Mist.
The result of such pattern-forming stays second conducting film 14 at peripheral circuit area I, simultaneously in the II of unit area, with first, second conducting film 7,13 and intermediate insulating film 9 respectively as floating boom 7a, control gate 13a and intermediate insulating film 9a.
In addition, shown in first cross section of unit area II, illusory control gate 13b is formed on the element separating insulation film 2 of end of unit area II, and the bottom electric conductor 7b that is made of first conducting film 7 is covered by this illusory control gate 13b.
Then, remove the 3rd corrosion-resisting pattern 16.
Figure 24 removes the 3rd corrosion-resisting pattern 16 vertical view afterwards, and the peripheral circuit area I of Fig. 9 of front and unit area II (first cross section) are the sectional views along the A8-A8 line of Figure 24.In addition, second to the 4th cross section of the unit area II of Fig. 9 is equivalent to respectively along the sectional view of B8-B8 line, C8-C8 line and the D8-D8 line of Figure 24.
As shown in figure 24, in the space between each control gate 13a, the intermediate insulating film 9 that forms on first conducting film 7 (Figure 20 reference) is removed by carrying out etching, owing to the intermediate insulating film 9 on the side that is formed on first conducting film 7, to be formed on the thickness direction of substrate 1 with the roughly the same thickness of the thickness of first conducting film 7, therefore this intermediate insulating film 9 is not etched, thereby is left as fence (fence) 9d.
Then, as shown in figure 10, thermal oxidation is carried out in the side separately of floating boom 7a and control gate 13a, thereby at the heat oxide film 17 that forms on their side about the about 10nm of thickness.This heat oxide film 17 also is formed on the side of illusory control gate 13b, and its effect is the retention performance that improves the final flash cell that forms.
Then, as shown in figure 11, by floating boom 7a and control gate 13a are injected as the ion of mask, inject As n type impurity to silicon substrate 1 ion of unit area II -The condition that this ion injects for example is: acceleration energy is 50KeV, and dosage is 6.0 * 10 14Cm -2The result that such ion injects has formed 1n type source/drain extension area 18a on the silicon substrate 1 on the next door of floating boom 7a.
Figure 25 is the vertical view after this operation finishes, and the peripheral circuit area I of Figure 11 of front and unit area II (first cross section) are the sectional views along the A9-A9 line of Figure 25.In addition, second to the 4th cross section of the unit area II of Figure 11 is equivalent to respectively along the sectional view of B9-B9 line, C9-C9 line and the D9-D9 line of Figure 25.
Below, describe obtaining the represented cross section structure of Figure 12 operation before.
At first, carry out thermal oxidation once more, make the thickness of heat oxide film 17 only increase 9.5nm again by side separately to floating boom 7a and control gate 13a.Then, in each area I, form silicon nitride film among the II, make that the thickness on the tabular surface of silicon substrate 1 becomes about 115nm by plasma CVD method.Then, by RIE (Reactive Ion Etching: reactive ion etching) this silicon nitride film is eat-back (Etchback), and it is stayed the side separately of floating boom 7a and control gate 13a as the first insulating properties sidewall 20.
This first side wall 20 also is formed on the side of illusory control gate 13b.
Then, as shown in figure 13, the 4th corrosion-resisting pattern 21 as mask, is carried out etching to second conducting film 13 among the peripheral circuit area I simultaneously, the second not etched and residual conducting film 13 that will be under the 4th corrosion-resisting pattern 21 is as gate electrode 13c.
Figure 26 is the vertical view after this operation finishes, and the peripheral circuit area I of Figure 13 of front and unit area II (first cross section) are the sectional views along the A10-A10 line of Figure 26.In addition, second to the 4th cross section of the unit area II of Figure 13 is equivalent to respectively along the sectional view of B10-B10 line, C10-C10 line and the D10-D10 line of Figure 26.
Then, as shown in figure 14, by with TEOS (Tetraethyl orthosilicate: tetraethoxysilane) as the plasma CVD method of reacting gas, after on whole of the tabular surface of silicon substrate 1, silicon oxide film thickness being formed 100nm, this silicon oxide film is eat-back, form the second insulating properties sidewall 22 in the side separately of the first insulating properties sidewall 20 and gate electrode 23c.
In this eat-back, the part that does not have Be Controlled grid 13a to cover in tunnel insulator film 15 was etched, only residual tunnel insulator film 15 below control gate 13a.
Below, describe obtaining the represented cross section structure of Figure 15 operation before.
At first, the second insulating properties sidewall 22, control gate 13a and gate electrode 13c are carried out ion as mask inject, thus formation n type regions and source 25a and p type regions and source 25b as shown in the figure.Use not shown corrosion-resisting pattern to carry out the n type impurity of this ion injection and the division of p type impurity, behind the ion implanted junction bundle, remove this corrosion-resisting pattern.
In addition, adopt P as n type impurity +Ion, and at acceleration energy 10KeV, dosage 6.0 * 10 15Cm -2Condition under ion inject P +Ion.And, adopt B as p type impurity +Ion, and at acceleration energy 5KeV, dosage 4.0 * 10 15Cm -2Condition under ion inject B +Ion.
Then, by sputtering method, the cobalt film of thickness 8nm and titanium nitride (TiN) film of thickness 10nm are formed on whole successively.Then, be that about 550 ℃, processing time are about 0.5 minute RTA (Rapid Thermal Anneal: short annealing), these films are annealed, and make they and pasc reaction by underlayer temperature.Then, the mixed solution of APM and SPM as etching solution, is removed unreacted cobalt film and titanium nitride film on element separating insulation film 2 grades by wet etching, stay cobalt suicide layer 26 on the top layer of silicon substrate 1.In addition, above-mentioned APM is meant pure water, hydrogen peroxide and NH 4The mixed solution of OH, SPM are meant the mixed solution of sulfuric acid and hydrogen peroxide.
Cobalt suicide layer 26 also be formed on gate electrode 13c above, gate electrode 13c becomes self aligned polycide (salicide) structure thus.
Then, use RTA that cobalt suicide layer 26 is implemented annealing once more, cobalt suicide layer 26 resistance are reduced.Condition as this RTA adopts for example 800 ℃ of underlayer temperatures, 0.5 minute processing time.
By operation so far, form MOS transistor TR at peripheral circuit area I.
On the other hand, in the II of unit area, formed the flash cell FL that constitutes by control gate 13a, intermediate insulating film 9a, floating boom 7a, tunnel insulator film 15 and n type regions and source 25a.
Figure 27 is the vertical view after this operation finishes, and the peripheral circuit area I of Figure 15 of front and unit area II (first cross section) are the sectional views along the A11-A11 line of Figure 27.In addition, second to the 4th cross section of the unit area II of Figure 27 is equivalent to respectively along the sectional view of B11-B11 line, C11-C11 line and the D11-D11 line of Figure 27.
Below, describe obtaining the represented cross section structure of Figure 16 operation before.
At first, by the CVD method, on whole of the upside of silicon substrate 1, form silicon oxide film as interlayer dielectric 27.Then, this interlayer dielectric 27 is carried out by photoetching process interlayer dielectric 27 being carried out pattern-forming after the planarization, form contact hole on the interlayer dielectric 27 of regions and source 25a, 25b top by the CMP method.
Then, by sputtering method, the inner face of this contact hole and above the interlayer dielectric 27 formation on this glued membrane, form tungsten film by the CVD method as the titanium nitride film of glued membrane, with this tungsten film complete filling contact hole.Then, grind and remove the top unnecessary glued membrane and the tungsten film of interlayer dielectric 27 by the CMP method, as 28 dielectric films that in contact hole, stay these of conductivity connector.
In addition, Figure 28 is the vertical view after this operation finishes, and the peripheral circuit area I of Figure 16 of front and unit area II (first cross section) are the sectional views along the A12-A12 line of Figure 28.In addition, second to the 4th cross section of the unit area II of Figure 16 is equivalent to respectively along the sectional view of B1-B1 line, C1-C1 line and the D1-D1 line of Figure 28.
By above operation, finished the basic structure of flash memory.
According to this flash memory, shown in the vertical view of Figure 27, in the space between the control gate 13a in the II of unit area, when the pattern-forming of control gate 13a not etched by intermediate insulating film 9 that the ONO film constituted as fence 9d and by residual.
Though this fence 9d is at physics and unstable, owing to form linearity between control gate 13a, therefore the possibility of peeling off in operation is low.
On the other hand, in the end portion of unit area II, as mentioned before, the flat shape of first conducting film 7 of the optical adjacent effect pattern-forming during because of exposure has radian, and the step part 9x of intermediate insulating film 9 also has circle.Then, under the situation that does not form illusory control gate 13b, this step part 9x is etched and left behind as curvilinear fence.
But so curvilinear fence is more unstable more than the fence 9d of the linearity between the control gate 13a, and the possibility of peeling off in operation is big.
Therefore, in the present example, illusory control gate 13b is set, covers intermediate insulating film 9 below it with this illusory control gate 13b, thereby do not form curvilinear fence at the end of unit area II at the end of unit area II.
This structure for prevent under the illusory control gate 13b fence peel off to a certain degree effect.
But inventor of the present invention finds when investigation, the part between above-mentioned illusory control gate 13b and the genuine control gate 13a, and promptly the fence 9d among the broken circle A of Figure 27 also is very easy to peel off.Supposition thinks that at this moment because the flat shape of the fence 9d of this part is to become curvilinear line of demarcation from linearity, because the combination of so different types of shape, it is very unstable physically that fence 9d becomes.
If fence 9d peels off in operation, fence 9d again on other the part attached to silicon substrate 1 then, thus the pattern that causes this part is bad.Its result, it is bad to produce flash memory, and therefore the problem that semiconductor device yield is low need be used for preventing the new countermeasure of peeling off of the fence 9d of broken circle A.
Inventor of the present invention has expected embodiments of the present invention as described below in view of such problem points.
(2) first execution modes
In the example of above-mentioned preparatory items, when first corrosion-resisting pattern 8 that forms shown in Figure 18, used the reticle mask 100 of illustrated attenuation type among Figure 29 by exposure.
As shown in figure 29, the pattern that light-shielding pattern that this reticle mask 100 had 102 just obtains the similar amplification of design shape of first corrosion-resisting pattern 8 (Figure 18 with reference to) is not considered the distortion of the projection image that produces because of the optical adjacent effect.
Figure 30 be to the flat shape of first corrosion-resisting pattern 8 because of the variation that the out of focus Δ d (μ m) of exposure device takes place, simulate and the vertical view that obtains, the flat shape of described first corrosion-resisting pattern 8 is to use this reticle mask 100 to obtain.
In addition, the pattern concentration among Figure 30 be the expression light-shielding pattern 102 projection image in light intensity.
As shown in figure 30, can know, then be connected to each other together because of the optical adjacent effect causes the first adjacent corrosion-resisting pattern 8 if out of focus Δ d becomes more than 0.4.
Figure 31 is the amplification plan view of the reticle mask 103 that works out for the distortion that reduces so caused projection image of optical adjacent effect.
In this reticle mask 103, near terminal two long limit 102a of light-shielding pattern 102 rib (edge) 102b only is set respectively.Below, the fore-end of this rib 102b is called narrow width portion 104.
Figure 32 is the variation that the flat shape of first corrosion-resisting pattern 8 is taken place because of the out of focus Δ d of exposure device, the vertical view of simulating and obtaining, the flat shape of described first corrosion-resisting pattern 8 are to use the reticle mask 103 that is formed with narrow width portion 104 to obtain.
In Figure 32, be that first corrosion-resisting pattern 8 width that joins each other is narrower than its width of Figure 30 of front under 0.4 the situation at out of focus Δ d, thereby the distortion of first corrosion-resisting pattern 8 has obtained improvement to a certain degree.But, be that this point that links together each other of first corrosion-resisting pattern 8 does not change under 0.4 the situation at out of focus Δ d.
Figure 33 is the amplification plan view of the reticle mask 105 that works out for the distortion that further reduces the caused projection image of optical adjacent effect.
In this reticle mask 105, the quantity that is arranged on the rib 102b on the long limit 102a of light-shielding pattern 102 increases by one again, thereby has formed two the narrow width portion 104 that adterminal width narrows down successively.
In addition, though to De Ju From D as shown in figure 33 1To D 6Value do not do special qualification, but the value below having used in the present embodiment:
D 1＝400nm
D 2＝10nm
D 3＝10nm
D 4＝120nm
D 5＝150nm
D 6＝200nm
Wherein, these values are that the value of the projection image on the silicon substrate of light-shielding pattern 102 does not take place under the situation of distortion of the picture that produces because of the optical adjacent effect in hypothesis.The value of the reality of the light-shielding pattern 102 in the reticle mask 105 is products of inverse of the minification (1/4 times) of these values and exposure device.
Figure 34 is the variation that the flat shape of this first corrosion-resisting pattern 8 is taken place because of the out of focus Δ d of exposure device, the vertical view of simulating and obtaining, the flat shape of described first corrosion-resisting pattern 8 are to use the reticle mask 105 that is formed with two narrow width portions 104 to obtain.
As shown in figure 34, if use above-mentioned reticle mask 105, then under out of focus Δ d was 0.4 situation, first corrosion-resisting pattern 8 became each other and does not connect together, therefore can make out of focus (focus) become big, till first corrosion-resisting pattern 8 connects together each other.
Figure 35 has put down in writing in the lump, use the analog result of flat shape of reticle mask illustrated in the preparatory items 100 (comparative example) and above-mentioned reticle mask 105 resulting first corrosion-resisting patterns 8 and SEM (the Scanning Electron Microscope: scanning electron microscopy) as figure of actual corrosion-resisting pattern 108 respectively.In Figure 35, what the left side was represented is comparative example, and what the right side was represented is present embodiment.
As shown in figure 35, in the SEM of comparative example picture, expand in the same manner during with simulation for the first end parts of first corrosion-resisting pattern 8, in the SEM picture under the situation of having used the reticle mask 105 that is provided with two-layer narrow width portion 104, the expansion of the first end parts of first corrosion-resisting pattern 8 is inhibited.
Figure 36 schematically shows in order, focus is with reticle mask illustrated in the preparatory items 100 (left side), only be provided with the reticle mask 103 (central authorities) of one deck narrow width portion 104, and the vertical view that is provided with the appearance that the order of the reticle mask 105 (right side) of two-layer narrow width portion 104 amplifies.In addition, in Figure 36, three top figure expression theoretic face profiles (layout), three following actual formed face profiles of figure expression.
Illustrated as reference Figure 33 and Figure 34, the reticle mask 105 that is provided with two narrow width portions 104 is effectively for the focus that is amplified in when forming first corrosion-resisting pattern 8, also uses this reticle mask 105 in the illustrated below execution mode.
Yet, by using EB (Electron Beam: the photoetching carried out of describing device electron beam), to being formed on the photomask that constitutes by MoSiN on the transparency carrier 101 that constitutes by quartz, carry out pattern-forming, thereby form the light-shielding pattern 102 of this reticle mask 105.
In the EB describing device, by electron beam deflection orthogonal x direction and y direction in the plane of transparency carrier 101 are drawn, to shown in the light-shielding pattern 102 as shown in Figure 33, easily the pattern that is made of profile the straight line that extends to x direction and y direction is drawn.
To this, patent documentation 4 as previously described, under the situation at oblique angle of cutting away banded exposing patterns, need fine to adjust deflection amount on one side to x direction and y direction, use electron beam to draw oblique part on one side, therefore can cause draw more time-consuming, and then the problem that rises of the cost of manufacture of reticle mask.
At this, as OPC for the light-shielding pattern 102 of the reticle mask 105 of Figure 33, the automatic OPC of the shape correction that comprising uses a computer carries out light-shielding pattern 102 and carry out the manual OPC of this shape correction by the people.
In the present embodiment, for narrow width portion 104 is set, can use automatic APC and manual any one among the APC on light-shielding pattern 102.
But, in existing technology,, be difficult to be suitable for automatic APC for repeat patterns as the band shape of light-shielding pattern 102.This is because in automatic APC, has used by a pair of OPC table that constitutes of the live width correcting value of pattern spacing and pattern, and for resembling the such repeat patterns of light-shielding pattern 102, has been difficult to make this OPC table.
Therefore, present situation is to use manual OPC that narrow width portion 104 is set on light-shielding pattern 102.
But, under the situation of technological progress, can certainly narrow width portion 104 be set from now on by automatic OPC.
(3) second execution modes
Figure 37 to Figure 56 is the sectional view in the manufacture process of semiconductor device of second execution mode of the present invention, and Figure 57 to Figure 68 is its vertical view.In the present embodiment, adopting grid length is the design rule of 0.13 μ m, and (Field Programmable Gate Array: field programmable gate array) etc. logic is mixed and carried internal memory to make FPGA.
At first, as shown in figure 50, on the silicon substrate 50 of having delimited peripheral circuit area I and unit area II, form the element separating tank 50a of STI (Shallow Trench Isolation: shallow trench isolation from) usefulness, in this groove 50a, form silica as element separating insulation film 51.In addition, also can replace STI, use LOCOS (Local Oxidation of Silicon) method to form element separating insulation film 51.
In addition, in addition, the peripheral circuit area I of silicon substrate 50 also is subdivided into high voltage transistor and forms area I H, middle voltage transistor forms area I M, and low-voltag transistor forms area I L
Figure 57 is the vertical view after this operation finishes.Then, first to the 3rd cross section of the unit area II among Figure 37 of front is equivalent to respectively E1-E1 line, the F1-F1 line along Figure 57, the sectional view of G1-G1 line.In addition, the sectional view of the peripheral circuit area I among Figure 37 is the sectional view along the H1-H1 line of Figure 57.Wherein, finally make 10 MOS transistor in peripheral circuit area I, but become numerous and diverse for fear of figure, in Figure 37 and vertical view afterwards, only the peripheral circuit area I of the part of a MOS transistor is made in expression.
Shown in Figure 57, the active region 50b of the silicon substrate 50 that is surrounded by element separating insulation film 51 forms in active region II and leaves band shape at interval.
Below, describe obtaining the represented cross section structure of Figure 38 operation before.
At first, the whole face to silicon substrate 50 carries out the sacrifice dielectric film (not shown) that thermal oxidation forms the about 15nm of thickness.
Then, by the P of ion implantation with n type impurity +Ion is injected in the silicon substrate 50, forms a n trap 53 in the deep of silicon substrate 50.Though the condition of injecting for this ion does not have special qualification, the acceleration energy 2MeV of Cai Yonging in the present embodiment, dosage 2 * 10 13Cm -2
Then, by the ion injection of step 2, inject the B of p type impurity to silicon substrate 50 +Ion forms first to the 3rd p trap 54 to 56.The condition that this ion injects is, for example the acceleration energy of first step is 420KeV, and dosage is 1.4 * 10 13Cm -2, the acceleration energy of second step is 100KeV, dosage is 3.6 * 10 12Cm -2
Form area I at high voltage transistor HIn, forming high n type MOS transistor and the low n type MOS transistor of threshold voltage of threshold voltage, the latter's threshold voltage is controlled by an above-mentioned p trap 54.
In addition, at acceleration energy 100KeV, dosage 4.0 * 10 12Cm -2Condition under, by the B of ion implantation with p type impurity +Ion is injected in the silicon substrate 50, thereby forms the 4th to the 6th p trap 57 to 59.
In these traps, the 4th p trap 57 is that the back is formed area I at high voltage transistor HThe threshold voltage of the n type MOS transistor that the middle threshold voltage that forms is high is controlled.On the other hand, the five, the six p trap 58,59 has the back in middle voltage transistor formation area I MForm area I with low-voltag transistor LThe middle passage as n type MOS transistor that forms stops the function of (channel stop) layer.
Then, by the ion injection of step 2, inject the P of n type impurity to silicon substrate 50 +Ion forms second to the 4th n trap 60 to 62.Inject at this ion, first step has adopted acceleration energy 600KeV, dosage 1.5 * 10 13Cm -2Condition, second step has adopted acceleration energy 240KeV, dosage 9.0 * 10 11Cm -2Condition.
Form area I at high voltage transistor HIn, though be formed with the low p type MOS transistor of high p type MOS transistor of threshold voltage and threshold voltage, the latter's threshold voltage is to control by the 2nd above-mentioned p trap 60.
Then, at acceleration energy 240KeV, dosage 3.6 * 10 12Cm -2Condition under, by the P of ion implantation with n type impurity +Ion is injected in the silicon substrate 50, thereby forms the 5th to the 7th n trap 63 to 65.
In these traps, 63 pairs of back of the 5th n trap form area I at high voltage transistor HThe threshold voltage of the high p type MOS transistor of the middle threshold voltage that forms is controlled.On the other hand, the six, the seven n trap 64,65 has the back in middle voltage transistor formation area I MForm area I with low-voltag transistor LThe passage as p type MOS transistor that forms stops the function of layer.
Then, by the B of ion implantation with p type impurity +Ion is injected in the silicon substrate 50, is used for controlling the threshold voltage of back at the formed flash cell of unit area II thereby form 66, the one p type diffusion of impurities zones 66, a p type diffusion of impurities zone.The condition of injecting as this ion for example adopts acceleration energy 40KeV, dosage 6 * 10 13Cm -2Condition.
In addition, inject at above-mentioned various ions, at first the sacrifice dielectric film of Xing Chenging is used as filter membrane, divides impurity according to the not shown corrosion-resisting pattern on this sacrifice dielectric film simultaneously, removes this corrosion-resisting pattern after each ion implanted junction bundle.
Then, remove the sacrifice dielectric film by the wet etching that uses fluorspar acid solution, the cleaning of silicon substrate 50 is showed out, for example 900 ℃ to 1050 ℃ of underlayer temperatures, under the heat-treat condition in 30 minutes processing times, on the surface of silicon substrate 50, form the heat oxide film of about 10nm thickness, and with it as tunnel insulator film 52.
Below, describe obtaining the represented cross section structure of Figure 39 operation before.
At first, by with SiH 4And PH 3As the decompression CVD method of reacting gas, on tunnel insulator film 52, form the in-situ doped polysilicon film of phosphorus of thickness for about 90nm, and with it as first conducting film 67.
Then, the photoresist of coating eurymeric on this first conducting film 67.
Then, use reticle mask illustrated among Figure 33 of first execution mode 105, in the exposure device of stepping exposure device (stepper) etc., above-mentioned photoresist is exposed.In this exposure process, the focusing of exposure device is in the out of focus scope that the projection image of the light-shielding pattern 102 that makes the reticle mask 105 shown in Figure 33 does not link together each other.
Then, photoresist is developed, thus formation first corrosion-resisting pattern 68 as shown in the figure.
Figure 58 is the vertical view that is formed as described above after first corrosion-resisting pattern 68, and first to the 3rd cross section of the unit area II among Figure 39 of front is equivalent to respectively E2-E2 line, the F2-F2 line along Figure 58, the cross section of G2-G2 line.In addition, the sectional view of the peripheral circuit area I among Figure 39 is the sectional view along the H2-H2 line of Figure 58.
As shown in Figure 33 because mask 105 can suppress reducing of the focus that causes because of the optical adjacent effect, even therefore in the light operation focusing of exposure device be offset a little, also can prevent to connect together each other.Its result shown in Figure 58, uses each of first corrosion-resisting pattern 68 of a plurality of band shapes that this reticle mask 105 forms can be because of the optical adjacent effect does not connect together, but formation with being separated from each other.
In addition, the bearing of trend of first corrosion-resisting pattern 68 of this band shape is identical with the orthogonal direction of word line (Word Line).
Then, as shown in figure 40, the first above-mentioned corrosion-resisting pattern 68 as mask, is carried out etching to first conducting film 67 simultaneously, thereby first conducting film 67 is carried out pattern-forming, and remove first conducting film 67 from peripheral circuit area I.
Then, remove first corrosion-resisting pattern 68
Figure 59 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 40 of front is equivalent to respectively E3-E3 line, the F3-F3 line along Figure 59, the cross section of G3-G3 line.In addition, the sectional view of the peripheral circuit area I among Figure 40 is the sectional view along the H3-H3 line of Figure 59.
Shown in Figure 59, as mentioned above, as mask, first conducting film 67 among the II of unit area also is separated from each other first corrosion-resisting pattern 68 by will being separated from each other (Figure 58 with reference to), becomes a plurality of band shapes of extending along the orthogonal direction of word line.
Below, describe obtaining the represented cross section structure of Figure 41 operation before.
At first, on first conducting film 67 and on the tunnel insulator film 52 among the peripheral circuit area I, use decompression CVD method to form silicon oxide film and silicon nitride film in order, thickness is respectively 5nm, 8nm.In addition, at Ar and O 2The mist gaseous environment in, about 950 ℃ at underlayer temperature, under the heating time about 90 minutes heat-treat condition, oxidation is carried out on the surface of silicon nitride film, form the silicon oxide film of about 6nm on this surface.Thus, with the first silicon oxide film 69f, silicon nitride film 69g, and the second silicon oxide film 69h stacks gradually the ONO film that forms and is formed on whole as intermediate insulating film 69.
In addition, the heat treatment during the illustrated formation tunnel insulator film 52 of the heat treatment when the silicon nitride film in the ONO film is carried out oxidation and Figure 38, the impurity that forms in the trap on the silicon substrate 50 spreads, thereby makes its distribution broadness (broad) that becomes.
Then, with each dielectric film 52,69 as filter membrane the time, by the B of ion implantation with p type impurity +Ion is injected in the silicon substrate 60, thereby forms area I at middle voltage transistor MIn be formed for regulating the 2nd p type diffusion of impurities zone 82 of the threshold voltage of n type MOS transistor.Though the condition of injecting for this ion does not have special qualification, adopts acceleration energy 15KeV in the present embodiment, dosage 7.0 * 10 12Cm -2Condition.
Then, by the ion of each dielectric film 52,69 as filter membrane injected, at acceleration energy 150KeV, dosage 6.0 * 10 12Cm -2Condition under, be injected in the silicon substrate 50 by the As-ion of ion implantation n type impurity, form area I at middle voltage transistor MIn be formed for regulating a n type diffusion of impurities zone 83 of the threshold voltage of p type MOS transistor.
Then, at acceleration energy 35KeV, dosage 4.5 * 10 12Cm -2Condition under, by the B of ion implantation with p type impurity +Ion is injected in the silicon substrate 50, forms the 3rd p type diffusion of impurities zone 84.Form two n type MOS transistor that form high threshold voltage and low threshold voltage among the area I L at low-voltag transistor afterwards, with two p type MOS transistor of high threshold voltage and low threshold voltage, but the threshold voltage of the n type MOS transistor of high threshold voltage wherein is subjected to the control in the 3rd above-mentioned p type diffusion of impurities zone 84.
Then, be injected in the silicon substrate 50, form 85, the two n type diffusion of impurities zones 85, the 2nd n type diffusion of impurities zone and be used to regulate low-voltag transistor formation area I by the As-ion of ion implantation with n type impurity LIn the threshold voltage of p type MOS transistor of high threshold voltage.The condition of injecting as this ion adopts for example acceleration energy 150KeV, dosage 2.0 * 10 12Cm -2Condition.
In addition, the not shown corrosion-resisting pattern that each diffusion zone that above-mentioned threshold value adjustment is used is formed on the intermediate insulating film 69 separates, and removes this corrosion-resisting pattern again after forming each trap.
Figure 60 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 41 of front is equivalent to respectively E4-E4 line, the F4-F4 line along Figure 60, the cross section of G4-G4 line.In addition, the sectional view of the peripheral circuit area I among Figure 41 is the sectional view along the H4-H4 line of Figure 60.
By the end of present operation, as shown in figure 41, the formation of diffusion zone 82 to 85 that is used for controlling the transistorized threshold voltage of peripheral circuit area I finishes, therefore injecting the diffusion zone 82 to 85 o'clock that forms these by ion, no longer need in the operation of dielectric film 52,69 after this as the peripheral circuit area I of filter membrane.
Therefore, in ensuing operation shown in Figure 42,, on intermediate insulating film 69, form second corrosion-resisting pattern 70 of capping unit area I I in order optionally to remove each dielectric film 52,69 of this peripheral circuit area I.
Then, with this second corrosion-resisting pattern 70 as in the mask, by with C 4F 8, Ar, CO and O 2Mist as the plasma etching of etching gas, optionally etching is to each dielectric film 52,69 of peripheral circuit area I and remove, thus the surface of exposing the silicon substrate 50 in peripheral circuit area I.
Figure 61 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 42 of front is equivalent to respectively E5-E5 line, the F5-F5 along Figure 61
The cross section of line, G5-G5 line.In addition, the sectional view of the peripheral circuit area I among Figure 42 is the sectional view along the H5-H5 line of Figure 61.
Then, remove after second corrosion-resisting pattern 70, clean the surface of silicon substrate 50 by wet process by the oxygen ashing.
Below, describe obtaining the represented cross section structure of Figure 43 operation before.
At first, adopting underlayer temperature is 850 ℃, and the processing time is 40 minutes a oxidizing condition, and thermal oxidation is carried out on the surface of the silicon substrate 50 that exposes among the peripheral circuit area I, and the thickness of heat oxide film is formed about 12nm.Then, form area I at unit area II and high voltage transistor HThe not shown corrosion-resisting pattern of last formation as mask, is removed this corrosion-resisting pattern in middle voltage transistor formation area I by etching MAnd low-voltag transistor forms area I LThe middle above-mentioned heat oxide film that forms only forms area I at high voltage transistor HStay this heat oxide film.
In addition, to forming area I at middle voltage transistor MForm area I with low-voltag transistor LIn the surface of the silicon substrate 50 that exposes carry out thermal oxidation, in these zone, heat oxide film is formed the thickness of about 7.0nm.For example adopt 800 ℃ to 900 ℃ of underlayer temperatures, the condition that the processing time is about 10 minutes as this oxidizing condition.Then, form area I at unit area II, high voltage transistor HAnd middle voltage transistor forms area I MUpward form not shown corrosion-resisting pattern, and with it as mask, by above-mentioned heat oxide film is carried out etching, form area I from low-voltag transistor LRemove this heat oxide film, form area I thereby expose low-voltag transistor LIn the surface of silicon substrate 50.Then, remove corrosion-resisting pattern as mask.
Then, adopt about 700 ℃ to 800 ℃ of underlayer temperature in the oxygen gas environment, the oxidizing condition that the processing time is about 5 minutes forms area I at low-voltag transistor LIn form heat oxide film on the surface of the silicon substrate 50 that exposes.Though be not particularly limited the thickness of this heat oxide film, be made as about 2.2nm in the present embodiment.
By above-mentioned three times thermal oxidation, form area I at high voltage transistor H, middle voltage transistor forms area I MAnd low-voltag transistor forms area I LIn, form by final thickness and be respectively the gate insulating film 71 that the heat oxide film of 16nm, 7.5nm and 2.2nm constitutes.
Then, as shown in figure 44, adopt SiH 4And PH 3As the decompression CVD method of reacting gas, on each dielectric film 69,71, be formed on the polysilicon film of the about 180nm of thickness of in-situ doped phosphorus as second conducting film 74.In addition,, on this second conducting film 74, form the silicon nitride film of the about 30nm of thickness by plasma CVD method, and with it as antireflection film 75.
Figure 62 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 44 of front is equivalent to respectively E6-E6 line, the F6-F6 line along Figure 61, the cross section of G6-G6 line.In addition, the sectional view of the peripheral circuit area I among Figure 44 is the sectional view along the H6-H6 line of Figure 62.
But, become numerous and diverse in order to prevent figure, in Figure 62, omitted antireflection film 75.
Shown in Figure 62, on intermediate insulating film 69, formed step part 69x, this step part 69x has reflected first conducting film 67 of substrate.
Then, as shown in figure 45, on antireflection film 75, apply photoresist, after it is exposed, develops, with it as the 3rd corrosion-resisting pattern 76.
Figure 63 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 45 of front is equivalent to respectively E7-E7 line, the F7-F7 line along Figure 63, the cross section of G7-G7 line.In addition, the sectional view of the peripheral circuit area I among Figure 45 is the sectional view along the H7-H7 line of Figure 63.
Shown in Figure 63, the 3rd corrosion-resisting pattern 76 has the word line shape in the II of unit area.
Then, as shown in figure 46, by the 3rd corrosion-resisting pattern 76 is used as etching mask, to first, second conducting film 67,74, and intermediate insulating film 69 carries out pattern-forming.
The result of such pattern-forming stays in peripheral circuit area I in second conducting film 74, and first, second conducting film 67,74 in the II of unit area becomes floating boom 67a and control gate 74a respectively.
In addition, on the element separating insulation film 51 in the end of unit area II, form illusory control gate (illusory conductive pattern) 74b that constitutes by second conducting film 74 of pattern-forming.Then, in the end of unit area II not by pattern-forming and the section 69c of residual intermediate insulating film 69 and covered by above-mentioned illusory control gate 74b by the bottom conductor pattern 67b that is constituted by first conducting film 67 of pattern-forming.
In the end of unit area II, form and such stack gradually the structure 98 that forms by bottom conductor pattern 67b, section 69c and illusory control gate 74b.
Above-mentioned pattern-forming for example in plasma etch chamber the etching by three steps carry out.
In first etching step, with Cl 2And O 2Mist as etching gas, remove the part that can not become control gate 74a and illusory control gate 74b in second conducting film 74 by etching optionally.
In second etching step, with CH 3F and O 2Mist as etching gas, remove the intermediate insulating film 69 that forms above first conducting film 67 between control gate 74a and illusory control gate 74b by etching optionally.
Then, in the 3rd etching step, with Cl 2And O 2Mist as etching gas (etchant), remove first conducting film 67 between control gate 74a and the illusory control gate 74b by etching optionally.
After this pattern-forming finished, the 3rd corrosion-resisting pattern 76 was removed.
Figure 64 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 46 of front is equivalent to respectively E8-E8 line, the F8-F8 line along Figure 64, the cross section of G8-G8 line.In addition, the sectional view of the peripheral circuit area I among Figure 46 is the sectional view along the H8-H8 line of Figure 64.
Shown in Figure 64, control gate 74a and illusory control gate 74b are the band shapes of extending in parallel to each other with the vertical direction of the bearing of trend of active region 50b (Figure 57 with reference to).
In addition, in the space between each control gate 74a, in previously described second etching step, remove the intermediate insulating film 69 that on first conducting film 67 (Figure 63 with reference to), forms by etching.
But, because forming, the intermediate insulating film 69 that forms in the side of first conducting film 67 has the thickness roughly the same with the thickness of first conducting film 67 on the thickness direction of silicon substrate 50, therefore it is not etched in second etching step, thereby as fence 69d and by residual.
In addition, in second etching step with CH 3F and O 2Mist as etching gas, this point that the etch-rate of intermediate insulating film 69 is slower than the etch-rate of first conducting film 67 also becomes and encourages the essential factor that fence 69d forms.
On element separating insulation film 51, this fence 69d extends to bottom conductive pattern 67b from the side of floating boom 67a along active region 50b (Figure 57 reference).
Then, separate band shape because first conducting film 67 before the pattern-forming is, the previously described bottom conductor pattern 67b that is formed on the end of unit area II becomes the island that is separated from each other by this pattern-forming.In addition, the section 69c of previously described intermediate insulating film 69 forms the parallel ribbon with control gate 74a, is shared by each of the bottom conductor pattern 67b of island.
In addition, under situation about seeing from top to bottom, illusory control gate 74b forms in the mode that comprises above-mentioned bottom conductor pattern 67b.
Figure 69 is the amplification plan view of the position relation when design between the light-shielding pattern 102 of the illustrated reticle mask 105 of expression Figure 33 and the illusory control gate 74b.
In addition, in Figure 69, be more readily understood in order to make design profile, light-shielding pattern 102 and illusory control gate 74b are documented on the same drawing, but in the equipment of reality, the light-shielding pattern 102 of Figure 69 is corresponding with first conducting film 67 (Figure 59 reference) behind the pattern-forming.
Shown in Figure 69, in the present embodiment, illusory control gate 74b is formed on the crossing position with the narrow width portion 104 of light-shielding pattern 102 by the long limit 74c of control gate 74a one side.
In addition, De Ju From D shown in Figure 69 4, D 5The value illustrated with Figure 33 is identical.On the other hand, Figure 69 De Ju From D7 to D9 for example has following value:
D 7＝710nm
D 8＝200nm
D 9＝450nm
Then, as shown in figure 47, by thermal oxidation being carried out in the side separately of floating boom 67a and control gate 74a, the heat oxide film 77 about their the about 10nm of side formation thickness.The effect of this heat oxide film 77 is the retention performances that improve the final flash cell that forms.
This heat oxide film 77 also is formed on the side of illusory control gate 74b and bottom conductor pattern 67b.
Then, as shown in figure 48, form the not shown corrosion-resisting pattern that covers peripheral circuit area I, this corrosion-resisting pattern will be injected silicon substrate 50 as mask as the As-of n type impurity by ion implantation.Though be not particularly limited the condition that this ion injects, adopt for example acceleration energy 50KeV in the present embodiment, dosage 6.0 * 10 14Cm -2Condition.The result that such ion injects is on the silicon substrate 50 on the next door of floating boom 67a, has formed a n type source/drain extension area 78b.
Then, remove above-mentioned corrosion-resisting pattern.
Figure 65 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 48 of front is equivalent to respectively E9-E9 line, the F9-F9 line along Figure 65, the cross section of G9-G9 line.In addition, the sectional view of the peripheral circuit area I among Figure 48 is the sectional view along the H9-H9 line of Figure 65.
Below, describe obtaining the represented cross section structure of Figure 49 operation before.
At first, once more thermal oxidation is carried out in the side separately of floating boom 67a and control gate 74a, make the thickness of heat oxide film 77 only increase 9.5nm again.Then,, in each area I, II, form silicon nitride film, and to make the thickness of this silicon nitride film on the tabular surface of silicon substrate 50 be about 115nm by plasma CVD method.Then, this silicon nitride film is eat-back, it is stayed the side separately of illusory control gate 74b and floating boom 67a as the first insulating properties sidewall 79 by RIE.
Then, as shown in figure 50, whole of the upside of silicon substrate 50 is gone up the coating photoresist, and it is exposed, develops, thereby is formed on the 4th corrosion-resisting pattern 80 of the flat shape that has the gate electrode shape among the peripheral circuit area I.
Then, shown in Figure 51,, make second conducting film 74 of peripheral circuit area I become first to the tenth gate electrode 74e to 74n that peripheral transistor is used by with of the etching of the 4th corrosion-resisting pattern 80 as mask.Such etching is by for example with Cl 2And O 2Mist carry out as the RIE of etching gas.
Figure 66 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 51 of front is equivalent to respectively E10-E10 line, the F10-F10 line along Figure 66, the cross section of G10-G10 line.In addition, the sectional view of the peripheral circuit area I among Figure 51 is the sectional view along the H10-H10 line of Figure 66.
Then, remove the 4th corrosion-resisting pattern 80.
Then, shown in Figure 52, first to the ten gate electrode 74e to 74n is being injected into silicon substrate 50 by ion implantation with the n type impurity of As or P etc. in as mask, thereby is forming second to the 8th n type source/drain extension area 78c to 78g as shown in the figure.In addition, be injected in the silicon substrate 50 by the p type impurity of ion implantation in the same manner therewith, form first to the 5th such p type source/drain extension area 78h to 781 of diagram BF2 etc.In addition, the n type impurity that above-mentioned ion injects and the division of p type impurity are to use not shown corrosion-resisting pattern to carry out, and remove this corrosion-resisting pattern behind the ion implanted junction bundle.
Below, describe obtaining the represented cross section structure of Figure 53 operation before.
At first, by TEOS being used as the plasma CVD method of reacting gas, on whole, form silicon oxide film, and make the thickness of this silicon oxide film on the tabular surface of silicon substrate 50 become 100nm, then, this silicon oxide film is eat-back, form the second insulating properties sidewall 81 in the side of the first insulating properties sidewall 79 and first to the ten gate electrode 74e to 74n.
In addition, in this eat-back, the second insulating properties sidewall 81 became mask, and tunnel insulator film 52 is carried out pattern-forming, and this tunnel insulator film 52 is only stayed the below of floating boom 67a.
In addition, in peripheral circuit area I, remove the part that is not covered in the gate insulating film 71 by first to the ten gate electrode 74e to 74n.
Then, shown in Figure 54, by the second insulating properties sidewall 81, control gate 74a and first to the ten gate electrode 74e to 74n are injected as the ion of mask, form as shown in the figure first to the 6th n type regions and source 90b to 90g and first to the 5th p type regions and source 90h to 901.The n type impurity that this ion injects and the division of p type impurity are to use not shown corrosion-resisting pattern to carry out, and remove this corrosion-resisting pattern behind the ion implanted junction bundle.In addition, the condition of injecting for this ion does not limit especially yet.In the present embodiment, adopt P as n type impurity +Ion, with acceleration energy 10KeV, dosage 6.0 * 10 15Cm -2Condition carry out ion and inject.In addition, adopt B as p type impurity +Ion, with acceleration energy 5KeV, dosage 4.0 * 10 15Cm -2Condition carry out ion and inject.In addition, inject at this ion, with B +Iontophoresis to the gate electrode of p type MOS transistor (the the three, the four, the six, the nine, the tenth gate electrode 74g, 74h, 74j, 74m, 74n) in, the conductivity that makes these gate electrodes is the p type.
By operation so far, form area I at high voltage transistor respectively HForm area I with low-voltag transistor LOn formed the n type MOS transistor TR of the logical circuit that constitutes sense amplifier etc. n(Low Vth), TR n(High Vth) and p type MOS transistor TR p(Low Vth), TR p(High Vth).Each transistorized Low Vth and High Vth represent the height of this transistorized threshold voltage.
Like this, if transistor and the low transistor that threshold voltage is high mixes, by using the low transistor of threshold voltage, can make the circuit high speed motion, and when waiting for (stand by), switch to the state of pass (OFF) by the transistor that this threshold voltage is low, and use the high transistor of threshold voltage, the leakage current that takes place in can suppressing to wait for.
In addition, in above-mentioned transistor, high voltage transistor forms area I HIn what form is to be the high voltage transistor of 5V to the voltage that gate electrode adds, form area I at low-voltag transistor LIn what form is the low-voltag transistor of 1.2V.
Then, form area I at middle voltage transistor MIn, being formed as shown the voltage that is added on the gate electrode all is the n type MOS transistor TR of 3.3V nWith p type MOS transistor TR p
On the other hand, in the II of unit area, form the flash cell FL that constitutes by control gate 74a, intermediate insulating film 69, floating boom 67a, tunnel insulator film 52 and a n type regions and source 90b.
In the present embodiment, 10 the MOS transistor that forms in peripheral circuit area I constitutes the primary module of logical circuit.Then, by these transistors, the input and output among the control unit area I I.
Figure 67 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 54 of front is equivalent to respectively E11-E11 line, the F11-F11 line along Figure 67, the cross section of G11-G11 line.In addition, the sectional view of the peripheral circuit area I among Figure 54 is the sectional view along the H11-H11 line of Figure 67.
Below, describe obtaining the represented cross section structure of Figure 55 operation before.
At first, on whole of the upside of silicon substrate 50,, form the cobalt film of thickness 8nm and titanium nitride (TiN) film of thickness 10nm successively by sputtering method.Then, about 550 ℃ by underlayer temperature, the RTA (Rapid Thermal Anneal) that the processing time is about 0.5 minute anneals and itself and silicon is reacted these films.Then, the mixed solution that uses APM and SPM is as etching solution, removes unreacted cobalt film and titanium nitride film on element separating insulation film 51 grades by wet etching, stays cobalt suicide layer 92 on the top layer of silicon substrate 50.In addition, above-mentioned APM is meant pure water, hydrogen peroxide and NH 4The mixed solution of OH, SPM are meant the mixed solution of sulfuric acid and hydrogen peroxide.
Cobalt suicide layer 92 also be formed on first to the ten gate electrode 74e to 74n above, each gate electrode 74e to 74n becomes the self aligned polycide structure thus.
Then, cobalt suicide layer 92 is implemented annealing by RTA once more, thereby realize the low resistanceization of cobalt suicide layer 92.Though be not particularly limited the condition of this RTA, underlayer temperature is made as 800 ℃ in the present embodiment, and the processing time was made as 0.5 minute.
In addition, replace cobalt suicide layer 92, also can form other refractory metal silicide layer, for example nickel silicide layer.
Below, describe obtaining the represented cross section structure of Figure 56 operation before.
At first,, on whole of the upside of silicon substrate 50, form the silicon nitride film of thickness for about 70nm by the CVD method, and with it as etching block film 93.Then, by the CVD method, on this etching block film 93, form silicon oxide film as interlayer dielectric 94.
Then, above CMP (Chemical Mechanical Polishing) method grinding interlayer dielectric 94, make its planarization.The result of planarization is that the thickness that etching block film 93 and interlayer dielectric 94 add together is about 600nm on the tabular surface of silicon substrate 50.Then, interlayer dielectric 94 and etching block film 93 are carried out pattern-forming, be formed on the contact hole on each regions and source 90b to 901 by photoetching.
In this photoetching, use etching block film 93 as block film, optionally interlayer dielectric 94 is carried out after etched first etching step, changing etching gas and cobalt suicide layer 92 (Figure 52 with reference to) is optionally carried out etching to etching block film 93 in as second etching step of block film.
In addition,,, form Ti film and TiN film successively by sputtering method at the inner face of above-mentioned contact hole with above the interlayer dielectric 94, and with it as glued membrane.Then,, on this glued membrane, form W (tungsten) film by using the CVD method of tungsten fluoride as reacting gas, thus filling contact hole fully.Then, remove unnecessary W film and the glued membrane that on interlayer dielectric 94, forms by the CMP method, as 96 of conductivity connectors stay each contact hole in part.
Figure 68 is the vertical view after this operation finishes, and first to the 3rd cross section of the unit area II among Figure 56 of front is equivalent to respectively E12-E12 line, the F12-F12 line along Figure 68, the cross section of G12-G12 line.In addition, the sectional view of the peripheral circuit area I among Figure 56 is the sectional view along the H12-H12 line of Figure 68.
Then, be transferred to and be formed on the operation that interlayer dielectric 94 (Figure 56 reference) is gone up the metal wiring of ground floor, omit its detailed content.Like this in the metal wiring of Xing Chenging, the distribution that is electrically connected with two the n type source/drain 90b of flash cell FL is for example as the bit line (BL) of NAND type flash memory and source electrode line (SL) and work respectively.
As mentioned above, finished the basic structure of the semiconductor device of present embodiment.
According to above-mentioned execution mode, in order to form first corrosion-resisting pattern 68 shown in Figure 58, use the illustrated reticle mask 105 of Figure 33 with flat shape, photoresist is exposed.
Illustrated as Figure 33, because this reticle mask 105 has two the narrow width portion 104 that narrows down successively towards the end direction width, the deflection of the projection image of the light-shielding pattern 102 that produces because of the optical adjacent effect is diminished, can increase the focus in the exposure device, promptly increase focus bias, this focus bias is not connect mutually each other by projection image, isolated mutually obtaining.
Therefore, shown in Figure 58, be offset slightly even focus in the above-mentioned exposure device, a plurality of first corrosion-resisting patterns 68 that use this reticle mask 105 and form form with the state that is separated from each other, and first conducting film 67 (Figure 59 reference) that this first corrosion-resisting pattern 68 is carried out pattern-forming as mask also is separated from each other.
Its result, shown in Figure 65, the part between illusory control gate 74b and the genuine control gate 13a is promptly among the broken circle B of Figure 65, the flat shape of the fence 69d of intermediate insulating film 69 becomes roughly linearity, can not form the broken circle A of Figure 27 such become the transformation part of curve from straight line.
As illustrated in the preparatory items,, then can produce the problem that the fence 69d of this part peels off easily if there is the transformation part that becomes curve from straight line in fence 69d.
To this, in the present embodiment, owing to there is not such transformation part, can prevent peeling off of in operation fence 69d effectively, can be suppressed at the generation of the defective of the bad grade of being seen under the situation that fence 69d peels off of pattern, thereby improve finished semiconductor device product rate.
In addition, in the present embodiment, shown in Figure 65, the step part 69x that has the section 69c of radian because of the optical adjacent effect is covered by illusory control gate 74b.
Thus, when the pattern-forming of the illustrated intermediate insulating film 69 of Figure 46, because illusory control gate 74b becomes etching mask, so this step part 69x can not become fence.Therefore, do not produce the curvilinear fence that peels off easily, can further prevent the low problem of finished semiconductor device product rate that causes because of this fence in the end of unit area II.
More than, embodiments of the present invention are had been described in detail, but the present invention is not limited only to above-mentioned execution mode.
For example, though to Figure 29, Figure 31, the reticle mask 100,103,105 of the attenuation type among Figure 33 is illustrated, and replaces these films, also can use binary (binary) reticle mask of the photomask with chromium etc.

Claims (8)

1. the manufacture method of a semiconductor device is characterized in that, comprising:
By on Semiconductor substrate, forming element separating insulation film, on above-mentioned Semiconductor substrate, delimit the operation that is parallel to each other and separates the active region of spaced a plurality of band shapes;
Be positioned at the operation that forms tunnel insulator film on the above-mentioned Semiconductor substrate of above-mentioned active region;
On above-mentioned tunnel insulator film and said elements separating insulation film, form the operation of first conducting film respectively;
The operation of coating photoresist on above-mentioned first conducting film;
Use exposure mask, the operation that above-mentioned photoresist is exposed, described exposure mask has the structure that has formed the light-shielding pattern of a plurality of band shapes on transparency carrier in parallel to each other, and described light-shielding pattern has the narrow width portion more than two that the terminad width narrows down successively;
Above-mentioned photoresist is developed, form the operation of the corrosion-resisting pattern of each and the separated a plurality of band shapes comprise above-mentioned a plurality of active regions;
Above-mentioned corrosion-resisting pattern as mask, is optionally carried out etched operation to above-mentioned first conducting film;
Remove the operation of above-mentioned corrosion-resisting pattern;
After removing above-mentioned corrosion-resisting pattern, on said elements separating insulation film and above-mentioned first conducting film, form the operation of intermediate insulating film respectively;
On above-mentioned intermediate insulating film, form the operation of second conducting film;
By above-mentioned first conducting film, above-mentioned intermediate insulating film and above-mentioned second conducting film are carried out pattern-forming, on above-mentioned active region, form the flash cell be formed with above-mentioned tunnel insulator film, floating boom, above-mentioned intermediate insulating film and control gate successively, and on the said elements separating insulation film of the end of above-mentioned active region, form the operation of the structure of the section that is formed with the bottom conductor pattern of island, above-mentioned intermediate insulating film successively and illusory conductive pattern.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, forms the operation of above-mentioned flash cell and said structure body, comprising:
First etching step, optionally the part that does not become above-mentioned control gate and above-mentioned illusory conductive pattern in above-mentioned second conducting film is removed in etching;
Second etching step, optionally formed above-mentioned intermediate insulating film on above-mentioned first conducting film between above-mentioned control gate and above-mentioned illusory conductive pattern is removed in etching;
The 3rd etching step, after above-mentioned intermediate insulating film is carried out etching, use the etch-rate etchant slower than the etch-rate of above-mentioned second conducting film of above-mentioned intermediate insulating film, optionally above-mentioned first conducting film between above-mentioned control gate and above-mentioned illusory conductive pattern is removed in etching.
3. the manufacture method of semiconductor device as claimed in claim 2 is characterized in that,
Above-mentioned etchant in above-mentioned the 3rd etching step adopts Cl 2And O 2Mist, and
Above-mentioned first conducting film adopts polysilicon film, and above-mentioned intermediate insulating film adopts the ONO film.
4. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in the operation that forms above-mentioned flash cell and said structure body, above-mentioned control gate and above-mentioned illusory conductive pattern are formed band shape, this band shape is meant, the belt like shape of extending in parallel to each other on the direction vertical with the bearing of trend of above-mentioned active region.
5. the manufacture method of semiconductor device as claimed in claim 4, it is characterized in that, in the operation that forms above-mentioned flash cell and said structure body, with the long limit of close above-mentioned control gate one side of above-mentioned illusory conductive pattern be formed on the above-mentioned narrow width portion of above-mentioned light-shielding pattern crossing position on.
6. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, in the operation that forms above-mentioned flash cell and said structure body, forms above-mentioned illusory conductive pattern in the mode that comprises above-mentioned bottom conductor pattern.
7. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, in the operation that above-mentioned photoresist is exposed, with the focusing of exposure device in the out of focus scope that the projection image that does not make above-mentioned light-shielding pattern connects together each other.
8. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned first conducting film adopts polysilicon film.
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