CN101325245A - Electronics module, method for the manufacture thereof and applications - Google Patents
Electronics module, method for the manufacture thereof and applications Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/64—Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof, not peculiar to a single device provided for in groups H01L31/00 - H10K99/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
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- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Read Only Memory (AREA)
Abstract
This publication concerns electronics modules comprising at least one first material zone formed of first material which can be structurally transformed by means of electric interaction in order to increase its conductivity at least locally, the first material having a first transformation threshold, and at least one second material zone in the vicinity of the first material zone. According to the invention, the second material zone is formed from second material, which can also be structurally transformed in order to increase its conductivity, the second material having a second transformation threshold, which is lower than the transformation threshold of the first material zone. With the aid of the invention, post-processing electrical programmability and non-volatility of printable memories can be achieved.
Description
Technical field
But the present invention relates to electric unit and manufacture method thereof such as memory device one especially printed memory.Memory can for example use in low cost RFID, transducer or the media application.The invention still further relates to manufacture method.
Background technology
Conductor structure can based on be printed on plastics or the paper substrates and under the compatible temperature of plastic the metal nanoparticle suspended substance of (T<200 ℃) sintering form.The nano-ink of this silver (nanoink) can easily buy from the company such as Cabot company or Harima company.Except that sintering in stove, known laser sintering [people such as N.Bieri, Superlattices and Microstructures 35,437 (2004) .], UV sintering and microwave sintering [people such as J.Perelaer also in this area, Adv.Mater.18,2101 (2006)].
Also inedited patent application FI has described a kind of improving one's methods of sintering nanoparticle systems that be used for, electric sintering for No. 20060697 when submitting the application to.In the method, the nanoparticle systems conductance significantly improves under electric treatment.Compare with the thermal sintering of routine, electric sintering process is quick, and can reduce the heat load of substrate and other surrounding structure.The electricity sintering has been realized the direct-on-line monitoring through the conductance of the line of sintering, and it has also realized the patterning of conductor structure during sintering.The residual resistance that FI 20060697 has also described electric sintering structure can pass through the boundary condition of the electric treatment that applied and systematically control (for example, source impedance (bias resistor), the dynamic source adjusting of propagating based on sintering process etc.).
People such as S.Sivaramakrishnan at Nature Materials (nature material) 6,149 (2007) but in the another kind of method of insulator controlled in the printed polymeric composition of nano metal cluster to metallic transition that having proposed.Similarly method discloses in the open WO 2007/004033A2 of patent application.
US 2004/0085797 has disclosed a kind of method that changes nanometer or atomic state by means of dc voltage.The lip-deep electrode application voltage of the layer by being positioned at the flexibility that contains dispersed particle, similar gels, thus particle aligns or forms cluster along electric field, and the conductivity of this structure is local to be increased.This method can not be applicable to the manufacturing non-volatile structure well, and can not be used for forming from the teeth outwards lead.
Disclosed among the WO 2005/104226 and a kind ofly applied by passing the layer that contains nano particle that very high (>1kV) potential pulse makes the method for break-through contact in semiconductor chip.This method can not be used for forming from the teeth outwards lead.
US 2006/159889 discloses a kind of multi-sheet printed method that is used for electronic product and display.In the method, electronic ink is deposited from the teeth outwards and make this China ink solidify.After only formerly anterior layer is cured, promptly reach after its end-state, carry out the deposition of succeeding layer.Therefore, but this method can not Production Example as the write memory of printing.
Summary of the invention
An object of the present invention is to provide a kind of electronic module of novelty, concrete is a kind of memory component, and it can make the line operate of going forward side by side easily.Particularly, the purpose of this invention is to provide can print memory element, product and make the exercisable innovative techniques of this element in the middle of it.
Another object of the present invention provides a kind of novel method that is used to make the practical application of module and module.
The present invention can produce by the interact idea of the structure that increases of electricity from the conductivity that two kinds of materials that will carry out sintering process etc. under different condition are used for constructing the intermediate layer between two electrodes wherein.Particularly, the nanometer particle material with different sintering temperatures can be used to realize this structure.If the sintering temperature of described electrode is selected as being lower than the sintering temperature in intermediate layer, then electrode can be by sintering easily and sintering intermediate layer not.The intermediate layer can be used as the write once memory layer in memory component, switch, the anti-fuse etc. subsequently.Basic principle of the present invention also can be used for other electricity field.
Therefore, electronic module according to the present invention comprises at least one first material sections of being formed by first material and at least one second material sections adjacent with this first material sections, first material can structurally change by means of electricity interacts so that increase its conductivity at least partly, and described first material has first and changes threshold value.According to the present invention, second material sections is formed by second material, and this second material also can structurally change so that increase its conductivity, and second material has the second transformation threshold value lower than the transformation threshold value of first material sections.
Structural transformation can interact by internal electrical processes such as () electric sintering or increase temperature by the external heat radiation and begin.Preferably, the described structural transformation of described at least first material is permanent in nature.
Utilize the memory component of above-mentioned principle to comprise that the structure of two electrode layers and memory layer makes, thereby memory layer is formed so that increase the conductivity of this layer at least partly by first material that can electricity changes by formation.These materials preferably contain the material of nano particle.According to the present invention in the electrode layer at least one, preferably both are by second made, and this second material can change to increase the conductance of electrode layer.Select the transformation threshold value of layer, transition temperature makes the transition temperature of electrode layer be lower than the transformation threshold value of memory layer specifically.This allows by the condition that the characteristic that makes element be subjected to each layer changes between the threshold value memory component to be transformed into the functional memory element from middle product.When utilizing conventional sintering, condition comprises suitable external temperature and/or pressure.On the other hand, when material can interact change by means of electricity by suitable electric field being applied to the condition that this structure realizes expecting (thereby, in micro-scale, the temperature of electrode is increased to it more than transformation threshold value) in inside.
Therefore, memory component is included at least one memory block (memory bits) that does not also change when the partial electrode material is applied to element at least.Yet, because electrode material is easier to change than the memory block, thus the back it can under the situation that does not change the memory block, change.Only when being written into, memory changes the memory block.Because the coating of necessary material and each unit is worked can finish in the diverse stage, but this allows more directly to make the printed memory unit.
The memory component or the intermediate product that are used for the gained of manufacturing function memory component comprise
-two electrode layers, and
-structurally change so that increase the memory layer of first made of the conductivity of this layer at least partly by interacting by means of electricity.
Electrode layer and memory layer are aligned to the such relative position about each other: the structural transformation of memory layer can be induced by apply voltage between electrode layer.According to the present invention, at least one in the electrode layer preferably two this second material also can structurally change so that increase the conductivity of this layer at least partly by second made, it changes the transformation threshold value that threshold value is lower than memory layer.
These layers can vertically place the top of each other, as sandwich, or laterally as planar structure.In arranged perpendicular, structural transformation from fashionable intermediate layer to element that write is main along carrying out perpendicular to the direction of substrate.In landscape configuration, change the main direction that limits along the plane of substrate and carry out.
A plurality of memory cells of above kind can be arranged to array, have the element of the storage capacity of increase in order to formation.Therefore, this structure comprises a plurality of memory cells of one dimension, two dimension or 3 d grid shape, thereby electrode layer is arranged to allow writing separately and reading of each memory cell.
More specifically, the method according to this invention, electronic module, printing electronic product, transducer and RFID label are characterized by independent claims.
According to preferred embodiment of the present invention, a kind of method that is used to form memory component is provided, described method comprises that formation comprises the structure of external electrode layer and intermediate store layer, make in the exterior layer at least one comprise nano particle, it can be sintered so that increase the conductivity of described at least one exterior layer, and the sintering temperature of described at least one exterior layer is lower than the sintering temperature in described intermediate layer.
The invention provides significant advantage.By means of the present invention, for example, can make and some structure of functionalization, described structure comprises two or more material sections of tight adjacent coating each other, but only one of them expectation changes by sintering.
But in the printed memory field, obtained specific advantage.That is, described structure can be used as for example write once read many (WORM) device.In a lot of the application, such as RFID, transducer and the media application of printing electronics, IDTechEx expects that its market growth is rapid, has the needs for the low-cost digital memory.The present invention allows reprocessing, electrically programmable, low voltage operating and non-volatile, and these all are memory characteristics desired in the above-mentioned field.On the other hand, the type of required memory, random-access memory (ram), ROM or WORM depend on application.
Another advantage of the present invention is that memory writes and can finishes after the device fabrication process of reality.This significantly is better than the printing device described among the U.S. Patent Application Publication US 2007/0057311 for example, and wherein each bit all forms during printing.Equally, much other conventional printed memory is ROM type (read-only memory), promptly writes during fabrication.
In low cost was used, the common target of memory manufacturing was to utilize printing to finish, and printing is the method that has superiority very much that potential low cost is produced in enormous quantities.
Product in main range of application of the present invention generally is passive or battery powered, therefore it is highly important that with low voltage level and reads and write its memory.Because the vertical topology device according to preferred embodiment of the present invention can be designed such that the permission low operating voltage, the present invention also provides solution easily to this problem.
Observe, nano particle, the metal nanoparticle of especially sealing the low frit voltage of memory and non-volatile aspect have superiority very much.The metal that is fit to specifically is silver, gold, copper, platinum, nickel, palladium, iron, titanium, tin and alloy thereof.
Additional advantage obtains by other embodiments of the invention, and some feature wherein characterizes in the dependent claims.
According to an embodiment, use to allow structural transformation to increase the material that temperature begins by the internal electrical interaction or by external heat irradiation.
According to an embodiment, use first and/or second material (such as the memory layer in the WORM memory) of the permanent character of structural transformation characteristic with first and/or second material.
According to an embodiment, contain the material of nano particle, preferably contain the material of sealing nano particle and generally having metallic core and be used as first and/or second material.
According to an embodiment, electronic module is by making the memory component that a kind of structure obtains, this structure comprises one or more memory cells, each memory cell comprises two electrode layers and memory layer, thereby memory layer is formed by described first material, and in the electrode layer at least one formed by described second material.Generally speaking, in the electrode layer at least one be more than the transformation threshold value of electrode layer but change under the condition below the transformation threshold value of memory layer, preferably by the thermal sintering method or pass at least one electrode layer plane of (preferably perpendicular to this layer) and apply suitable transformation electric field or voltage.Memory cell preferably forms sandwich separately, and wherein memory layer is coated between the outer electrode layer.
In all layers in the structure one or more layers generally forms on substrate by printing or aerosol deposition.As substrate, preferably use paper, cardboard or plastics.
According to preferred embodiment, all layer is printed on the substrate as the China ink that contains nano particle, it is dry after coating.
Nano particle in the one or more layer in this structure is preferably to be sealed, and deposits easily and sintering in order to allowing.
When making memory product be ready to use, at least one exterior layer is by conventional thermal sintering method (for example, stove, laser, UV or microwave) or by preferably applying sintering under the sintering temperature that suitable sintering electric field or voltage is being lower than the intermediate layer at least one exterior layer perpendicular to the plane of layer.
Described structure is preferably by the sandwich of following realization
-first electrode pattern is printed on the substrate, and make described electrode layer drying,
-intermediate layer is printed on the first dry electrode pattern, and partly overlapping with first electrode pattern, and make the intermediate layer drying, and
-second electrode pattern is printed onto dry intermediate layer, and partly overlapping with the intermediate layer, and make the second electrode lay drying.
A plurality of such sandwiches can form by one dimension, two dimension or 3 d grid shape, thereby at least one in the exterior layer or both are with continuous band-shaped setting, this band intersects with the one or more bands that formed by other exterior layer, makes that at least the intermediate layer remains between two exterior layers in the zone of intersection.
The supplementary insulation material layer can be coated in the sandwich, so that before the sintering intermediate layer, keep the electrode layer electric insulation.
Described structure also can be by spaced first and second electrode patterns of printing on substrate, and the planarized structure that realize in the printing intermediate layer between first and second electrode patterns.
According to a second aspect of the invention, first and second electrode layers are formed by the layer that contains nano particle, and the sintering temperature of these layers is lower than the sintering temperature in intermediate layer.These layers are coated on paper, cardboard or the plastic.These layers form sandwich, as above better detailed description.In addition, this structure can comprise a plurality of such sandwich of one dimension, two dimension or 3 d grid shape, thereby at least one in the exterior layer or both are continuous band-shaped, this band intersects with the one or more bands that formed by other exterior layer, makes that at least the intermediate layer remains between two exterior layers in the zone of intersection.
Can laterally apply these layers so that form planarized structure.Therefore, first and second electrode layers are printed on the substrate apart from one another by ground, and memory layer is printed between first and second electrode layers.
In memory application, first and second electrode layers have carried out sintering by the thermal sintering method of routine or by electric sintering process with the temperature that its temperature increases to the sintering temperature that is lower than the intermediate layer.
According to a third aspect of the invention we, provide a kind of printing-type electronic product, it comprises memory component or the intermediate products that are used for the manufacturing function memory component.
According to a forth aspect of the invention, provide sensor component, comprised transducer, this transducer is coupled to memory component or the intermediate products that are used for the manufacturing function memory component, in order to the data that provided by described transducer to be provided.
When describing embodiment, term " electric sintering " is used for being described in the structural transformation process of the layer generation that contains nano particle continually.Should note, term " electric sintering " has general sense in this article: except that the scope that nano particle adheres to mutually in sintering process of routine, " electric sintering " changes can comprise that also (i) lasting electricity applies, it causes melting completely and recrystallization, original therebetween nano particles array form disappears, (ii) electricity-Re snowslide or puncture the type phenomenon, it causes the formation of the structure of local similar lead.Particularly, it shall yet further be noted that electricity induces transformation may not comprise whole intermediate layer, and the conductive path of inducing can be a local characteristics.
The accompanying drawing summary
Figure 1A-1D preferred embodiment according to the present invention illustrates the end view of manufacture process, final structure and memory program of a memory bits of vertical topology.
Fig. 2 A-2C illustrates among Fig. 1 with the memory bits manufacture process of vertical topology and the vertical view of final structure.
Fig. 3 illustrates the end view of two dimensional memory matrix according to one embodiment of present invention.
Fig. 4 illustrates the vertical view of the two dimensional memory matrix of Fig. 3.
Fig. 5 illustrates the end view of the two dimensional memory matrix that comprises supplemental dielectric layer.
Fig. 6 describes the vertical view of the two dimensional memory matrix of Fig. 5.
Fig. 7 A-7D preferred embodiment according to the present invention illustrates the end view of three-dimensional storage matrix manufacture process and final structure.
Fig. 8 illustrates the end view of the three-dimensional storage matrix structure that utilizes optional electrode configuration.
Fig. 9 describes the vertical view of the three-dimensional storage matrix structure of Fig. 8.
Figure 10 A-10C illustrates the end view of the manufacture process and the structure of horizontal topological manufacture method according to one embodiment of present invention.
Figure 11 illustrates the exemplary configuration of the electric sintering of electrode.
But Figure 12 illustrates the arrangement of the electric sintering of electrode.
The detailed description of embodiment
Fig. 1 and Fig. 2 have described a preferred embodiment of the present invention.Here, realized being used as the vertical parallel plates three-decker of write once read many (WORM) memory component.Manufacturing and operating process are made up of step shown in Figure 1 (A) .. (D) substantially.The key property of this structure is that it is by respectively in temperature T
Cure1<T
Cure2Black N1 of two kinds of nano particles of following sintering and N2 make.First electrode 101 at first is printed on [Figure 1A] and drying on the substrate 100 by material N1, makes that further deposition becomes possibility.Intermediate layer 102 is by material N2 printing and dry in order to allow further deposition [Figure 1B] then.Then second electrode 103 by material N1 because of brush and dry [Fig. 1 C].At this moment, total is ready in temperature T
Cure1<T<T
Cure2Following sintering makes in the intermediate layer 102 to keep unsintered whiles two electrode 101,103 and be sintered and good conductive.This nano particle China ink that fully different sintering temperatures is shown can buy.The programming of memory bits [Fig. 1 D] utilizes " electric sintering " to finish: voltage 104 is applied to becomes (at least in part) sintering and the intermediate layer of the conductivity of increase is shown.So this device is as write once read many (WORM) memory.This device may use the data record that is included in the sensor application: for example, can realize monitoring encapsulation humidity and at the interval/limited cross place of programming with the printing wetness sensor of writing data into memory
Fig. 2 illustrates the vertical view of Fig. 1 and the described manufacture process of above literal.
The key advantage of vertical topology shown in Figure 1 is that the less thickness of the layer 102 of electric sintering allows to write with low operating voltage/power.In addition, the normally good controllable parameter of known bed thickness in the thin film technique field.
We observe for practical application in our test, but sinter layer can not kept the sufficiently long duration of electricity sintering (some months, several years).
Obviously, alternatively, the ground floor 101 and the second layer 102 can be in temperature T after deposition
Cure1<T<T
Cure2Directly solidify, and be not only dry and curing after a while.
Fig. 3,4,5 and 6 illustrates another that be used to realize two dimensional memory arrays and organizes preferred embodiment of the present invention.Fig. 3 and Fig. 4 describe such structure: wherein first electrode 201 (that is, " bit line ") at first is printed on the substrate 100, deposits the intermediate store layer 202 and second electrode 203 (that is, " word line ") then.As conspicuous from Fig. 4 institute, the deposition of memory layer 202 can be deposited over the electrode crossing position.
As illustrated in Figures 5 and 6, supplemental dielectric layer 204 can use in this structure, for example is used for helping to solve step coverage issues.Equally, memory layer district 202 can control easily by utilizing insulating barrier 204, for example by impedance ranges of regulating memory bits or the material consumption that reduces memory layer 202.
Fig. 7,8 and 9 illustrates the another group of preferred embodiment that realizes three-dimensional (3D) memory construction.Should note, possibility via the stacked vertical of a plurality of layers of successive sedimentations is the basic advantage of printing process, and comprise the potentiality that realize high-density memory device (although there is line width limit in printing technology, bit/volume, little area occupied, high density are potential).Fig. 7 illustrates basic preferable 3D memory construction and implementation procedure thereof.At first, first electrode 301 and first insulation layer 302 are deposited over [Fig. 7 A] on the substrate 100.Then, memory layer 303 and another insulating barrier 304 are deposited [Fig. 7 B], deposit second electrode 305[Fig. 7 C subsequently].In this, formed the ground floor of memory cell.Then, the 3D implementation procedure can and comprise that for example the second layer memory cell of first electrode 308, memory layer 309 and second electrode 310 continues [Fig. 7 D] similarly by depositing insulating layer 307.Can further continue described implementation procedure by repeating above-mentioned preceding two memory layers similarly then, up to the memory size [Fig. 7 D] that realizes expectation.
Fig. 8 illustrates another preferred embodiment (end view) that realizes the 3D memory construction.Here, compare, improve memory density by the memory layer that utilizes each electrode to visit top of electrodes and bottom in essence with Fig. 7.Fig. 8 illustrates first electrode 311, memory layer 312, insulating barrier 313 and second electrode 314.
Fig. 9 illustrates x electrode and y electrode (being respectively " bit " and " word " line) and arranges (vertical view) as alternate position how.Here, first group of y line 321, first group of x line 322, second group of y line 323 and second group of x line 324 are by successive sedimentation (comprising intermediate store layer and insulating barrier, not shown among Fig. 9).So manufacture process can continue by going up the 3rd group of y line of deposition or the like in the position (top) of first group of y line 321.The structure that utilizes y line and x line to replace can obtain such as (i) higher memory density (comparatively thin structure), (ii) helps the advantage of more smooth structure that ladder for example covers and so on.
Figure 10,11 and 12 illustrates another group preferred embodiment that wherein adopts the transversal device topology.Here, the one 401 and the 2 403 electrode at first is printed on [Figure 10 A] on the substrate 100, subsequently printed memory layer 402[Figure 10 B].As mentioned above, be used for electrode 401,403 and memory layer 402 by the material that will have different sintering temperatures, total finally can be in temperature T
Cure1<T<T
Cure2Sintering, this is with the electrode sintering but make memory layer keep not sintering.Memory construction can utilize the electric sintering of the voltage that applies 404 to write [Figure 10 C] after a while.
Alternatively, as Figure 11 and shown in Figure 12, also can replace thermal sintering to be used for the sintering of horizontal memory construction electrode electric sintering.This can be after printing electrode (applying before the memory layer) [Figure 11] maybe when selecting electric sintering strength to make that the higher sintering temperature of memory layer makes it keep not sintering in the electrode sintering, printing this two-layer after [Figure 12] finish.In Figure 11 and Figure 12, electric sintering process comprises sintered electrode 406, power supply and electrical connection 405 and the optional insulating barrier 407 that is coated in structural top to be sintered and bottom.Generally, apply AC voltage to impel the electric sintering of electrode 401,403.Insulating barrier 407 and sintered electrode 406 can externally promptly, not remain the part of manufacturing structure.
Obviously, electric sintering also can be used at least one the sintering in the electrode of vertical topology (Fig. 1 ... 9) similarly.
As obviously easily seeing among Figure 10, laterally the major defect of topology is to realize the required high printed resolution/accuracy of sufficient electric sintering length.This has emphasized the advantage of the vertical topology among Fig. 1.
In order to allow write memory, this device comprises or is coupled to the device that is used for applying electric sintering voltage between electrode layer.When applying voltage, the state of memory layer changes.
Observe in test, the resistance of electric agglomerated material can systematically be controlled by electric condition (for example, the bias resistor by using series connection or by using may command wherein to apply the programmable power supply of voltage and current pattern) by change.Therefore, can repeatedly write each memory cell, the resistance that is obtained all becomes lower each time.A plurality of values/a plurality of bit storage in each unit of this permission (i), (ii) the part rewriting property of each unit.That is, apply the device of writing voltage and be applicable to the conductivity of memory layer is progressively increased with controlled manner, have three kinds or more kinds of predetermined conductivity state memory component separately in order to the capacity that increases this device so that realize memory cell wherein.
In addition, for additional rewriting property, can construct the emulation RAM that has limited write cycle time N; For example, comprise the structure that N takes advantage of the M bit, wherein M is memory stores (piece) size.Writing/when rewriteeing, use the new piece of M bit.In addition, this structure comprises the pointer memory block of similar memory cell, and it is being write fashionable renewal at every turn and will read the memory block of pointing to expectation with next write access.
Those skilled in the art sees easily that obviously (i) exists to utilize and have different sintering temperature T
Cure1, T
Cure2, T
Cure3..., three kinds or the additional embodiment that realizes of more materials, (ii) material is not limited to metal nanoparticle, but also (for example can adopt other material, ITO, the ZnO that mixes etc.), (iii) printing process is not limited to the method (liquid suspension) based on China ink, but also can adopt aerosol deposition technology [for example, referring to www.optomec.com M3D depositing operation].
Claims (18)
1. method that forms electric module, described method comprises: described module is formed the structure that comprises at least one first material sections and at least one second material sections adjacent with described first material sections, described first material sections is formed by first material, described first material can structurally change by means of electricity interacts so that increase its conductivity at least partly, described first material has first and changes threshold value
It is characterized in that utilize second material sections that is formed by second material, described second material can structurally change so that increase its conductivity, described second material has the second transformation threshold value lower than the transformation threshold value of described first material sections.
2. the method for claim 1 is characterized in that, described structural transformation can interact or increase temperature by the external heat radiation and begin by internal electrical.
3. method as claimed in claim 1 or 2 is characterized in that, the described structural transformation characteristic of described at least first material is permanent.
4. as each the described method in the above claim, it is characterized in that, the material that will contain nano particle is as described first and/or second material, and described first and/or second material preferably comprises entrapped nano particle, generally has metallic core.
5. as each the described method in the above claim, it is characterized in that, memory component forms as described electronic module, described method comprises that formation comprises the structure of one or more memory cells, each described memory cell all comprises two electrode layers and a memory layer, preferably with the form of sandwich, thereby described memory layer is formed by described first material, and in the described electrode layer at least one formed by described second material.
6. method as claimed in claim 5, it is characterized in that, in the described electrode layer at least one preferably preferably applies suitable transformation electric field or voltage perpendicular to the plane of layer by the thermal sintering method or via at least one electrode layer more than the transformation threshold value of this electrode layer but change under the condition below the transformation threshold value at described memory layer.
7. as claim 5 or 6 described methods, it is characterized in that, form a plurality of sandwiches with one dimension, two dimension or 3 d grid shape, thereby at least one or two in the described exterior layer are with continuous band-shaped setting, described band intersects with the band or a plurality of band that are formed by described other exterior layer, makes to remain between two described exterior layers at memory layer described in the described zone of intersection at least.
8. as each the described method among the claim 5-7, it is characterized in that,
-first electrode layer is printed on the substrate, and make described electrode layer drying,
-described memory layer is printed on first electrode layer of described drying, and partly overlapping with described first electrode layer, and make described memory layer drying, and
-the second electrode lay is printed onto on the memory layer of described drying, and partly overlapping with described memory layer, and make described the second electrode lay drying.
9. as claim 5 or 6 described methods, it is characterized in that described structure is a planar structure, described memory layer and electrode layer relative to each other laterally are placed on the substrate.
10. an electronic module comprises
-by at least one first material sections that first material forms, described first material can interact by means of electricity and structurally change so that increase its conductivity at least partly, and described first material has first and changes threshold value, and
-at least one second material sections adjacent with described first material sections,
It is characterized in that second material sections is formed by second material, described second material also can structurally change so that increase its conductivity, and described second material has the second transformation threshold value lower than the transformation threshold value of described first material sections.
11. electronic module as claimed in claim 10 is characterized in that, before changing, described first and/or second material comprises the preferably nano particle of envelope-like.
12., it is characterized in that it is memory component such as the WORM element or the intermediate products that are used for the manufacturing function memory component, comprises one or more memory cells as claim 10 or 11 described electronic modules, each described unit also comprises
-by two electrode layers of described second made,
-by the memory layer of described first made,
Thereby described electrode layer and described memory layer are aligned to sandwich or other about each other such relative position: the structural transformation of described memory layer can be induced by apply voltage between described electrode layer.
13. electronic module as claimed in claim 12, it is characterized in that, it comprises control unit, described control unit is applicable to that the memory cell with described memory component is divided into memory block and memory block pointer unit, has the element of the random-access memory (ram) type of a limited number of possibility write access in order to realization.
14. as claim 12 or 13 described electronic modules, it is characterized in that, it comprises a plurality of such sandwich of one dimension, two dimension or 3 d grid shape, thereby at least one or two in the described exterior layer are continuous band-shaped, described band intersects with the band or a plurality of band that are formed by described other exterior layer, makes to remain between the described exterior layer in intermediate layer described in the described zone of intersection at least.
15. as each the described electronic module among the claim 22-30, it is characterized in that, it is a memory component, in the wherein said electrode layer at least one---generally be that the both is in structural transition stage at least in part, the conductivity of wherein said layer is higher than the not conductivity of transition layer.
16. one kind comprises the printing electronic product as each the described electronic module among the claim 10-15.
17. a sensor component comprises transducer, it is coupled to as each described memory component or the intermediate products that are used for the manufacturing function memory component among the claim 12-15, in order to the data that provided by described transducer to be provided.
18. a RFID label comprises as each described memory component or the intermediate products that are used for the manufacturing function memory component among the claim 12-15.
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FI20075429A FI122011B (en) | 2007-06-08 | 2007-06-08 | Method for Producing an Electronic Module, Intermediate to Produce an Electronic Module, Memory Element, Printed Electronic Product, Sensor Device, and RFID Tag |
FI20075429 | 2007-06-08 |
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CN101325245A true CN101325245A (en) | 2008-12-17 |
CN101325245B CN101325245B (en) | 2011-06-22 |
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EP (1) | EP2001053B1 (en) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104347589A (en) * | 2013-08-02 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Antifuse structure |
CN112054121A (en) * | 2020-09-14 | 2020-12-08 | 清华大学 | Resistive random access memory, resistive random access memory chip and preparation method thereof |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI124372B (en) | 2009-11-13 | 2014-07-31 | Teknologian Tutkimuskeskus Vtt | Method and products related to the deposited particles |
FI20155964A (en) * | 2015-12-17 | 2017-06-18 | Teknologian Tutkimuskeskus Vtt Oy | Electronic component, circuit, device, process for producing the component and functional process |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5714766A (en) * | 1995-09-29 | 1998-02-03 | International Business Machines Corporation | Nano-structure memory device |
US7294366B2 (en) * | 1998-09-30 | 2007-11-13 | Optomec Design Company | Laser processing for heat-sensitive mesoscale deposition |
US6541792B1 (en) * | 2001-09-14 | 2003-04-01 | Hewlett-Packard Development Company, Llp | Memory device having dual tunnel junction memory cells |
US6821848B2 (en) * | 2002-04-02 | 2004-11-23 | Hewlett-Packard Development Company, L.P. | Tunnel-junction structures and methods |
US7051945B2 (en) * | 2002-09-30 | 2006-05-30 | Nanosys, Inc | Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites |
US6807079B2 (en) | 2002-11-01 | 2004-10-19 | Hewlett-Packard Development Company, L.P. | Device having a state dependent upon the state of particles dispersed in a carrier |
CN100386868C (en) * | 2002-12-18 | 2008-05-07 | 国际商业机器公司 | Method of self-assembling electronic circuitry and circuits formed thereby |
KR100973282B1 (en) * | 2003-05-20 | 2010-07-30 | 삼성전자주식회사 | SONOS memory device having nanocrystal layer |
DE102004003363A1 (en) * | 2004-01-22 | 2005-08-18 | Infineon Technologies Ag | Process to manufacture a nano-storage component for storage of an electronic charge by ion injection and crystallisation |
DE102004007633B4 (en) * | 2004-02-17 | 2010-10-14 | Qimonda Ag | Memory cell, semiconductor memory device and method of manufacturing a memory cell |
WO2005089165A2 (en) * | 2004-03-10 | 2005-09-29 | Nanosys, Inc. | Nano-enabled memory devices and anisotropic charge carrying arrays |
DE102004020497B8 (en) | 2004-04-26 | 2006-06-14 | Infineon Technologies Ag | Method for the production of plated-through holes and semiconductor device with such plated-through holes |
EP1743380B1 (en) * | 2004-05-06 | 2016-12-28 | Sidense Corp. | Split-channel antifuse array architecture |
US20060098485A1 (en) * | 2004-10-29 | 2006-05-11 | Agfa-Gevaert | Printable non-volatile passive memory element and method of making thereof |
US20070057311A1 (en) * | 2004-10-29 | 2007-03-15 | Agfa-Gevaert | Conventionally printable non-volatile passive memory element and method of making thereof |
US20060131555A1 (en) * | 2004-12-22 | 2006-06-22 | Micron Technology, Inc. | Resistance variable devices with controllable channels |
US8334464B2 (en) | 2005-01-14 | 2012-12-18 | Cabot Corporation | Optimized multi-layer printing of electronics and displays |
US20060163744A1 (en) * | 2005-01-14 | 2006-07-27 | Cabot Corporation | Printable electrical conductors |
US7208372B2 (en) * | 2005-01-19 | 2007-04-24 | Sharp Laboratories Of America, Inc. | Non-volatile memory resistor cell with nanotip electrode |
DE102005005938B4 (en) * | 2005-02-09 | 2009-04-30 | Qimonda Ag | Resistive memory element with shortened erase time, method of manufacture and memory cell arrangement |
US7507618B2 (en) * | 2005-06-27 | 2009-03-24 | 3M Innovative Properties Company | Method for making electronic devices using metal oxide nanoparticles |
CN101238528B (en) | 2005-07-01 | 2011-12-07 | 新加坡国立大学 | Electrically conductive composites and preparation method, and storage device containing electrically conductive composites |
US7297975B2 (en) * | 2005-07-28 | 2007-11-20 | Infineon Technologies Ag | Non-volatile, resistive memory cell based on metal oxide nanoparticles, process for manufacturing the same and memory cell arrangement of the same |
DE102005035445B4 (en) * | 2005-07-28 | 2007-09-27 | Qimonda Ag | Non-volatile, resistive memory cell based on metal oxide nanoparticles, as well as processes for their preparation and corresponding memory cell arrangement |
US7491962B2 (en) * | 2005-08-30 | 2009-02-17 | Micron Technology, Inc. | Resistance variable memory device with nanoparticle electrode and method of fabrication |
US7482619B2 (en) * | 2005-09-07 | 2009-01-27 | Samsung Electronics Co., Ltd. | Charge trap memory device comprising composite of nanoparticles and method of fabricating the charge trap memory device |
KR100790861B1 (en) * | 2005-10-21 | 2008-01-03 | 삼성전자주식회사 | Resistive memory device comprising nanodot and manufacturing method for the same |
FI121562B (en) | 2006-07-21 | 2010-12-31 | Valtion Teknillinen | Method for the manufacture of conductors and semiconductors |
US9011762B2 (en) | 2006-07-21 | 2015-04-21 | Valtion Teknillinen Tutkimuskeskus | Method for manufacturing conductors and semiconductors |
-
2007
- 2007-06-08 FI FI20075429A patent/FI122011B/en not_active IP Right Cessation
-
2008
- 2008-06-06 US US12/155,671 patent/US7915097B2/en not_active Expired - Fee Related
- 2008-06-06 EP EP08157721.5A patent/EP2001053B1/en not_active Not-in-force
- 2008-06-06 CN CN2008101099822A patent/CN101325245B/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104347589A (en) * | 2013-08-02 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Antifuse structure |
CN104347589B (en) * | 2013-08-02 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of anti-fuse structures |
CN112054121A (en) * | 2020-09-14 | 2020-12-08 | 清华大学 | Resistive random access memory, resistive random access memory chip and preparation method thereof |
CN112054121B (en) * | 2020-09-14 | 2023-04-07 | 清华大学 | Resistive random access memory, resistive random access memory chip and preparation method thereof |
Also Published As
Publication number | Publication date |
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EP2001053A3 (en) | 2012-03-28 |
FI122011B (en) | 2011-07-15 |
US20080303583A1 (en) | 2008-12-11 |
FI20075429A0 (en) | 2007-06-08 |
EP2001053A2 (en) | 2008-12-10 |
EP2001053B1 (en) | 2014-10-29 |
FI20075429A (en) | 2008-12-09 |
CN101325245B (en) | 2011-06-22 |
US7915097B2 (en) | 2011-03-29 |
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