CN101320417A - Squarer circuit and implementing method thereof - Google Patents
Squarer circuit and implementing method thereof Download PDFInfo
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- CN101320417A CN101320417A CNA2008101344063A CN200810134406A CN101320417A CN 101320417 A CN101320417 A CN 101320417A CN A2008101344063 A CNA2008101344063 A CN A2008101344063A CN 200810134406 A CN200810134406 A CN 200810134406A CN 101320417 A CN101320417 A CN 101320417A
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Abstract
The invention discloses a realization circuit for a squarer, which comprises: an acquisition module that is used to acquire a mutual multiply item, square item and supplement item according to the input symbolic number during the squaring process; a first sum module that sums up the mutual multiply item attained by the acquisition module and generates a first sum result; a second sum module that sums up the first sum result attained by the first sum module and the square item attained by the acquisition module and generates a second sum result; a third sum module that sums up the second sum result attained by the second sum module and the supplement item attained by the acquisition module and generates a third sum result; a combination module that combines the third sum result attained by the third sum module and a lower 2bit digit and generates a square result for the symbolic number. Therefore, the invention simplifies the circuit structure for realizing the squarer and greatly saves the circuit resources.
Description
Technical field
The embodiment of the invention relates to circuit design field, particularly relates to a kind of square circuit and implementation method.
Background technology
Squarer is one of widely used typical circuit of science and technology field, in the side circuit design, can adopt multiplier to realize squarer or employing look-up table realization squarer.
Wherein, the implementation structure of employing multiplier comprises an absolute value realization circuit and a multiplier as shown in Figure 1, and the implementation procedure of squarer is as follows, describes as the input data instance with the 4bit signed number.
At first, the binary expression formula of the input data A of 4bit signed number is as follows:
A＝a
3×2
3+a
2×2
2+a
1×2
1+a
0×2
0，
A wherein
i=0 or 1, i=0,1,2,3;
The first step: utilize absolute value realization circuit that input data A is asked for and export absolute value, promptly obtain importing the complement code of data according to sign bit, the complement code that obtains can be expressed as a 4bit unsigned number.The expression formula of this implementation procedure is as follows:
abs(A)＝(a
2^a
3)×2
2+(a
1^a
3)×2
1+(a
0^a
3)×2
0+a
3
＝b
3×2
3+b
2×2
2+b
1×2
1+b
0×2
0，
Wherein ^ represents XOR gate, b
i=0 or 1, i=0,1,2,3;
Second step: utilize multiplier absolute value is realized everybody of 4bit unsigned number of circuit output launch and add and, export final square result.The expression formula of this implementation procedure is as follows:
A
2＝(b
3&b
3+b
2&b
3+b
1&b
3+b
0&b
3)×2
3+(b
3&b
2+b
2&b
2+b
1&b
2+b
0&b
2)×2
2+
(b
3&b
1+b
2&b
1+b
1&b
1+b
0&b
1)×2
1+(b
3&b
0+b
2&b
0+b
1&b
0+b
0&b
0)×2
0，
Qi Zhong ﹠amp; Expression and door ,+expression or door.
In the scheme of above-mentioned employing multiplier, need 3 XOR gate and 1 4bit totalizer in the first step, wherein 1 XOR gate can equivalence be 3 not gates and 2 and door; Need 16 and door and 4 7bit totalizers in second step.Therefore, need 9 not gates, 22 and door, 1 4bit totalizer and 4 7bit totalizers altogether, the wasting of resources is more serious.
The implementation structure of employing look-up table as shown in Figure 2, squarer comprises an input port and an output port, also need to comprise storage unit, be used to store square result of corresponding input data, storage unit adopts ROM (Read-Only Memory usually, ROM (read-only memory)) or RAM (Random AccessMemory, random access memory).
For adopting look-up table to realize the method for squarer, when the input bit wide is 12bit, need 2
12Individual storage unit needs promptly that the degree of depth is 4096, bit wide is 23 ROM or RAM, and the resource that takies is very huge.
In realizing process of the present invention, the inventor finds that there is following shortcoming in above prior art: the method wasting of resources of the prior art is all compared seriously.
Summary of the invention
The embodiment of the invention provides a kind of square circuit and implementation method, to save the resource that realizes square circuit.
In order to reach above purpose, the embodiment of the invention provides a kind of realization circuit of squarer, comprising: acquisition module is used for signed number according to input and obtains the taking advantage of mutually of square process, involution item and addition item; First adds and module, is used for taking advantage of mutually of obtaining of described acquisition module summed up, and obtains first and adds and the result, and described first adds with the result and be adding and the result of taking advantage of mutually; Second adds and module, is used for adding and involution item that result and described acquisition module obtain sums up described first, obtains second and adds and the result, and described second adds with the result and add and the adding and the result of result and involution item for described first; The 3rd adds and module, is used for adding and addition item that result and described acquisition module obtain sums up described second, obtains the 3rd and adds and the result, and the described the 3rd adds with the result and add and the adding and the result of result and addition item for described second; Merge module, be used for adding with result and low 2bit position and merge, obtain square result of described signed number the described the 3rd.
The embodiment of the invention also provides a kind of implementation method of squarer, comprising: obtain according to the signed number of importing and take advantage of item, involution item, addition item in square process mutually; The described item of taking advantage of is mutually summed up, obtain first and add and the result; Add with result and described involution item described first and to sum up, obtain second and add and the result; Add with result and described addition item described second and to sum up, obtain the 3rd and add and the result; Add with result and low 2bit position the described the 3rd and to merge, obtain square result of described signed number.
In the embodiment of the invention,, compare and adopt multiplier and look-up table, saved the hardware circuit resource greatly by adopting the squarer universal circuit of this paper mode.
Description of drawings
Fig. 1 is the structural drawing that the available technology adopting multiplier is realized squarer;
Fig. 2 is the structural drawing that the available technology adopting look-up table is realized squarer;
Fig. 3 is the realization circuit structure diagram of the embodiment of the invention one 4bit signed number squarer;
Fig. 4 is the derivation figure of acquisition module in the embodiment of the invention one;
Fig. 5 is the realization circuit structure diagram of the embodiment of the invention two n bit signed number squarers;
Fig. 6 is the process flow diagram of the embodiment of the invention three squarer implementation methods.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail:
The embodiment of the invention one provides a kind of realization circuit of 4bit signed number squarer, and the binary expression formula of 4bit signed number is:
A＝a
3×2
3+a
2×2
2+a
1×2
1+a
0×2
0，
A wherein
i=0 or 1, i=0,1,2,3;
As shown in Figure 3, this circuit comprises: acquisition module 310, the first adds to add with module 330, the three with module 320, the second and adds and module 340, merges module 350.
Wherein, acquisition module 310 is used for according to input data taking advantage of mutually of obtaining that square process occurs, involution item and addition item, and input end is the value of every numerical digit of 4bit signed number: a
3, a
2, a
1, a
0, output terminal is taking advantage of mutually of occurring in square process, involution item and addition item.
As shown in Figure 4, acquisition module 310 specifically comprises:
The submodule 410 that multiplies each other is used for described 4bit signed number A is carried out from multiplying each other, wherein with sign bit a according to the binary expansion mode
3Relevant item all needs negate, this result with earlier A is taken absolute value after the multiply each other result that obtains identical;
Addition submodule 420 is used for the rule according to binary addition, and promptly identical two additions be equivalent to move to left 1bit and involution item equals multiplier itself, and every data that the submodule 410 that multiplies each other obtains are sued for peace.A as shown in Figure 4
1﹠amp; a
0, a
2﹠amp; a
0, a
3﹠amp; a
0, a
3﹠amp; a
1, a
3﹠amp; a
2, a
2﹠amp; a
1Every 1bit that all is moved to the left, each involution item is a simultaneously
0﹠amp; a
0, a
1﹠amp; a
1, a
2﹠amp; a
2, a
3﹠amp; a
3Every a that is expressed as respectively
0, a
1, a
2, a
3
Combination submodule 430 is used for every data that addition submodule 420 obtains are made up according to data structure, and the data with same structure are formed a class, and preferentially the numerical digit of each addend in each class are filled up, to reach the unification of arithmetic element structure.Making up the data that 430 pairs of addition submodules 420 of submodule obtain as seen from Figure 4 makes up according to data structure, data with same structure are formed a class, be combined as the involution item, take advantage of and addition item three classes mutually, and preferentially the numerical digit of each addend in each class is filled up, to not exist involution item and the position of taking advantage of item mutually to fill out 0 in the merging process, and economize lower slightly 2bit position.
Acquisition module 310 is taken advantage of { an a mutually
3﹠amp; a
2, a
3﹠amp; a
1, a
3﹠amp; a
0, a
2﹠amp; a
0, a
1﹠amp; a
0With 0,0, a
2﹠amp; a
1, 0,0}, involution item { a
3, 0, a
2, 0, a
1, { 0,0,1,0,0} adds to add with module the 330, the 3rd with module 320, second as first respectively and adds input data with module 340 addition item.Output data expression formula by acquisition module 310 realizes that as can be seen the circuit of this module needs 6 and door and 3 not gates altogether.
First adds and module 320, be used for acquisition module 310 is obtained two take advantage of mutually to sum up, need 1 5bit totalizer, input end is that two of obtaining of acquisition module 310 take advantage of item mutually, output terminal is first to add and the result, and described first adds with the result and be adding and the result of taking advantage of mutually.
Second adds and module 330, is used for adding the involution item that obtains with result and acquisition module 310 to described first and sums up, and needs 1 5bit totalizer, and input end is described first to add the involution item { a that obtains with result and acquisition module 310
3, 0, a
2, 0, a
1, output terminal is second to add and the result, described second adds with the result and adds and the adding and the result of result and involution item for described first.
The 3rd adds and module 340, being used for adding the addition item that obtains with result and acquisition module 310 to described second sums up, need 1 5bit totalizer, input end is described second to add the addition item { 0,0,1 that obtains with result and acquisition module 310,0,0}, output terminal the 3rd add and the result, and the described the 3rd adds with the result and add and the adding and the result of result and addition item for described second.
Merge module 350, be used for adding and result and low 2bit{0, a the described the 3rd
0Merge, input end is the described the 3rd to add and result and low 2bit{0, a
0, output terminal is square result of this 4bit signed number.
As mentioned above, the circuit structure that this squarer is realized only needs 6 and door, 3 not gates and 3 5bit totalizers, has therefore compared with prior art saved the hardware circuit resource in a large number.
The embodiment of the invention two provides a kind of realization circuit of n bit signed number squarer, present embodiment is the popularization to the realization circuit of above-mentioned 4bit signed number squarer, as shown in Figure 5, comprising: acquisition module 510, first adds to add with module 520, second and adds with module the 530, the 3rd and module 540 and merge module 550.
Wherein, acquisition module 510 is used for obtaining that input data square process occurs takes advantage of mutually, involution item and addition item, and input end is the value of every numerical digit of n bit signed number, and output terminal is taking advantage of mutually in square process, involution item and addition item.
The submodule that multiplies each other is used for the input data are carried out from multiplying each other, wherein with sign bit a according to the binary expansion mode
nRelevant item all needs negate, this result with earlier described n bit signed number is taken absolute value after the multiply each other result that obtains identical.Input end is described n bit signed number, and output terminal is for importing data from multiplied result.
The addition submodule is used for the rule according to binary addition, and promptly identical two additions be equivalent to move to left 1bit and involution item equals multiplier itself, and the result that the described submodule that multiplies each other is obtained sues for peace.Input end is the result that the described submodule that multiplies each other obtains, and output terminal is the result's that obtains of the described submodule that multiplies each other a summed result.
The combination submodule, be used for the result that described addition submodule obtains is made up according to data structure, data with same structure are formed a class, and preferentially the numerical digit of each addend in each class is filled up, to reach the unification of arithmetic element structure, to not exist involution item and the position of taking advantage of item mutually to fill out 0 in the merging process, and economize lower slightly 2bit position.Input end is the result that described addition submodule obtains, and output terminal is the combined result of the data that obtain of described addition submodule.The data that described addition submodule obtains can be combined as the involution item, take advantage of and addition item three classes mutually.
The involution item that acquisition module 510 obtains is:
{a
n-1，0，a
n-2，0，a
n-3，......，0，a
2，0，a
1}，
Wherein ", " represents the position connector.
The item of taking advantage of mutually that obtains is:
When n was even number, taking advantage of an item number mutually was n/2, every as follows:
The 1st: { a
N-1a
N-2, a
N-1a
N-3, a
N-1a
N-4..., a
N-1a
0, a
N-2a
0, a
N-3a
0, a
N-4a
0..., a
1a
0;
The 2nd: { a
N-2a
N-3, a
N-2a
N-4, a
N-2a
N-5..., a
N-2a
1, a
N-3a
1, a
N-4a
1, a
N-5a
1..., a
2a
1, 0,0};
The 3rd: { a
N-3a
N-4, a
N-3a
N-5, a
N-3a
N-6..., a
N-3a
2, a
N-4a
2, a
N-5a
2, a
N-6a
2..., a
3a
2, 0,0,0,0};
N/2 item: { a
N/2a
N/2-1, 0,0,0 ..., 0} wherein has n-2 individual 0.
When n is odd number, take advantage of an item number to be (n-1)/2 mutually, every as follows:
The 1st: { a
N-1a
N-2, a
N-1a
N-3, a
N-1a
N-4..., a
N-1a
0, a
N-2a
0, a
N-3a
0, a
N-4a
0..., a
1a
0;
The 2nd: { a
N-2a
N-3, a
N-2a
N-4, a
N-2a
N-5..., a
N-2a
1, a
N-3a
1, a
N-4a
1, a
N-5a
1..., a
2a
1, 0,0};
The 3rd: { a
N-3a
N-4, a
N-3a
N-5, a
N-3a
N-6..., a
N-3a
2, a
N-4a
2, a
N-5a
2, a
N-6a
2..., a
3a
2, 0,0,0,0};
(n-1)/2: { a
(n+1)/2a
(n-1)/2, a
(n+1)/2a
(n-3)/2, a
(n-1)/2a
(n-3)/2, 0,0,0 ..., 0} wherein has (n-3) individual 0.
The addition item that obtains is:
{1，0，0，0，......，0}，
N-2 individual 0 is wherein arranged.
First adds and module 520, be used for acquisition module 510 is obtained two takes advantage of mutually to sum up, and input end is that two of obtaining of acquisition module 510 take advantage of item mutually, and output terminal is first to add and the result, and described first adds with the result and be adding and the result of taking advantage of mutually.
Second adds and module 530, being used for adding the involution item that obtains with result and acquisition module 510 to described first sums up, input end is described first to add the involution item that obtains with result and acquisition module 510, output terminal is second to add and the result, and described second adds with the result and add and the adding and the result of result and involution item for described first.
The 3rd adds and module 540, being used for adding the addition item that obtains with result and acquisition module 510 to described second sums up, input end is second to add the addition item that obtains with result and acquisition module 510, output terminal is the 3rd to add and the result, and the described the 3rd adds with the result and add and the adding and the result of result and addition item for described second.
When n was even number, the realization circuit of the embodiment of the invention two needed (2n-3) bit totalizer n/2+1 altogether; When n was odd number, the realization circuit of the embodiment of the invention two needed (2n-3) bit totalizer (n+1)/2 altogether.
The embodiment of the invention three provides a kind of implementation method of squarer, as shown in Figure 6, comprising:
Step 601: obtain according to the signed number that receives and to take advantage of item, involution item, addition item mutually in square process;
Wherein, step 601 can also comprise following three steps:
Step 601A: the signed number that receives is carried out from multiplying each other according to the binary expansion mode, and the item relevant with sign bit all needs negate;
Step 601B: every data that step 601A is obtained sum up;
Step 601C: every data that step 601B is obtained make up according to data structure, data with same structure are formed a class, taken advantage of item, involution item and addition item three classes mutually, and preferentially the numerical digit of each addend in each class is filled up, to not exist involution item and the position of taking advantage of item mutually to fill out 0 in the merging process, and economize lower slightly 2bit position.
Step 602: taking advantage of mutually of obtaining of step 601C summed up, obtain first and add and the result, described first adds with the result and is adding and the result of taking advantage of mutually;
Step 603: first add the involution item that obtains with result and step 601C and sum up what step 602 obtained, obtain second and add and the result, this second adds with the result and adds and the adding and the result of result and involution item for described first;
Step 604: second add the addition item that obtains with result and step 601C and sum up what step 603 obtained, obtain the 3rd and add and the result, the described the 3rd adds with the result and adds and the adding and the result of result and addition item for described second;
Step 605: the 3rd add with result and low 2bit position and merge what step 604 obtained, obtain receiving square result of data.
The technical scheme of the embodiment of the invention adopts above-described squarer universal circuit design architecture, has reached the effect of saving the hardware circuit resource.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by hardware, also can realize based on such understanding by the mode that software adds necessary general hardware platform, technical scheme of the present invention can embody with the form of software product, it (can be CD-ROM that this software product can be stored in a non-volatile memory medium, USB flash disk, portable hard drive etc.) in, comprise that some instructions are with so that a computer equipment (can be a personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be looked protection scope of the present invention.
Claims (8)
1, a kind of realization circuit of squarer is characterized in that, comprising:
Acquisition module is used for signed number according to input and obtains the taking advantage of mutually of square process, involution item and addition item;
First adds and module, is used for taking advantage of mutually of obtaining of described acquisition module summed up, and obtains first and adds and the result, and described first adds with the result and be adding and the result of taking advantage of mutually;
Second adds and module, is used for adding and involution item that result and described acquisition module obtain sums up described first, obtains second and adds and the result, and described second adds with the result and add and the adding and the result of result and involution item for described first;
The 3rd adds and module, is used for adding and addition item that result and described acquisition module obtain sums up described second, obtains the 3rd and adds and the result, and the described the 3rd adds with the result and add and the adding and the result of result and addition item for described second;
Merge module, be used for adding with result and low 2bit position and merge, obtain square result of described signed number the described the 3rd.
2, the realization circuit of squarer according to claim 1 is characterized in that described acquisition module comprises:
The submodule that multiplies each other is used for described signed number is carried out from multiplying each other according to the binary expansion mode, and to the negate relevant with sign bit;
The addition submodule is used for every data that the described submodule that multiplies each other obtains are sued for peace;
The combination submodule is used for every data that described addition submodule obtains are made up.
3, as the realization circuit of squarer as described in the claim 2, it is characterized in that described combination submodule is the first combination submodule, is used for making up according to data structure, data with same structure are formed a class, and preferentially the numerical digit of each addend in each class are filled up; To not exist involution item and the position of taking advantage of item mutually to fill out 0, and economize lower slightly 2bit position.
4, the realization circuit of squarer according to claim 1 is characterized in that,
The described item of taking advantage of mutually is:
When n was even number, wherein n was the bit wide of the signed number of input, and taking advantage of an item number mutually is n/2, every as follows:
The 1st: { a
N-1a
N-2, a
N-1a
N-3, a
N-1a
N-4..., a
N-1a
0, a
N-2a
0, a
N-3a
0, a
N-4a
0..., a
1a
0;
The 2nd: { a
N-2a
N-3, a
N-2a
N-4, a
N-2a
N-5..., a
N-2a
1, a
N-3a
1, a
N-4a
1, a
N-5a
1... .., a
2a
1, 0,0};
The 3rd: { a
N-3a
N-4, a
N-3a
N-5, a
N-3a
N-6..., a
N-3a
2, a
N-4a
2, a
N-5a
2, a
N-6a
2..., a
3a
2, 0,0,0,0};
......
N/2 item: { a
N/2a
N/2-1, 0,0,0 ..., 0} wherein has n-2 individual 0;
When n is odd number, take advantage of an item number to be (n-1)/2 mutually, every as follows:
The 1st: { a
N-1a
N-2, a
N-1a
N-3, a
N-1a
N-4..., a
N-1a
0, a
N-2a
0, a
N-3a
0, a
N-4a
0..., a
1a
0;
The 2nd: { a
N-2a
N-3, a
N-2a
N-4, a
N-2a
N-5..., a
N-2a
1, a
N-3a
1, a
N-4a
1, a
N-5a
1..., a
2a
1, 0,0};
The 3rd: { a
N-3a
N-4, a
N-3a
N-5, a
N-3a
N-6..., a
N-3a
2, a
N-4a
2, a
N-5a
2, a
N-6a
2..., a
3a
2, 0,0,0,0};
......
(n-1)/2: { a
(n+1)/2a
(n-1)/2, a
(n+1)/2a
(n-3)/2, a
(n-1)/2a
(n-3)/2, 0,0,0 ..., 0} wherein has (n-3) individual 0;
Described involution item is:
{a
n-1，0，a
n-2，0，a
n-3，......，0，a
2，0，a
1}，
Wherein ", " represents the position connector;
Described addition item is:
{1，0，0，0，......，0}，
N-2 individual 0 is wherein arranged.
5, a kind of implementation method of squarer is characterized in that, comprising:
Signed number according to input obtains and takes advantage of item, involution item, addition item in square process mutually;
The described item of taking advantage of is mutually summed up, obtain first and add and the result;
Add with result and described involution item described first and to sum up, obtain second and add and the result;
Add with result and described addition item described second and to sum up, obtain the 3rd and add and the result;
Add with result and low 2bit position the described the 3rd and to merge, obtain square result of described signed number.
As the implementation method of squarer as described in the claim 5, it is characterized in that 6, described signed number according to input obtains takes advantage of item, involution item, addition item to comprise mutually in square process:
Described signed number is carried out multiplying each other certainly according to the binary expansion mode, and to the item negate relevant with sign bit;
The every data that obtain multiplying each other certainly sum up;
The every data that add and obtain are made up.
7, as the implementation method of squarer as described in the claim 5, it is characterized in that, the described every data that add and obtain are made up comprises: make up according to data structure, the data with same structure are formed a class, and preferentially the numerical digit of each addend in each class are filled up; To not exist involution item and the position of taking advantage of item mutually to fill out 0, and economize lower slightly 2bit position.
8, as implementation method as described in the claim 5, it is characterized in that,
The described item of taking advantage of mutually is:
When n was even number, wherein n was the bit wide of the signed number of input, and taking advantage of an item number mutually is n/2, every as follows:
The 1st: { a
N-1a
N-2, a
N-1a
N-3, a
N-1a
N-4..., a
N-1a
0, a
N-2a
0, a
N-3a
0, a
N-4a
0..., a
1a
0;
The 2nd: { a
N-2a
N-3, a
N-2a
N-4, a
N-2a
N-5..., a
N-2a
1, a
N-3a
1, a
N-4a
1, a
N-5a
1..., a
2a
1, 0,0};
The 3rd: { a
N-3a
N-4, a
N-3a
N-5, a
N-3a
N-6..., a
N-3a
2, a
N-4a
2, a
N-5a
2, a
N-6a
2..., a
3a
2, 0,0,0,0};
......
N/2 item: { a
N/2a
N/2-1, 0,0,0 ..., 0} wherein has n-2 individual 0;
When n is odd number, take advantage of an item number to be (n-1)/2 mutually, every as follows:
The 1st: { a
N-1a
N-2, a
N-1a
N-3, a
N-1a
N-4..., a
N-1a
0, a
N-2a
0, a
N-3a
0, a
N-4a
0..., a
1a
0;
The 2nd: { a
N-2a
N-3, a
N-2a
N-4, a
N-2a
N-5..., a
N-2a
1, a
N-3a
1, a
N-4a
1, a
N-5a
1..., a
2a
1, 0,0};
The 3rd: { a
N-3a
N-4, a
N-3a
N-5, a
N-3a
N-6..., a
N-3a
2, a
N-4a
2, a
N-5a
2, a
N-6a
2..., a
3a
2, 0,0,0,0};
......
(n-1)/2: { a
(n+1)/2a
(n-1)/2, a
(n+1)/2a
(n-3)/2, a
(n-1)/2a
(n-3)/2, 0,0,0 ..., 0} wherein has (n-3) individual 0;
Described involution item is:
{a
n-1，0，a
n-2，0，a
n-3，......，0，a
2，0，a
1}，
Wherein ", " represents the position connector.
Described addition item is:
{1，0，0，0，......，0}，
N-2 individual 0 is wherein arranged.
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| CN100590636C CN100590636C (en) | 2010-02-17 |
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| CN106569778A (en) * | 2015-10-13 | 2017-04-19 | 华为技术有限公司 | Data processing method and electronic equipment |
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| IL133451A0 (en) * | 1999-12-10 | 2001-04-30 | Dspc Tech Ltd | Programmable convolver |
| US7340019B2 (en) * | 2003-04-02 | 2008-03-04 | Intel Corporation | Programmable filter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106569778A (en) * | 2015-10-13 | 2017-04-19 | 华为技术有限公司 | Data processing method and electronic equipment |
| CN106569778B (en) * | 2015-10-13 | 2019-06-07 | 华为技术有限公司 | A kind of method and electronic equipment of data processing |
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