CN111191779B - Data processing method, device, processor and computer readable storage medium - Google Patents

Data processing method, device, processor and computer readable storage medium Download PDF

Info

Publication number
CN111191779B
CN111191779B CN202010000224.8A CN202010000224A CN111191779B CN 111191779 B CN111191779 B CN 111191779B CN 202010000224 A CN202010000224 A CN 202010000224A CN 111191779 B CN111191779 B CN 111191779B
Authority
CN
China
Prior art keywords
fitting
data
input data
interval
operation result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010000224.8A
Other languages
Chinese (zh)
Other versions
CN111191779A (en
Inventor
闯小明
杨龚轶凡
郑瀚寻
曾昭睿
周远航
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhonghao Xinying Hangzhou Technology Co ltd
Original Assignee
Zhonghao Xinying Hangzhou Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhonghao Xinying Hangzhou Technology Co ltd filed Critical Zhonghao Xinying Hangzhou Technology Co ltd
Priority to CN202010000224.8A priority Critical patent/CN111191779B/en
Publication of CN111191779A publication Critical patent/CN111191779A/en
Application granted granted Critical
Publication of CN111191779B publication Critical patent/CN111191779B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Computational Linguistics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Neurology (AREA)
  • Complex Calculations (AREA)
  • Image Analysis (AREA)

Abstract

The invention discloses a data processing method, a data processing device, a processor and a computer readable storage medium. The invention adopts the matching of the function value mapping circuit and the fitting operation circuit to rapidly and efficiently process the data so as to meet the requirement of the neural network on the nonlinearity, thereby improving the approximation capability of the neural network on complex functions. Compared with the prior art that only the fitting operation circuit is adopted to carry out the whole-interval fitting operation to fit the function value of the specific function, the invention not only can reduce the hardware resource cost by reducing the use of the fitting parameters, but also can accelerate the processing speed of the data processing device for the data by reducing the time of the fitting operation circuit for matching the fitting parameters.

Description

Data processing method, device, processor and computer readable storage medium
Technical Field
The present invention relates to the field of neural networks, and in particular, to a data processing method, apparatus, processor, and computer readable storage medium.
Background
In the deep learning application scenario of the neural network, we express the complex relationship between input and output by using the neural network. In mathematical language, complex functions are implemented using artificial neural networks. The neural network is composed of multiple layers of neurons, each neuron is provided with an activation function, the neurons can receive multiple inputs simultaneously and unify the inputs, then the multiple inputs are processed by the activation functions and output, a certain mapping relation exists between the inputs and the outputs, if the activation function in each neuron is a linear function, the mapping relation between the inputs and the outputs is linear, the neural network only combines the multiple inputs linearly and outputs the multiple inputs, namely the neural network lacks nonlinearity, and the approximation capability of complex functions is very limited.
In order to make the expression capability of the neural network for complex functions more powerful, a nonlinear activation function needs to be introduced for constructing the neural network. The nonlinear function is introduced for the neural network, corresponding to the function value to be fitted to the nonlinear function. Generally speaking, the function value of the nonlinear function fitted in the prior art is generally calculated by a general-purpose processor, which is low in efficiency. Even if a special fitting circuit is adopted, the required fitting interval is huge, the involved fitting parameters are numerous, the memory resource expense is high, the circuit area is large, and meanwhile, the data processing speed is difficult to meet the requirement of a neural network.
Disclosure of Invention
Aiming at the problems, in order to meet the requirement of the neural network on the nonlinearity, a whole set of solving measures for improving the data processing capacity of the neural network is provided on the basis of combining a special circuit with a scheme of only configuring a fitting operation circuit of a specific fitting interval to replace a scheme of configuring a fitting operation circuit of a whole interval, and the expenditure of hardware resources is obviously reduced.
To achieve the above object, according to a first aspect of the present invention, there is provided a data processing method applied to a neural network. Providing a multiplier, a fitting operation circuit and a function value mapping circuit, wherein the fitting operation circuit is used for calling fitting parameters to perform fitting operation on data; the function value mapping circuit is used for matching corresponding numerical values according to the indexes. At the same time, at least one specific fitting interval in the specific function definition domain is provided, the specific fitting interval corresponds to at least one group of fitting parameters, and the fitting operation circuit only processes data in the specific fitting interval; and provides input data x, which is a normalized floating point number, the input data x including significant digits, exponents, and symbols. The data processing method provided by the invention comprises the following steps:
Step S10, acquiring the input data x, and judging whether the input data x is positioned in a specific fitting interval according to effective numbers, indexes and symbols of the input data x;
if the input data x is positioned in a specific fitting interval, a fitting operation circuit is used for calling fitting parameters to perform fitting operation on the input data x, so that a fitting operation result is obtained, and a final operation result is obtained based on the fitting operation result;
if the input data x is outside the specific fitting interval, the step of directly calling the fitting operation circuit to process the input data x is skipped, and the step S20 is directly executed.
Step S20, shifting the input data x to obtain shifted data x'. The shifting process includes obtaining an exponent t of the shifted data x ', where t is an integer, calculating a difference between the exponent t and the exponent t of the input data x, and shifting a significant number of the input data x based on the difference to obtain a significant number of the shifted data x'.
Step S30, obtaining fitting part x based on the shift data x 1 Non-fitting portion x 2 Fitting part x 1 Non-fitting part x 2 The sum of (2) is equal to the shift data x'. Wherein the fitting part x 1 The significant number of (2) is equal to the fractional part of the significant number of the shift data x' plus the integer r, fitting part x 1 Is located within a specific fit interval; non-fitting portion x 2 The significant number of (2) is equal to the integer part of the significant number of the shift data x' minus the integer r.
Step S40, calling fitting parameters to the fitting part x by using a fitting operation circuit 1 Fitting operation is carried out to obtain a first operation result f (x 1 );
Using function value mapping circuit to non-fit part x 2 The mapping table is searched for the index, and the second operation result f (x 2 ) The method comprises the steps of carrying out a first treatment on the surface of the The mapping table includes non-fitting portions x 2 And non-fitting part x 2 Corresponding second operation result f (x 2 )。
Step S50, using multiplier to compute the first operation result f (x 1 ) And a second operation result f (x 2 ) And multiplying to obtain a final operation result.
The invention decomposes the input data x into fitting parts x 1 Non-fitting portion x 2 And respectively to the fitting part x through different circuits 1 Non-fitting portion x 2 And (5) processing. Specifically, the fitting part x is fitted by a fitting operation circuit 1 Fitting operation is carried out to obtain a first operation result f(x 1 ) The method comprises the steps of carrying out a first treatment on the surface of the And the function value mapping circuit is used for mapping the non-fitting part x 2 The mapping table is searched for the index, and the second operation result f (x 2 ) Then based on the first operation result f (x 1 ) And a second operation result f (x 2 ) And restoring the function fitting value of the specific function. Compared with the closest specific implementation scheme of fitting by using a fitting operation circuit covering a whole section in the prior art, the invention uses the function value mapping circuit to match the fitting operation circuit only provided with a very small specific fitting section to replace the fitting operation circuit provided with the whole section fitting section with high power consumption and multiple components, thereby greatly reducing the quantity of fitting parameters and further reducing the cost of hardware resources, particularly memory resources. Meanwhile, compared with the prior art, the fitting operation circuit provided by the invention only provided with the very small specific fitting interval has fewer fitting parameters, so that the time for selecting and matching the fitting parameters when the fitting operation circuit calls the fitting parameters can be shortened, the processing speed of data is improved as a whole, the data processing method is particularly applied to a neural network, and particularly when the neural network approximates to the function value of a specific function, the requirement of the neural network on nonlinearity is met, and the approximation capability of the neural network to complex functions is further improved.
Preferably, the specific fitting interval includes [ -2 [ t+n ,2 t+m ]N and m are positive integers. In a preferred embodiment, the integer r is generally 1. Therefore, the fitting part x 1 The fitting part x is known from the construction mode of (a) 1 The significant number of (2) is smaller than that of (2), fitting part x 1 The index of (2) is equal to t, fitting part x 1 The sign of (c) includes both positive and negative cases. Therefore, the fitting part x under the premise of keeping n and m both positive integers in the binary neural network processing system preferred by the invention 1 Must lie within a specific fit interval [ -2 [ t+n ,2 t+m ]Thereby not requiring the fitting part x 1 The fitting operation can be performed by performing additional processing, so that the processing speed of the method for data is further improved, and only a specific fitting interval < -2 > is required to be stored t+n ,2 t+m ]And corresponding fitting parameters reduce the cost of storage resources.
More preferably, the specific fitting interval includes a first fitting interval and a second fitting interval, and the first fitting interval includes [ -2 t+n ,-2 t-p ]The second fit interval includes [2 t-q ,2 t+m ]P and q are both non-negative integers. From the fitting part x 1 The fitting part x is known from the construction mode of (a) 1 Significant numbers of (2) are greater than 1, fitting portion x 1 The index of (2) is equal to t, fitting part x 1 The sign of (c) includes both positive and negative cases. Therefore, on the premise that p and q are both non-negative integers, the fitting portion x 1 Must lie within the first fitting interval [ -2 ] t +n ,-2 t-p ]Or a second fitting interval [2 ] t-q ,2 t+m ]Thereby reducing the number of fitting parameters even further to reduce the overhead of memory resources.
More preferably, m and n are equal to 1, and p and q are equal to 0. At the assurance fitting part x 1 On the premise of being positioned in a specific fitting interval, the specific fitting interval is fixed at the most convenient [ -2 ] of use t+1 ,2 t+1 ]Or [ -2 t+1 ,-2 t ]U[2 t ,2 t+1 ]Thereby reducing the number of fitting parameters to a locally optimal situation to reduce the overhead of storage resources.
Preferably, the non-fitting part x in the mapping table 2 Comprising at least one arithmetic series with a tolerance of 2 t . In the present invention, the mapping table does not need to store every non-fitting portion x within a particular function definition field 2 But only some specific values need to be stored. From the non-fitting part x 2 The construction of the non-fitting portion x is known 2 The significant numbers of (a) are integers, the non-fitting portion x 2 The index of (a) is t (t is an integer), and therefore the non-fitting portion x 2 Is an integer. At the same time fit fitting part x 1 Only one group of tolerance 2 is stored in the mapping table t The integer arithmetic progression of (2) can realize the processing of arbitrary input data x. Thus, by reducing the fitting portion x in the mapping table 2 Can reduce the cost of storage resources and can further reduce the function value mapping The radio circuit uses a non-fitting part x 2 Obtaining a second operation result f (x 2 ) Thereby accelerating the processing speed of the data processing method for the data.
To achieve the above object, according to a second aspect of the present invention, there is provided a data processing apparatus. Providing at least one specific fitting interval corresponding to the specific function, wherein the specific fitting interval corresponds to at least one group of fitting parameters; and provides input data x, which is a normalized floating point number, the input data x including significant digits, exponents, and symbols. The data processing device provided by the invention comprises:
the judging unit is used for judging whether the input data x is located in a specific fitting interval or not according to the effective numbers, indexes and symbols of the input data x.
The shifting unit is connected with the judging unit and is used for acquiring input data x outside the specific fitting interval and carrying out shifting processing on the input data x to obtain shifted data x'.
The splitting unit is connected with the shifting unit and is used for acquiring shifting data x 'and splitting the shifting data x' into fitting parts x 1 Non-fitting portion x 2 Fitting part x 1 Non-fitting part x 2 The sum of (2) is equal to the shift data x'.
A function value mapping circuit connected with the splitting unit for obtaining the non-fitting part x 2 And by non-fitting part x 2 Searching mapping table for index to obtain non-fitting part x 2 Corresponding second operation result f (x 2 ) The method comprises the steps of carrying out a first treatment on the surface of the The mapping table includes non-fitting portions x 2 And non-fitting part x 2 Corresponding second operation result f (x 2 )。
The fitting operation circuit is used for receiving input data x positioned in a specific fitting interval and calling fitting parameters to perform fitting operation on the input data x to obtain a fitting operation result; the fitting operation circuit is also used for receiving the fitting part x 1 And call fitting parameters to fitting part x 1 Fitting operation is carried out to obtain a first operation result f (x 1 )。
The multiplier is connected with the fitting operation circuit; the multiplier is used for receiving the fitting operation result and a fixed numerical value, wherein the fixed numerical value is equal to 1, and multiplying the fitting operation result and the fixed numerical value; the multiplier is also used for receiving the first operation result f (x 1 ) And a second operation result f (x 2 ) And the first operation result f (x 1 ) And a second operation result f (x 2 ) Multiplying.
The invention finally disassembles the input data x into the fitting part x through the shifting unit and the disassembling unit 1 Non-fitting part x 2 And the fitting part x is respectively connected with the function value mapping circuit through a fitting operation circuit 1 Non-fitting part x 2 Processing to obtain a first operation result f (x 1 ) And a second operation result f (x 2 ) And based on the first operation result f (x 1 ) And a second operation result f (x 2 ) And restoring the function fitting value of the specific function. Therefore, through the processing procedure, the fitting operation circuit with the very small specific fitting interval is matched with the function value mapping circuit to replace the fitting operation circuit with the very large fitting interval, so that the number of fitting parameters is reduced, and the cost of storage resources is reduced.
Preferably, the data processing apparatus further comprises a first multiplexer, the first multiplexer comprising an output and at least two inputs. One input end of the first multiplexer is connected with the judging unit, the other input end of the first multiplexer is connected with the splitting unit, and the output end of the first multiplexer is connected with the fitting operation circuit. The first multiplexer is used for acquiring input data x and/or fitting part x within a specific fitting interval 1 And selectively sending the result to a fitting operation circuit. By arranging the first multiplexer, when the fitting operation circuit performs the fitting operation of the pipelining, the fitting operation circuit is prevented from receiving a plurality of data simultaneously to cause operation errors, and the stability of the device is improved.
Preferably, the data processing apparatus further comprises a second multiplexer, the second multiplexer comprising an output and at least two inputs. One of the second multiplexersThe input end is connected with the function value mapping circuit, the other input end of the second multiplexer receives the fixed value, and the output end of the second multiplexer is connected with the multiplier. The second multiplexer is used for obtaining a second operation result f (x 2 ) And/or fixed values and optionally sent to the multiplier. By arranging the second multiplexer to selectively send the second operation result f (x 2 ) Or a fixed value, to make the two inputs received by the multiplier correspond.
To achieve the above object, according to a third aspect of the present invention, there is provided a computer-readable storage medium having stored thereon program code which, when executed by a processor, implements the steps of the data processing method in the above first aspect.
To achieve the above object, according to a fourth aspect of the present invention, there is provided a processor including the data processing apparatus in the above second aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a data processing method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a data processing apparatus according to an embodiment of the present invention;
FIG. 3 is a table of fitting parameters provided by an embodiment of the present invention;
FIG. 4 is another table of fitting parameters provided by an embodiment of the present invention;
FIG. 5 is a mapping table provided by an embodiment of the present invention;
FIG. 6 is another table of fitting parameters provided by an embodiment of the present invention;
FIG. 7 is another mapping table provided by an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order. The term "at least one" means one or more, and the term "plurality" means two or more, unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. It will be understood that when an element is referred to as being "coupled" to "or" connected "to another element or elements, it can be directly or indirectly connected to the other element or elements.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Fig. 1 is a schematic flow chart of a data processing method according to an embodiment of the invention. Specifically, the method comprises the following steps.
And S1, acquiring input data x. The input data x is a normalized floating point number, including significant digits, exponents, and signs. In a preferred embodiment of the present invention, the input data x may be an IEEE-754 floating point number.
And S2, judging whether the input data x is positioned in a specific fitting interval or not according to the effective numbers, indexes and symbols of the input data x. If the input data x is located in the specific fitting interval, executing step S3; if the input data x is outside the specific fitting interval, step S4 is performed.
And step S3, using a fitting operation circuit to call fitting parameters corresponding to the specific fitting interval to perform fitting operation on the input data x so as to obtain a fitting operation result.
And S4, performing shift processing on the input data x to obtain shift data x'. The shifting process includes obtaining an exponent t of the shifted data x ', where t is an integer, calculating a difference between the exponent t and the exponent t of the input data x, and shifting a significant number of the input data x based on the difference to obtain a significant number of the shifted data x'. Specifically, the exponent t of the shift data x' may be subtracted from the exponent of the input data x to obtain a difference value, and if the difference value is greater than zero, the effective number of the input data x is shifted to the left, where the number of the shifted bits is equal to the difference value; if the difference is smaller than zero, the significant digit of the input data x is shifted to the right, and the number of bits shifted to the right is equal to the difference. The index t of the shift data x' can be subtracted from the index of the input data x to obtain a difference value, if the difference value is smaller than zero, the effective number of the input data x is shifted left, and the number of the left shift is equal to the difference value; if the difference is greater than zero, the significant digit of the input data x is shifted to the right by a number of digits equal to the difference.
Step S5, splitting the shift data x' to obtain a fitting part x 1 Non-fitting portion x 2 Fitting part x 1 Non-fitting part x 2 The sum of (2) is equal to the shift data x'. Wherein the fitting part x 1 Is equal to the fraction of the significant number of the shifted data xAdding the integer r, fitting part x 1 Is located within a specific fit interval; non-fitting portion x 2 The significant number of (2) is equal to the integer part of the significant number of the shift data x' minus the integer r. In a preferred embodiment of the invention r is equal to 1.
Step S6, fitting part x 1 Non-fitting portion x 2 Respectively processing to obtain a first operation result f (x 1 ) And a second operation result f (x 2 ). Specifically, the fitting operation circuit is used to call the fitting parameters to the fitting part x 1 Fitting operation is carried out to obtain a first operation result f (x 1 ) The method comprises the steps of carrying out a first treatment on the surface of the Using function value mapping circuit to non-fit part x 2 Searching mapping table for index to obtain non-fitting part x 2 Corresponding second operation result f (x 2 ). Wherein the mapping table comprises non-fitting portions x 2 And non-fitting part x 2 Corresponding second operation result f (x 2 )。
Step S7, obtaining a first operation result f (x) 1 ) And a second operation result f (x 2 ) Is a product of (a) and (b).
Step S8: and outputting the fitting operation result in the step S3 or the product in the step S7 as a final operation result.
The prior art tends to configure a larger interval as the fit interval, e.g., for function 2 in an IEEE-754 single precision floating point number system x Fitting is performed, and the maximum value which can be represented by the IEEE-754 single-precision floating point number is 2 127 The fit interval is therefore often configured as [ -127,127]In order to ensure the accuracy of the fitting, the fitting interval is generally divided into a plurality of sub-intervals. If a subinterval is divided every 0.1, the fit interval is [ -127,127]It will be possible to divide into 2540 subintervals, so 2540 sets of fitting parameters are theoretically required to achieve a fit of the function, which is extremely large for storage resource usage. In the present invention, however, the function 2 x Fitting operation is carried out by only setting the fitting interval to be [ -2,2]In the same way for [ -2,2]The total of 40 sub-intervals can be known by dividing, so that 2 can be completed only by 40 groups of fitting parameters x 1 At [ -2,2]Fitting operation of (a)Then the function value mapping circuit is used for mapping the non-fitting part x 2 Find mapping table for index get 2 x 2 And multiplying the two to obtain 2 x 1 +x 2, i.e. the input data x is restored to be within [ -127,127]Is a function fit of the values.
From a memory resource perspective, memory resource overhead of about 2500 sets of fitting parameters is saved. In a system having a high requirement for fitting accuracy, the subinterval division interval is generally set to 0.1 or less; when 0.1 is taken as a common minimum subinterval standard, the invention saves at least two orders of magnitude intervals compared with the prior art, so the invention is quite considerable for saving storage resources. If the fitting parameters are not stored by using the storage resources, but are solidified in the circuit, compared with 2500 sets of fitting parameters needing to be solidified in the prior art, the invention can greatly reduce the area and the power consumption of the circuit.
In addition, in order to invoke the corresponding fitting parameters to perform the fitting operation, it is necessary to determine which sub-interval the input data x is located in, so that log is theoretically required in the prior art 2 2540 gates (gates) are used for judging subintervals, and the invention only needs log 2 40 gates. Therefore, the circuit area of the invention is significantly smaller than the prior art. Meanwhile, in the fitting operation of the pipelining, the invention uses less gates to judge, and the circuit delay (namely the fitting part x 1 The time to match the corresponding fitting parameters) is significantly lower than in the prior art.
Due to the second operation result f (x 2 ) Very close to the true value, the present invention uses the second operation result f (x 2 ) Restoring the function fitting value of the input data x has the advantage of high fitting accuracy.
In some embodiments of the present invention, the specific fit interval may be set to [ -2 t+n ,2 t+m ]M and n are positive integers. In other embodiments of the invention, a plurality of specific fit intervals may also be provided, e.g., the specific fit interval may be set to [ -2 [ t+n ,-2 t-p ]U[2 t-q ,2 t+m ]P and q are both non-negative integers. In a preferred embodiment of the invention, m and n are generally taken to be 1, and p and q are taken to be 0. In some embodiments of the present invention, the particular fit interval may also be configured as an open interval or a half-open half-closed interval.
For example, when the exponent t of the shift data x' is equal to 2, the particular fit interval may be set to [ -8,8], (-8, 8), etc. The specific fit interval may also be set to [ -8, -4] U [4,8], (-8, -4) U (4, 8), (-8, -4] U [4, 8), etc., and will not be described in detail herein. In a preferred embodiment of the invention, the specific fit interval comprises a plurality of sub-intervals, each corresponding to a set of fit parameters.
In a preferred embodiment of the present invention, the non-fitting portion x in the mapping table 2 Forming at least one arithmetic series with a tolerance of 2 t . It should be noted that the tolerance is equal to 2 t Or is equal to-2 t Depending on how the first and last terms of the arithmetic series are defined. Thus, the tolerance is equal to-2 t The arithmetic progression of (c) should be regarded as substantially the same as the present invention.
For example, when the exponent t of the shift data x' is equal to 2, the non-fitting portion x in the mapping table 2 The final and final terms that make up the arithmetic series are …, -8, -4,0,4,8, …, and the final and final terms of the arithmetic series can be determined from the maximum and minimum values that the system can represent. For example, a single precision floating point number may represent a maximum of 2 127 If the mapping table indicates e x Due to the mapping relation of e 88 Has exceeded 2 127 Combining the above specific fitting intervals [ -8,8 [ -8 ]]To make the maximum value capable of fitting reach e 88 The last term of the arithmetic series should be 80, and similarly, the first term of the arithmetic series should be-80.
Fig. 2 is a schematic diagram of a data processing apparatus 200 according to an embodiment of the invention. The data processing apparatus 200 includes: the device comprises a judging unit 210, a shifting unit 220, a splitting unit 230, a function value mapping circuit 240, a fitting operation circuit 250, a multiplier 260, a first multiplexer 270 and a second multiplexer 280.
The judging unit 210 is connected with the shifting unit 220; the shift unit 220 is connected to the split unit 230; the splitting unit 230 is connected to the function value mapping circuit 240; one input end of the first multiplexer 270 is connected with the judging unit 210, the other input end is connected with the splitting unit 230, and the output end of the first multiplexer 270 is connected with the fitting operation circuit 250; one input end of the second multiplexer 280 is connected with the function value mapping circuit 240, the other input end receives the fixed value 1, and the output end thereof is connected with the multiplier 260; multiplier 260 is also coupled to fitting circuit 250.
The determining unit 210 is configured to receive the input data x, and determine whether the input data x is located in a specific fitting interval according to significant digits, exponents, and signs of the input data x. If the input data x is within the specific fitting interval, the determining unit 210 sends the input data x to the first multiplexer 270; if the input data x is outside the specific fitting interval, the determining unit 210 sends the input data x to the shifting unit 220.
The shift unit 220 is configured to perform shift processing on the input data x to obtain shift data x ', and send the shift data x' to the splitting unit 230.
The splitting unit 230 is used for splitting the shift data x' into fitting parts x 1 Non-fitting portion x 2 Fitting part x 1 Non-fitting part x 2 The sum of (2) is equal to the shift data x'. Fitting part x 1 Send to the first multiplexer 270 and to fit the non-fitting portion x 2 To the function value mapping circuit 240.
The function value mapping circuit 240 is used for using the non-fitting part x 2 Searching mapping table for index to obtain non-fitting part x 2 Corresponding second operation result f (x 2 ) And the second operation result f (x 2 ) To the second multiplexer 280.
The first multiplexer 270 is used for receiving the input data x and/or the fitting part x within a specific fitting interval 1 The selection is sent to the fitting circuit 250.
The fitting operation circuit 250 is configured to receive the input data x within a specific fitting interval and perform fitting operation to obtain a fittingAn operation result; the fitting operation circuit 250 is also used for receiving the fitting part x 1 Fitting operation is carried out to obtain a first operation result f (x 1 ). In a preferred embodiment of the invention, the fitting circuit comprises a multiplier and an adder, the cooperation of which is used to perform the polynomial fitting operation. In other embodiments, a multiplier-adder may be used instead of the multiplier and adder to perform the polynomial operation. In a preferred embodiment, the polynomial fitting operation is a binomial fitting operation, but the term degree of the fitting operation is not particularly limited in the present invention.
The second multiplexer 280 is configured to receive the second operation result f (x 2 ) And/or a fixed value of 1 to multiplier 260. It is obvious that the fixed value may be either floating or integer.
Multiplier 260 is configured to receive the fixed value and the fitting result and multiply the two; multiplier 260 is also configured to receive the first operation result f (x 1 ) And a second operation result f (x 2 ) And multiplies the two.
Logic circuits that are selected to transfer data from multiple data channels to a unique common channel to perform the data selection function can be considered as simple permutations of a multiplexer (multiplexor). For example, a data selector, a multiplexer may be used instead of the multiplexer described above.
For ease of understanding, the process of data processing is described below with data processing apparatus 200 in connection with specific functions and input data.
Providing a function for fitting as e x Setting the specific fitting interval as [ -8,8]The specific fit interval is divided into a plurality of sub-intervals, each sub-interval corresponding to a set of fit parameters. Please refer to fig. 3, which illustrates the partial fitting parameters provided in this embodiment.
An IEEE-754 floating-point number 8 is provided as input data, with a significant number of 1, an exponent of 3, and a sign of positive, which may be represented as 1*2 3 (in binary).
The determining unit 210 receives the input data 8, determines that it is within a certain fitting interval [ -8,8], sends it to the first multiplexer 270, and the first multiplexer 270 sends it to the fitting operation circuit 250.
The fitting operation circuit 250 receives the input data 8 and determines sub-intervals [6, 8] of the specific fitting interval]And calling the fitting parameter a, the fitting parameter b and the fitting parameter c to perform binomial fitting operation on the fitting parameter a, the fitting parameter b and the fitting parameter c to obtain a fitting operation result. Wherein the fitting parameter a is 1400, the fitting parameter b is-19400, the fitting parameter c is 68800, and the formula for performing binomial fitting operation is ax 2 +bx+c, thus, the fitting operation result is 3200. It should be appreciated that to ensure the accuracy of the fitting operation, the fitting parameters may be iterated or debugged a number of times. The present embodiment shows trial-and-error fitting parameters for demonstration for the purpose of illustrating the fitting operation procedure, and should not be construed as fitting parameters in the optimal situation when the present invention is actually used.
The multiplier 260 obtains the fitting operation result, obtains a fixed value (equal to 1) from the second multiplexer 280, and multiplies the two to obtain a product of the two as a final operation result. In other embodiments of the present invention, the fitting operation result may be directly output.
In another embodiment of the invention, a function e for fitting is provided x Setting a specific fitting interval as [ -8, 8), the specific fitting interval being divided into a plurality of sub-intervals, each sub-interval corresponding to a set of fitting parameters. Please refer to fig. 4, which illustrates the partial fitting parameters provided in this embodiment.
An IEEE-754 floating-point number 8 is provided as input data, with a significant number of 1, an exponent of 3, and a sign of positive, which may be represented as 1*2 3 (in binary).
The judging unit 210 receives the input data 8, judges that it is not located in the specific fitting interval [ -8, 8), and sends it to the shifting unit 220.
The shift unit 220 shifts the input data 8 to obtain shifted data. Specifically, the index of shift data may be set to 2. Firstly, subtracting the index of the shift data from the index of the input data to obtain a difference value of 1, and then adding the input numberThe significant digit of the data is shifted left by 1 bit to obtain the significant digit of the shifted data. Thus, the shift data can be expressed as 10×2 2 (in binary).
The splitting unit 230 acquires the shift data and splits it into a fitting part and a non-fitting part. Specifically, the decimal part (equal to 0) of the significant figure of the shift data is added to 1 as the significant figure of the fitting section. Thus, the fitting portion may be denoted as 1*2 2 (represented in binary, 4 versus decimal). The integer part of the significant number of the shift data is subtracted by 1 as the significant number of the non-fitting portion. Thus, the non-fitting portion may be represented as 1*2 2 (represented in binary, 4 versus decimal).
The splitting unit 230 sends the fitting part to the fitting operation circuit 250 through the first multiplexer 270, and the fitting operation circuit determines that the fitting operation circuit is located in the subinterval [4,6 ] of the specific fitting interval, and invokes the fitting parameter to perform fitting operation on the subinterval to obtain a first operation result. Wherein the fitting parameter a is equal to 32, the fitting parameter b is equal to-202, and the fitting parameter c is equal to 350. The formula for performing the binomial fit operation is ax 2 +bx+c, thus, the first operation result is 54. It should be appreciated that to ensure the accuracy of the fitting operation, the fitting parameters may be iterated or debugged a number of times. The fitting parameters shown in this embodiment are given for illustrative purposes only to illustrate the fitting operation procedure, and are not to be construed as fitting parameters in the optimal situation when the present invention is actually used.
The splitting unit 230 further sends the non-fitting part to the function value mapping circuit 240, and the function value mapping circuit 240 searches the mapping table with the non-fitting part as an index, so as to obtain a corresponding second operation result of 54.6. Please refer to fig. 5, which is a mapping table provided in an embodiment of the present invention. The non-fitting portions of the mapping table form an arithmetic series with a first term of 0, a last term of 80 and a tolerance of 4. In other embodiments, the mapping table may omit sets of data, or may add sets of data.
The second multiplexer 280 obtains the second operation result and sends the second operation result to the multiplier 260, and the multiplier 260 also obtains the first operation result and multiplies the first operation result by the second operation result to obtain a product 2948.4 as a final operation result.
In another embodiment of the present invention, a function of 2 is provided for fitting x The specific fitting interval is set to (-2, -1) U (1, 2). The specific fitting interval is divided into a plurality of subintervals, each subinterval corresponding to a set of fitting parameters. Please refer to fig. 6, which illustrates the partial fitting parameters provided in this embodiment.
Providing input data equal to-4.5, with a significant number of 1.001, an exponent of 2, and a sign of negative, which may be expressed as-1.001 x 2 2 (in binary).
The determining unit 210 receives the input data, determines that it is located outside the specific fitting interval (-2, -1) U (1, 2), and sends it to the shifting unit 220. The shift unit 220 performs shift processing on the shift data to obtain shift data. Specifically, the index of the shift data may be set to 0. First, the exponent of the shift data is subtracted from the exponent of the input data to obtain a difference of 2, and then the significant digit of the input data is shifted left by 2 bits as the significant digit of the shift data. Thus, the shift data can be represented as-100.1×2 0 (in binary).
The splitting unit 230 acquires the shift data and splits it into a fitted portion and a non-fitted portion. Specifically, the decimal part of the significant figure of the shift data is added to 1 as the fitting portion, and thus, the fitting portion can be expressed as-1.1x2 0 (expressed in binary, equivalent to-1.5 in decimal). The integer part of the significant number of the shift data is subtracted by 1 as a non-fitting part, and thus the non-fitting part can be expressed as-11×2 0 (expressed in binary, corresponding to-3 in decimal).
The fitting operation circuit 250 obtains the fitting portion through the first multiplexer 270, determines that the fitting portion is located in the subinterval [ -1, 5, -1) of the specific fitting interval, and invokes the fitting parameter to perform fitting operation on the fitting portion, so as to obtain a first operation result. Wherein the fitting parameter a is equal to 0.2, the fitting parameter b is equal to 0.5, the fitting parameter c is equal to 0.7, and the formula for performing binomial fitting operation is ax 2 +bx+c, so the first operation result is 0.4. It should be appreciated that to ensure a fit operationThe calculated precision and fitting parameters are subjected to multiple iterations or debugging. The fitting parameters shown in this embodiment are given for illustrative purposes only to illustrate the fitting operation procedure, and are not to be construed as fitting parameters in the optimal situation when the present invention is actually used.
The function value mapping circuit 240 receives the non-fitting portion, and searches the mapping table with the non-fitting portion as an index, so as to finally obtain a second operation result corresponding to the non-fitting portion equal to 0.125. The correspondence between the non-fitting portion and the corresponding second operation result stored in the mapping table is shown in fig. 7. The non-fitting portions in the mapping table form an arithmetic progression with-1 for the first term, -86 for the last term, and-1 for the tolerance. In other embodiments, the mapping table may omit sets of data, or may add sets of data.
The multiplier 260 obtains the first operation result from the fitting operation circuit 250 and the second operation result from the function value mapping circuit 240 through the second multiplexer 280. The multiplier 260 multiplies the obtained first operation result and second operation result, and takes the product of the two as a final operation result, which is equal to 0.05.
It is obvious that the index of the shift data is not limited to 2 or 0 shown above, but can be adjusted according to the actual implementation. Similarly, the selection of the specific fitting interval is not limited to the above-described case, but may be determined according to the index of the shift data, and the manner of determining the specific fitting interval is described in detail above and will not be repeated here. The function of fitting is also not limited to e shown in the above embodiment x Or 2 x . In other embodiments, the function that is fitted may be any exponential function.
The above-described fitting parameters and the division of sub-intervals shown in the fitting parameter table are merely exemplary data and are not to be construed as a specific limitation of the invention to fitting parameters or individual fitting sub-intervals. The fitting parameters or the ranges of the subintervals can be adjusted according to the requirements for fitting accuracy. Similarly, the non-fitting portion of the mapping table and the second operation result are also exemplary data.
Fig. 8 is a schematic structural diagram of a data processing apparatus 800 according to an embodiment of the present invention. The data processing device 800 as shown in fig. 8 includes one or more processors 810, a communication interface 820, and a memory 830. Processor 810, communication interface 820, and memory 830 may be connected by a bus, or may communicate by other means such as wireless transmission. The embodiment of the present invention is exemplified by connection via bus 840. The memory 830 is configured to store program codes, and the processor 810 is provided with the data processing apparatus disclosed in the foregoing embodiment, and is configured to execute the program codes stored in the memory 830, where the program codes are executed by the processor 810 to implement the steps of the data processing method disclosed in the foregoing embodiment.
It should be appreciated that in embodiments of the present invention, the processor 810 may be a central processing unit (Central Processing Unit, CPU), which may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Communication interface 820 may be a wired interface (e.g., an ethernet interface) or a wireless interface (e.g., a cellular network interface or using a wireless local area network interface) for communicating with other modules or apparatus devices. For example, the communication interface 820 in the embodiment of the present application may be specifically configured to receive input data input by a user; or to receive data from an external device, etc.
Memory 830 may include Volatile Memory (Volatile Memory), such as random access Memory (Random Access Memory, RAM); the Memory may also include a Non-Volatile Memory (Non-Volatile Memory), such as a Read-Only Memory (ROM), a Flash Memory (Flash Memory), a Hard Disk (HDD), or a Solid State Drive (SSD); the memory may also comprise a combination of the above types of memories.
It should be noted that fig. 8 is only one possible implementation of the embodiment of the present invention, and in practical applications, the data processing apparatus may further include more or fewer components, which is not limited herein. For details not shown or described in the embodiments of the present invention, reference may be made to the related descriptions in the foregoing method embodiments, which are not repeated here.
Those of ordinary skill in the art will appreciate that the elements and steps of a process described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the elements and steps of a process have been described above generally in terms of functionality for clarity of understanding the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working procedures of the terminal device and unit described above may refer to the corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In several embodiments provided in the present application, it should be understood that the disclosed terminal device and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present invention.
In addition, each functional unit in each embodiment of the present invention may be integrated in one data processing apparatus, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims (10)

1. The data processing method is applied to a neural network, and provides a multiplier, a fitting operation circuit and a function value mapping circuit, wherein the fitting operation circuit is used for calling fitting parameters to carry out fitting operation on data, and the function value mapping circuit is used for matching corresponding numerical values according to indexes; providing at least one specific fit interval within a specific function definition domain, the specific fit interval corresponding to at least one set of fit parameters; providing input data x, wherein the input data x is a standardized floating point number, and the input data x comprises significant digits, exponentials and signs, and the fitting operation circuit is characterized in that only data in the specific fitting interval are processed;
the data processing method comprises the following steps:
step S10, acquiring the input data x, and judging whether the input data x is positioned in the specific fitting interval according to the effective numbers, indexes and symbols of the input data x;
if the input data x is located in the specific fitting interval, performing fitting operation on the input data x by using the fitting operation circuit to obtain a fitting operation result, and obtaining a final operation result based on the fitting operation result;
If the input data x is located outside the specific fitting interval, skipping the step of directly calling the fitting operation circuit to process the input data x, and directly executing the step S20;
step S20, performing shift processing on the input data x to obtain shift data x'; the shift processing includes obtaining an exponent t of the shift data x', where t is an integer, and then calculating a difference between the exponent of the input data x and the exponent t; shifting the effective number of the input data x based on the difference value to obtain the effective number of the shift data x';
step S30, acquiring fitting part x based on the shift data x 1 Non-fitting portion x 2 The fitting part x 1 To the non-fitting part x 2 Is equal to the shifted data x'; wherein the fitting part x 1 The significant number of (2) is equal to the fractional part of the significant number of the shift data x' plus an integer r, the fitting part x 1 Is located within the specific fitting interval; the non-fitting part x 2 The significant number of (2) is equal to the integer part of the significant number of the shift data x' minus the integer r;
step S40, using the fitting operation circuit to fit the fitting part x 1 Fitting operation is carried out to obtain a first operation result f (x 1 );
Using the function value mapping circuit to map the non-fitting part x 2 The mapping table is searched for the index, and the second operation result f (x 2 ) The method comprises the steps of carrying out a first treatment on the surface of the The mapping table comprises the non-fitting part x 2 And the non-fitting part x 2 Corresponding to the second operation result f (x 2 );
Step S50, receiving the first operation result f (x) by using the multiplier 1 ) And the second operation result f (x 2 ) And performing multiplication operation to obtain a final operation result.
2. The data processing method according to claim 1, wherein the specific fitting interval includes [ -2 [ t+n ,2 t +m ]N and m are positive integers.
3. The data processing method according to claim 2, wherein the specific fitting interval includes a first fitting interval and a second fitting interval, the first fitting interval including [ -2 [ t+n ,-2 t-p ]The second fitting interval includes [2 ] t-q ,2 t+m ]P and q are both non-negative integers.
4. A data processing method according to claim 3, wherein m and n are equal to 1, and p and q are equal to 0.
5. The data processing method according to claim 1, wherein the non-fitting portion x in the mapping table 2 Comprising at least one arithmetic series having a tolerance of 2 t
6. A data processing apparatus providing at least one specific fit interval within a specific function definition domain, the specific fit interval corresponding to at least one set of fit parameters; providing input data x, said input data x being a normalized floating point number, said input data x comprising significant digits, exponents, and signs, said data processing apparatus comprising:
The judging unit is used for judging whether the input data x is positioned in the specific fitting interval according to the effective numbers, indexes and symbols of the input data x;
the shifting unit is connected with the judging unit and is used for acquiring the input data x outside the specific fitting interval and carrying out shifting processing on the input data x to obtain shifted data x';
the splitting unit is connected with the shifting unit and is used for acquiring the shifting data x 'and splitting the shifting data x' into fitting parts x 1 Non-fitting portion x 2 The fitting part x 1 To the non-fitting part x 2 Is equal to the shifted data x';
the function value mapping circuit is connected with the splitting unit and is used for acquiring the non-fitting part x 2 And with the non-fitting part x 2 Searching a mapping table for indexes to finally obtain the non-fitting part x 2 Corresponding second operation result f (x 2 ) The method comprises the steps of carrying out a first treatment on the surface of the The mapping table comprises the non-fitting part x 2 And the non-fitting part x 2 Corresponding to the second operation result f (x 2 );
The fitting operation circuit is used for receiving input data x positioned in the specific fitting interval and calling the fitting parameters to perform fitting operation on the input data x to obtain a fitting operation result; the fitting operation circuit is also used for receiving the fitting part x 1 And call the fitting parameters to the fitting part x 1 Fitting operation is carried out to obtain a first operation result f (x 1 );
Multiplier, the multiplierThe fitting operation circuit is connected with the fitting operation circuit; the multiplier is used for receiving the fitting operation result and a fixed numerical value, wherein the fixed numerical value is equal to 1, and multiplying the fitting operation result and the fixed numerical value; the multiplier is further configured to receive the first operation result f (x 1 ) And the second operation result f (x 2 ) And compares the first operation result f (x 1 ) And the second operation result f (x 2 ) Multiplying.
7. The data processing apparatus according to claim 6, further comprising a first multiplexer, the first multiplexer including an output terminal and at least two input terminals, one of the input terminals of the first multiplexer being connected to the judging unit, the other input terminal of the first multiplexer being connected to the splitting unit, the output terminal of the first multiplexer being connected to the fitting operation circuit; the first multiplexer is used for acquiring the fitting part x through the input end thereof 1 And/or the input data x located in the specific fitting interval is selected and sent to the fitting operation circuit.
8. The data processing apparatus according to claim 6, further comprising a second multiplexer, the second multiplexer comprising an output and at least two inputs, the input of the second multiplexer being coupled to the function value mapping circuit, the other input of the second multiplexer receiving the fixed value, the output of the second multiplexer being coupled to the multiplier, the second multiplexer being configured to obtain the second operation result f (x 2 ) And/or the fixed value and selectively sent to the multiplier.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a program code which, when executed by a processor, implements the steps of the data processing method according to any one of claims 1 to 5.
10. A processor comprising a data processing apparatus as claimed in any one of claims 6 to 8.
CN202010000224.8A 2020-01-02 2020-01-02 Data processing method, device, processor and computer readable storage medium Active CN111191779B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010000224.8A CN111191779B (en) 2020-01-02 2020-01-02 Data processing method, device, processor and computer readable storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010000224.8A CN111191779B (en) 2020-01-02 2020-01-02 Data processing method, device, processor and computer readable storage medium

Publications (2)

Publication Number Publication Date
CN111191779A CN111191779A (en) 2020-05-22
CN111191779B true CN111191779B (en) 2023-05-30

Family

ID=70708140

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010000224.8A Active CN111191779B (en) 2020-01-02 2020-01-02 Data processing method, device, processor and computer readable storage medium

Country Status (1)

Country Link
CN (1) CN111191779B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115469829B (en) * 2022-10-28 2023-07-04 摩尔线程智能科技(北京)有限责任公司 Arithmetic device and exponent arithmetic method based on arithmetic circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107247992A (en) * 2014-12-30 2017-10-13 合肥工业大学 A kind of sigmoid Function Fitting hardware circuits based on row maze approximate algorithm
CN108154224A (en) * 2018-01-17 2018-06-12 北京中星微电子有限公司 For the method, apparatus and non-transitory computer-readable medium of data processing
CN108898216A (en) * 2018-05-04 2018-11-27 中国科学院计算技术研究所 Activation processing unit applied to neural network
CN109657788A (en) * 2018-12-18 2019-04-19 北京中科寒武纪科技有限公司 Data processing method, device and Related product

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11687762B2 (en) * 2018-02-27 2023-06-27 Stmicroelectronics S.R.L. Acceleration unit for a deep learning engine

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107247992A (en) * 2014-12-30 2017-10-13 合肥工业大学 A kind of sigmoid Function Fitting hardware circuits based on row maze approximate algorithm
CN108154224A (en) * 2018-01-17 2018-06-12 北京中星微电子有限公司 For the method, apparatus and non-transitory computer-readable medium of data processing
CN108898216A (en) * 2018-05-04 2018-11-27 中国科学院计算技术研究所 Activation processing unit applied to neural network
CN109657788A (en) * 2018-12-18 2019-04-19 北京中科寒武纪科技有限公司 Data processing method, device and Related product

Also Published As

Publication number Publication date
CN111191779A (en) 2020-05-22

Similar Documents

Publication Publication Date Title
US20210349692A1 (en) Multiplier and multiplication method
US4616330A (en) Pipelined multiply-accumulate unit
CN110221808B (en) Vector multiply-add operation preprocessing method, multiplier-adder and computer readable medium
US6601077B1 (en) DSP unit for multi-level global accumulation
CN106708468B (en) Division operation device
CN110796247B (en) Data processing method, device, processor and computer readable storage medium
CN110222833B (en) Data processing circuit for neural network
Rao et al. FPGA implementation of complex multiplier using minimum delay Vedic real multiplier architecture
CN111191779B (en) Data processing method, device, processor and computer readable storage medium
Kumar et al. New algorithm for signed integer comparison in $\{2^{n+ k}, 2^{n}-1, 2^{n}+ 1, 2^{n\pm 1}-1\} $ and its efficient hardware implementation
Basilakis et al. Efficient parallel binary operations on homomorphic encrypted real numbers
CN111191766B (en) Data processing method, device, processor and computer readable storage medium
JPH09325955A (en) Square root arithmetic circuit for sum of squares
Matutino et al. An efficient scalable RNS architecture for large dynamic ranges
CN113672196B (en) Double multiplication calculating device and method based on single digital signal processing unit
CN113805846A (en) Modulo arithmetic method, circuit, electronic device and computer readable storage medium
CN109992242B (en) Operation method and device based on multiplier
JP2021501406A (en) Methods, devices, and systems for task processing
GB2530883A (en) Implementing a square root operation in a computer system
US20210064340A1 (en) Arithmetic circuit
CN111142840A (en) Data calculation method and device based on FPGA
Hossain et al. A fast and compact binary to BCD converter circuit
Kumar et al. Fast Approximate Matrix Multiplier based on Dadda Reduction and Carry Save Ahead Adder
US20240118866A1 (en) Shift array circuit and arithmetic circuit including the shift array circuit
RU2751802C1 (en) Modulo multiplier

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20210209

Address after: 311201 No. 602-11, complex building, 1099 Qingxi 2nd Road, Hezhuang street, Qiantang New District, Hangzhou City, Zhejiang Province

Applicant after: Zhonghao Xinying (Hangzhou) Technology Co.,Ltd.

Address before: 518057 5-15, block B, building 10, science and technology ecological park, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province

Applicant before: Shenzhen Xinying Technology Co.,Ltd.

SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant