CN108390761B - Hardware implementation method of dual-domain modular inversion - Google Patents
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Abstract
The invention discloses a hardware implementation method of dual-domain modular inversion, and relates to the technical field of information security. The method adopts hardware description language to construct a modular inverse control state machine and modular addition, modular subtraction and shift operation units of two finite fields, and calls the modular addition, modular subtraction and shift operation units of the two finite fields through the modular inverse control state machine, and hardware realizes double-field modular inverse operation of two finite fields of a prime field and a binary field.
Description
Technical Field
The invention relates to the technical field of information security, in particular to a hardware implementation method of dual-domain modular inversion.
Background
With the development of computer networks and information technologies, information security plays an increasingly important role in various fields, wherein cryptography becomes the core of the information security technology, and Elliptic Curve Cryptography (ECC) is an emerging public key cryptosystem. Compared with the traditional RSA algorithm, the ECC has the advantages of shorter key length, less storage and quicker calculation under the condition of keeping the same security strength. The technical advantage of ECC is widely concerned by the cryptographic field and the information security industry, and has good application prospect.
At present, the domestic ECC algorithm is an SM2 algorithm, the main operation of the ECC (SM2) algorithm is finite field arithmetic operation, and the related finite field operation comprises two types: prime and binary domains. In the existing application-specific integrated circuit related to the ECC (SM2) algorithm, the finite field modular inversion operation is a relatively important step in the ECC (SM2) algorithm, and the hardware modular inversion can greatly improve the speed of implementing the ECC (SM2) algorithm, but the chip for implementing the hardware finite field modular inversion is fewer, especially the dual-field modular inversion including two finite fields, namely a prime field and a binary field.
Disclosure of Invention
The present invention is directed to a hardware implementation method of dual-domain modular inversion, so as to solve the foregoing problems in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a hardware implementation method of dual-domain modular inversion comprises the following steps:
s1, modeling an inverse control state machine and a basic operation unit by adopting a hardware description language structure, wherein the basic operation unit comprises: the device comprises a shift operation unit, a modulo addition operation unit of a prime field and a binary field, and a modulo subtraction operation unit of the prime field and the binary field;
and S2, the modular inversion control state machine realizes the dual-domain modular inversion operation of two finite domains of the prime domain and the binary domain by calling modular addition, modular subtraction and shift operation units of the prime domain and the binary domain according to the modular inversion algorithm flow of the prime domain and the binary domain through hardware.
Preferably, in S1, the hardware description language is verilog.
Preferably, the prime domain and binary domain modular inversion algorithm flow is implemented according to the following two stages:
the first stage is as follows: approximate modular inversion phase with element a2 in the Montgomery domainmThe sum modulus p is input, and an intermediate result is obtained as a-12k-mmod p and a parameter k, which is implemented in hardware by a modulo inverse control state machine by invoking modulo addition, modulo subtraction and shift arithmetic units of a prime field and a binary field, where a2mIs an element in the Montgomery domain, p is a modulus, m is a digit number, n is the most significant bit of p, m ≧ n (2)n-1≤p≤2n)；
And a second stage:a correction stage for outputting the intermediate result a-12k-mmod p to the final result a-12mmod p, this stage can be implemented in hardware or in software calling modular multiplication.
More preferably, the first stage is carried out as follows:
s201, taking the variables u, v, x1, x2 and k, wherein the initial value of the variable u is a2mThe initial value of the variable v is p, the initial value of x1 is 1, the initial value of x2 is 0, and the initial value of k is 0;
s202, judging the lower three bits of the variable v:
if the lowest bit of v is 0, calling a shift operation unit to shift v by one bit to the right, shift x1 by one bit to the left, and k is k + 1;
if the lowest two bits of v are 0, calling a shift operation unit to shift v by two bits to the right, shift x1 by two bits to the left, and shift k to k + 2;
if the lowest three bits of v are 0, calling a shift operation unit to shift v to the right by three bits, x1 to the left by three bits, and k is k + 3;
s203, judging the lower three bits of u:
if the lowest bit of u is 0, calling a shift operation unit to shift u by one bit to the right, x2 by one bit to the left, and k is k + 1;
if the lowest two bits of u are 0, calling a shift operation unit, shifting u by two bits to the right, shifting x2 by two bits to the left, and setting k as k + 2;
if the lowest three bits of u are 0, calling a shift operation unit to shift u to the right by three bits, x2 to the left by three bits, and k is k + 3;
s204, judging the current domain,
if the current domain is the prime domain, the modulo addition of the prime domain is called, and the modulo reduction operation unit calculates an intermediate variable: x-v-u, y-u-v, z-x 1+ x2, and judges u, v: if v > u, calling a shift operation unit to perform shift operation, wherein v is shifted to the right by one bit, x1 is shifted to the left by one bit, x1 is shifted to the left by one bit, x2 is z, and k is k + 1; if u > v, calling a shift operation unit to perform shift operation, wherein u is right shifted by one, x1 is z, x2 is x2 is left shifted by one, and k is k + 1;
if the current domain is a binary domain, calling a modular addition and modular subtraction operation unit of the binary domain to calculate an intermediate variable: x ^ v ^ u, z ^ x1^ x2, and determining deg (v) and deg (u), where deg (u), deg (v) represent u, v degrees: if deg (v) deg (u), calling the shift operation unit to perform shift operation, wherein v is shifted right by one bit, x1 is shifted left by one bit, x2 is shifted left by one bit, and k is shifted k + 1; if deg (u) deg (v), calling the shift operation unit to perform shift operation, where u equals x shifts right by one bit, x1 equals z, x2 equals x2 shifts left by one bit, and k equals k + 1;
s205, if v is not equal to 0, returning to S202;
s206, judging the current domain,
if the current domain is a prime domain, outputting an operation result of the prime domain modulo inversion and a parameter k: if x1> p, result is x 1-p; if x1< p, result ═ x 1;
if the current domain is a binary domain, calling a binary domain modulo addition, modulo subtraction and shift operation unit, and calculating an intermediate variable: x is p ^ x1, y is 1 and is left shifted by m bits, z is (2 ^ p) ^ x 1; and outputting a binary domain modulo inverse operation result and a parameter k: if y is more than or equal to x, result is x; if y is more than or equal to z, result is z; if none of the above conditions is met, result is x 1.
The invention has the beneficial effects that: the embodiment of the invention provides a hardware realization method of double-domain modular inversion, which adopts a hardware description language to construct a modular inversion control state machine and modular addition, modular subtraction and shift operation units of two finite domains, and the modular addition, modular subtraction and shift operation units of the two finite domains are called by the modular inversion control state machine, so that the hardware realizes the double-domain modular inversion operation of two finite domains of a prime domain and a binary domain.
Drawings
FIG. 1 is a diagram of a hardware architecture for implementing a dual-domain modular inverse operation;
fig. 2 is a basic flow chart of the implementation of the dual-domain modulo inverse control state machine.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, an embodiment of the present invention provides a hardware implementation method for dual-domain modular inversion, including the following steps:
s1, modeling an inverse control state machine and a basic operation unit by adopting a hardware description language structure, wherein the basic operation unit comprises: the device comprises a shift operation unit, a modulo addition operation unit of a prime field and a binary field, and a modulo subtraction operation unit of the prime field and the binary field;
and S2, the modular inversion control state machine realizes the dual-domain modular inversion operation of two finite domains of the prime domain and the binary domain by calling modular addition, modular subtraction and shift operation units of the prime domain and the binary domain according to the modular inversion algorithm flow of the prime domain and the binary domain through hardware.
Because the basic operation unit called by the algorithm of the binary domain and the prime domain modular inversion is a basic unit which can be realized by hardware such as modular addition, modular subtraction and shifting, and the main flow of the algorithm of the prime domain and the binary domain modular inversion is basically consistent, in the embodiment of the invention, the modular inversion of the two finite domains of the prime domain and the binary domain is realized by the hardware by constructing a control state machine and the basic operation unit of the prime domain and the binary domain and calling the modular addition, modular subtraction and shifting operation units of the prime domain and the binary domain according to the main flow of the algorithm of the two finite domains of the prime domain and the binary domain by the control state machine, so that the speed of realizing the algorithm can be greatly improved, logic resources can be saved, and the area can be saved.
In a preferred embodiment of the present invention, in S1, the hardware description language may be verilog.
Since Verilog is a basic language for hardware design and can meet the design requirements of mainstream hardware at present, the hardware description language is adopted in the embodiment of the present invention.
Other description languages may also be used for hardware design, as will be appreciated by those skilled in the art.
In another preferred embodiment of the present invention, the modular inversion algorithm flow of the prime domain and the binary domain can be implemented in two stages as follows:
the first stage is as follows: approximate modular inversion phase with element a2 in the Montgomery domainmThe sum modulus p is input, and an intermediate result is obtained as a-12k-mmod p and a parameter k, which is implemented in hardware by a modulo inverse control state machine by invoking modulo addition, modulo subtraction and shift arithmetic units of a prime field and a binary field, where a2mIs an element in the Montgomery domain, p is a modulus, m is a digit number, n is the most significant bit of p, m ≧ n (2)n-1≤p≤2n)；
And a second stage: a correction stage for outputting the intermediate result a-12k-mmod p to the final result a-12mmod p, this stage can be implemented in hardware or in software calling modular multiplication.
In the first stage of the two finite field modular inversion algorithms, a multi-bit shifting Montgomery modular inversion algorithm is adopted, the algorithm is evolved from an extended Euclidean algorithm, a multi-bit shifting technology for shifting three bits at most once is adopted, the basic operation called in the technology is only modular addition, modular subtraction and shifting of two finite fields, and the three hardware basic operation units can be realized by hardware.
In a preferred embodiment of the present invention, the first stage may be specifically implemented according to the following steps:
s201, taking the variables u, v, x1, x2 and k, wherein the initial value of the variable u is a2mThe initial value of the variable v is p, the initial value of x1 is 1, the initial value of x2 is 0, and the initial value of k is 0;
s202, judging the lower three bits of the variable v:
if the lowest bit of v is 0, calling a shift operation unit to shift v by one bit to the right, shift x1 by one bit to the left, and k is k + 1;
if the lowest two bits of v are 0, calling a shift operation unit to shift v by two bits to the right, shift x1 by two bits to the left, and shift k to k + 2;
if the lowest three bits of v are 0, calling a shift operation unit to shift v to the right by three bits, x1 to the left by three bits, and k is k + 3;
s203, judging the lower three bits of u:
if the lowest bit of u is 0, calling a shift operation unit to shift u by one bit to the right, x2 by one bit to the left, and k is k + 1;
if the lowest two bits of u are 0, calling a shift operation unit, shifting u by two bits to the right, shifting x2 by two bits to the left, and setting k as k + 2;
if the lowest three bits of u are 0, calling a shift operation unit to shift u to the right by three bits, x2 to the left by three bits, and k is k + 3;
s204, judging the current domain,
if the current domain is the prime domain, calling a modular addition and modular subtraction operation unit of the prime domain to calculate an intermediate variable: x-v-u, y-u-v, z-x 1+ x2, and judges u, v: if v > u, calling a shift operation unit to perform shift operation, wherein v is shifted to the right by one bit, x1 is shifted to the left by one bit, x1 is shifted to the left by one bit, x2 is z, and k is k + 1; if u > v, calling a shift operation unit to perform shift operation, wherein u is right shifted by one, x1 is z, x2 is x2 is left shifted by one, and k is k + 1;
if the current domain is a binary domain, calling a modular addition and modular subtraction operation unit of the binary domain to calculate an intermediate variable: x ^ v ^ u, z ^ x1^ x2, and determining deg (v) and deg (u), where deg (u), deg (v) represent u, v degrees: if deg (v) deg (u), calling the shift operation unit to perform shift operation, wherein v is shifted right by one bit, x1 is shifted left by one bit, x2 is shifted left by one bit, and k is shifted k + 1; if deg (u) deg (v), calling the shift operation unit to perform shift operation, where u equals x shifts right by one bit, x1 equals z, x2 equals x2 shifts left by one bit, and k equals k + 1;
s205, if v is not equal to 0, returning to S202;
s206, judging the current domain,
if the current domain is a prime domain, outputting an operation result of the prime domain modulo inversion and a parameter k: if x1> p, result is x 1-p; if x1< p, result ═ x 1;
if the current domain is a binary domain, calling a binary domain modulo addition, modulo subtraction and shift operation unit, and calculating an intermediate variable: x is p ^ x1, y is 1 and is left shifted by m bits, z is (2 ^ p) ^ x 1; and outputting a binary domain modulo inverse operation result and a parameter k: if y is more than or equal to x, result is x; if y is more than or equal to z, result is z; if none of the above conditions is met, result is x 1.
In a specific implementation process of the method provided by the embodiment of the present invention, a basic flow of a modular inverse control state machine may be as shown in fig. 2, and an explanation of each state in fig. 2 may be as follows:
as can be understood by those skilled in the art, in the specific implementation process of the method provided in the embodiment of the present invention, the modulo inversion control state machine may also adopt other basic flows.
By adopting the technical scheme disclosed by the invention, the following beneficial effects are obtained: the embodiment of the invention provides a hardware realization method of double-domain modular inversion, which adopts a hardware description language to construct a modular inversion control state machine and modular addition, modular subtraction and shift operation units of two finite domains, and the modular addition, modular subtraction and shift operation units of the two finite domains are called by the modular inversion control state machine, so that the hardware realizes the double-domain modular inversion operation of two finite domains of a prime domain and a binary domain.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
It should be understood by those skilled in the art that the timing sequence of the method steps provided in the above embodiments may be adaptively adjusted according to actual situations, or may be concurrently performed according to actual situations.
All or part of the steps in the methods according to the above embodiments may be implemented by a program instructing related hardware, where the program may be stored in a storage medium readable by a computer device and used to execute all or part of the steps in the methods according to the above embodiments. The computer device, for example: personal computer, server, network equipment, intelligent mobile terminal, intelligent home equipment, wearable intelligent equipment, vehicle-mounted intelligent equipment and the like; the storage medium, for example: RAM, ROM, magnetic disk, magnetic tape, optical disk, flash memory, U disk, removable hard disk, memory card, memory stick, network server storage, network cloud storage, etc.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements should also be considered within the scope of the present invention.
Claims (2)
1. A hardware implementation method of dual-domain modular inversion is characterized by comprising the following steps:
s1, modeling an inverse control state machine and a basic operation unit by adopting a hardware description language structure, wherein the basic operation unit comprises: the device comprises a shift operation unit, a modulo addition operation unit of a prime field and a binary field, and a modulo subtraction operation unit of the prime field and the binary field;
s2, the module inverse control state machine realizes the dual-domain module inverse operation of two finite domains of the prime domain and the binary domain by calling module adding, module subtracting and shifting operation units of the prime domain and the binary domain according to the module inverse algorithm flow of the prime domain and the binary domain;
the prime domain and binary domain modular inverse algorithm flow is implemented according to the following two stages:
the first stage is as follows: approximate modular inversion phase with element a2 in the Montgomery domainmThe sum modulus p is input, and an intermediate result is obtained as a-12k-mmod p and a parameter k, which is implemented in hardware by a modulo inverse control state machine by invoking modulo addition, modulo subtraction and shift arithmetic units of a prime field and a binary field, where a2mIs an element in the Montgomery domain, p is a modulus, m is a digit number, n is the most significant bit of p, m ≧ n (2)n-1≤p≤2n)；
The first stage is carried out according to the following steps:
s201, taking the variables u, v, x1, x2 and k, wherein the initial value of the variable u is a2mThe initial value of the variable v is p, the initial value of x1 is 1, the initial value of x2 is 0, and the initial value of k is 0;
s202, judging the lower three bits of the variable v:
if the lowest bit of v is 0, calling a shift operation unit to shift v by one bit to the right, shift x1 by one bit to the left, and k is k + 1;
if the lowest two bits of v are 0, calling a shift operation unit to shift v by two bits to the right, shift x1 by two bits to the left, and shift k to k + 2;
if the lowest three bits of v are 0, calling a shift operation unit to shift v to the right by three bits, x1 to the left by three bits, and k is k + 3;
s203, judging the lower three bits of u:
if the lowest bit of u is 0, calling a shift operation unit to shift u by one bit to the right, x2 by one bit to the left, and k is k + 1;
if the lowest two bits of u are 0, calling a shift operation unit, shifting u by two bits to the right, shifting x2 by two bits to the left, and setting k as k + 2;
if the lowest three bits of u are 0, calling a shift operation unit to shift u to the right by three bits, x2 to the left by three bits, and k is k + 3;
s204, judging the current domain,
if the current domain is the prime domain, the modulo addition of the prime domain is called, and the modulo reduction operation unit calculates an intermediate variable: x-v-u, y-u-v, z-x 1+ x2, and judges u, v: if v > u, calling a shift operation unit to perform shift operation, wherein v is shifted to the right by one bit, x1 is shifted to the left by one bit, x1 is shifted to the left by one bit, x2 is z, and k is k + 1; if u > v, calling a shift operation unit to perform shift operation, wherein u is right shifted by one, x1 is z, x2 is x2 is left shifted by one, and k is k + 1;
if the current domain is a binary domain, calling a modular addition and modular subtraction operation unit of the binary domain to calculate an intermediate variable: x ^ v ^ u, z ^ x1^ x2, and determining deg (v) and deg (u), where deg (u), deg (v) represent u, v degrees: if deg (v) deg (u), calling the shift operation unit to perform shift operation, wherein v is shifted right by one bit, x1 is shifted left by one bit, x2 is shifted left by one bit, and k is shifted k + 1; if deg (u) deg (v), calling the shift operation unit to perform shift operation, where u equals x shifts right by one bit, x1 equals z, x2 equals x2 shifts left by one bit, and k equals k + 1;
s205, if v is not equal to 0, returning to S202;
s206, judging the current domain,
if the current domain is a prime domain, outputting an operation result of the prime domain modulo inversion and a parameter k: if x1> p, result is x 1-p; if x1< p, result ═ x 1;
if the current domain is a binary domain, calling a binary domain modulo addition, modulo subtraction and shift operation unit, and calculating an intermediate variable: x is p ^ x1, y is 1 and is left shifted by m bits, z is (2 ^ p) ^ x 1; and outputting a binary domain modulo inverse operation result and a parameter k: if y is more than or equal to x, result is x; if y is more than or equal to z, result is z; if the conditions y is larger than or equal to x and y is larger than or equal to z, then result is x 1;
and a second stage: a correction stage for outputting the intermediate result a-12k-mmod p to the final result a-12mmod p, this stage can be implemented in hardware or in software calling modular multiplication.
2. The hardware implementation method of the dual-domain modular inversion of claim 1, wherein in S1, the hardware description language is verilog.
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